coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig
by Kane Chen (Code Review) 23 Apr '19

23 Apr '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32337 Change subject: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig ...................................................................... vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig CHROMEOS_SOC_DEBUG_CONSENT config is generally to enable SOC debug capability. Ex: USB DBC debug capability on cnl. Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32337/1 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 26ee31e..0ea5625 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -89,5 +89,9 @@ on normal boot as well as resume and coreboot is only involved in the resume piece w.r.t. the platform hierarchy. +config CHROMEOS_SOC_DEBUG_CONSENT + bool "Enable SOC debug capability" + default n + endif # CHROMEOS endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/32337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Gerrit-Change-Number: 32337 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
by Patrick Georgi (Code Review) 23 Apr '19

23 Apr '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29417 ) Change subject: soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code ...................................................................... soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code Linux remains using SPI1 and PWM ASL even if these devices are disabled. SPI1 and PWM are disabled by Intel FSP. Remove ASL code. BUG=N/A TEST=Boot Ubuntu on Intel CherryHill CRB Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/acpi/lpss.asl 1 file changed, 1 insertion(+), 109 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Michał Żygowski: Looks good to me, approved diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 4cc93cc..f9b376c 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -522,115 +523,6 @@ } } -Device (SPI1) -{ - Name (_HID, "8086228E") - Name (_UID, 1) - Name (_DDN, "SPI Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_SPI_IRQ - } - FixedDMA (0x0, 0x0, Width32Bit, ) - FixedDMA (0x1, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S9B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S9EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S9B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (PWM1) -{ - Name (_HID, "80862288") - Name (_UID, 1) - Name (_DDN, "PWM Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SAB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SAEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (PWM2) -{ - Name (_HID, "80862288") - Name (_UID, 2) - Name (_DDN, "PWM Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SBB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SBEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - Device (UAR1) { Name (_HID, "8086228A") -- To view, visit https://review.coreboot.org/c/coreboot/+/29417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Gerrit-Change-Number: 29417 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: ACPI: Clarify serial bus revision and specific revision
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32329 Change subject: ACPI: Clarify serial bus revision and specific revision ...................................................................... ACPI: Clarify serial bus revision and specific revision Serial bus revision [Byte 3] and serial bus specific revision [Byte 9] are not the same. Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi_device.c M src/arch/x86/include/arch/acpi_device.h 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/32329/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index c57ba48..bdb864c 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -377,7 +377,7 @@ desc_length = acpi_device_write_zero_len(); /* Byte 3: Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_I2C_SERIAL_BUS_REVISION_ID); /* Byte 4: Resource Source Index is Reserved */ acpigen_emit_byte(0); @@ -401,7 +401,7 @@ acpigen_emit_word(i2c->mode_10bit); /* Byte 9: Type Specific Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_I2C_SPECIFIC_REVISION_ID); /* Byte 10-11: I2C Type Data Length */ type_length = acpi_device_write_zero_len(); @@ -435,7 +435,7 @@ desc_length = acpi_device_write_zero_len(); /* Byte 3: Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_SPI_SERIAL_BUS_REVISION_ID); /* Byte 4: Resource Source Index is Reserved */ acpigen_emit_byte(0); @@ -464,7 +464,7 @@ acpigen_emit_word(flags); /* Byte 9: Type Specific Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_SPI_SPECIFIC_REVISION_ID); /* Byte 10-11: SPI Type Data Length */ type_length = acpi_device_write_zero_len(); diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index d26f330..f940ea3 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -311,7 +311,10 @@ #define ACPI_SERIAL_BUS_TYPE_I2C 1 #define ACPI_SERIAL_BUS_TYPE_SPI 2 -#define ACPI_SERIAL_BUS_REVISION_ID 1 +#define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */ +#define ACPI_I2C_SPECIFIC_REVISION_ID 1 +#define ACPI_SPI_SERIAL_BUS_REVISION_ID 1 +#define ACPI_SPI_SPECIFIC_REVISION_ID 1 /* * ACPI I2C Bus -- To view, visit https://review.coreboot.org/c/coreboot/+/32329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb Gerrit-Change-Number: 32329 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Drop pch.h from sandybridge.h
by Patrick Rudolph (Code Review) 23 Apr '19

23 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32065 Change subject: nb/intel/sandybridge: Drop pch.h from sandybridge.h ...................................................................... nb/intel/sandybridge: Drop pch.h from sandybridge.h Include pch.h in the source files instead in sandybridge.h. Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/acpi/pch.asl 4 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32065/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 0d28d67..cb6782e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -25,6 +25,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cbmem.h> #include "chip.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3f62d10..4bfc58d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -29,6 +29,7 @@ #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/smbus.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cpu/x86/msr.h> #include <delay.h> #include <lib.h> diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e315fa4..92cb888 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -52,8 +52,6 @@ #define IOMMU_BASE1 0xfed90000ULL #define IOMMU_BASE2 0xfed91000ULL -#include <southbridge/intel/bd82x6x/pch.h> - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 72e284d..2018219 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -15,6 +15,7 @@ */ /* Intel Cougar Point PCH support */ +#include <southbridge/intel/bd82x6x/pch.h> Scope(\) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Gerrit-Change-Number: 32065 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: soc/intel/cannonlake: Add null refrence check for Cnvi
by Aamir Bohra (Code Review) 23 Apr '19

23 Apr '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32322 Change subject: soc/intel/cannonlake: Add null refrence check for Cnvi ...................................................................... soc/intel/cannonlake: Add null refrence check for Cnvi Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32322/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2688557..994b31c 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -254,11 +254,13 @@ /* Enable CNVi Wifi if enabled in device tree */ dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); + if(dev) { #if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) - params->CnviMode = dev->enabled; + params->CnviMode = dev->enabled; #else - params->PchCnviMode = dev->enabled; + params->PchCnviMode = dev->enabled; #endif + } /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/32322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43 Gerrit-Change-Number: 32322 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

6 18

Change in ...coreboot[master]: crossgcc: Update acpica to version 20190215
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31443 Change subject: crossgcc: Update acpica to version 20190215 ...................................................................... crossgcc: Update acpica to version 20190215 0) Support for ACPI specification version 6.3: Add PCC operation region support for the AML interpreter. This adds PCC operation region support in the AML interpreter and a default handler for acpiexec. The change also renames the PCC region address space keyword to PlatformCommChannel. Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG. These methods provide OSPM with health information and device boot status. PDTT: Add TriggerOrder to the PCC Identifier structure. The field value defines if the trigger needs to be invoked by OSPM before or at the end of kernel crash dump processing/handling operation. SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT is used for describing devices such as heterogeneous processors, accelerators, GPUs, and IO devices with integrated compute or DMA engines. MADT: Add support for statistical profiling in GICC. Statistical profiling extension (SPE) is an architecture-specific feature for ARM. MADT: Add online capable flag. If this bit is set, system hardware supports enabling this processor during OS runtime. New Error Disconnect Recover Notification value. There are a number of scenarios where system Firmware in collaboration with hardware may disconnect one or more devices from the rest of the system for purposes of error containment. Firmware can use this new notification value to alert OSPM of such a removal. PPTT: New additional fields in Processor Structure Flags. These flags provide more information about processor topology. NFIT/Disassembler: Change a field name from "Address Range" to "Region Type". HMAT updates: make several existing fields to be reserved as well as rename subtable 0 to "memory proximity domain attributes". GTDT: Add support for new GTDT Revision 3. This revision adds information for the EL2 timer. iASL: Update the HMAT example template for new fields. iASL: Add support for the new revision of the GTDT (Rev 3). More changes in this version at https://acpica.org/node/166 Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20190215_iasl.patch D util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum 5 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/31443/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index a83302d..b5dd435 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -71,7 +71,7 @@ */ #define COREBOOT_ACPI_ID "BOOT" /* ACPI ID for coreboot HIDs */ -#define ASL_REVISION 20190108 +#define ASL_REVISION 20190215 /* List of ACPI HID that use the coreboot ACPI ID */ enum coreboot_acpi_ids { diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 019b011..c6d7986 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 -IASL_VERSION=20190108 +IASL_VERSION=20190215 PYTHON_VERSION=3.7.2 EXPAT_VERSION=2.2.6 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190215_iasl.patch similarity index 84% rename from util/crossgcc/patches/acpica-unix2-20190108_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190215_iasl.patch index 6532255..c4f6052 100644 --- a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190215_iasl.patch @@ -1,4 +1,4 @@ -diff -Naur acpica-unix2-20190108_/source/compiler/asloptions.c acpica-unix2-20190108/source/compiler/asloptions.c > acpica-unix2-20190108_iasl.patch +diff -Naur acpica-unix2-20190215_/source/compiler/asloptions.c acpica-unix2-20190215/source/compiler/asloptions.c > acpica-unix2-20190215_iasl.patch --- acpica-unix2-20190108_/source/compiler/asloptions.c +++ acpica-unix2-20190108/source/compiler/asloptions.c @@ -126,6 +126,7 @@ diff --git a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum deleted file mode 100644 index c5cfb4c..0000000 --- a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -50d96dd38b89c69260ad209cf61035cda1fcdd67 tarballs/acpica-unix2-20190108.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum new file mode 100644 index 0000000..310454d --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum @@ -0,0 +1 @@ +82d729cb09edc50ee11669651683ca5a5c0f4d5a tarballs/acpica-unix2-20190215.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/31443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Gerrit-Change-Number: 31443 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: crossgcc: Update CMake to version 3.14.1
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32141 Change subject: crossgcc: Update CMake to version 3.14.1 ...................................................................... crossgcc: Update CMake to version 3.14.1 Release Note : https://cmake.org/cmake/help/v3.14/release/3.14.html "The FindFontconfig module added by 3.14.0 accidentally used uppercase FONTCONFIG_* variable names that do not match our conventions. 3.14.1 revises the module to use Fontconfig_* variable names. This is incompatible with 3.14.0 but since the module is new in the 3.14 series usage should not yet be widespread" Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.14.0.tar.gz.cksum A util/crossgcc/sum/cmake-3.14.1.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32141/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 8eaba80..d5f792e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.14.0 +CMAKE_VERSION=3.14.1 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/sum/cmake-3.14.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.0.tar.gz.cksum deleted file mode 100644 index 997b8a0..0000000 --- a/util/crossgcc/sum/cmake-3.14.0.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -30e5423245d98ad98f6ee0c5f73c587846b99d6b tarballs/cmake-3.14.0.tar.gz diff --git a/util/crossgcc/sum/cmake-3.14.1.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.1.tar.gz.cksum new file mode 100644 index 0000000..33c5c23 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.14.1.tar.gz.cksum @@ -0,0 +1 @@ +f4527f8e2f0d2e62e8c4417b64f11a51de9b9d47 tarballs/cmake-3.14.1.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/32141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d Gerrit-Change-Number: 32141 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: crossgcc: Upgrade GCC to version 8.3.0
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31598 Change subject: crossgcc: Upgrade GCC to version 8.3.0 ...................................................................... crossgcc: Upgrade GCC to version 8.3.0 Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-8.3.0_gnat.patch R util/crossgcc/patches/gcc-8.3.0_libgcc.patch R util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch D util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 7 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31598/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c19b766..5536d87 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -50,7 +50,7 @@ GMP_VERSION=6.1.2 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 -GCC_VERSION=8.2.0 +GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 diff --git a/util/crossgcc/patches/gcc-8.2.0_ada-musl_workaround.patch b/util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_ada-musl_workaround.patch rename to util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_gnat.patch b/util/crossgcc/patches/gcc-8.3.0_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_gnat.patch rename to util/crossgcc/patches/gcc-8.3.0_gnat.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_libgcc.patch b/util/crossgcc/patches/gcc-8.3.0_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-8.3.0_libgcc.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_nds32_ite.patch b/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_nds32_ite.patch rename to util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch diff --git a/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum deleted file mode 100644 index 1ef301a..0000000 --- a/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -19926bdb6c4b58891015929853d41aeff019d400 tarballs/gcc-8.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum new file mode 100644 index 0000000..b46ef8c --- /dev/null +++ b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum @@ -0,0 +1 @@ +c27f4499dd263fe4fb01bcc5565917f3698583b2 tarballs/gcc-8.3.0.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/31598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Gerrit-Change-Number: 31598 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: src: include <assert.h> when appropriate
by Patrick Georgi (Code Review) 23 Apr '19

23 Apr '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26796 ) Change subject: src: include <assert.h> when appropriate ...................................................................... src: include <assert.h> when appropriate Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: David Guckian --- M src/arch/arm64/arm_tf.c M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h M src/commonlib/storage/pci_sdhci.c M src/commonlib/storage/sd.c M src/commonlib/storage/sd_mmc.c M src/commonlib/storage/sdhci.c M src/commonlib/storage/sdhci_adma.c M src/commonlib/storage/storage.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/drivers/spi/winbond.c M src/lib/gpio.c M src/mainboard/google/dragonegg/romstage_fsp_params.c M src/mainboard/intel/galileo/vboot.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/security/vboot/vbnv_flash.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/twsi.c M src/soc/cavium/common/ecam.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/gpio_apl.c M src/soc/intel/apollolake/gpio_glk.c M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/denverton_ns/gpio.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/icelake/uart.c M src/soc/intel/quark/spi.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/gpio.c M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/pmic_wrap.c M src/soc/mediatek/mt8183/mt6358.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/rockchip/common/edp.c M src/soc/rockchip/common/pwm.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/bl31_plat_params.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/tsadc.c M src/soc/samsung/exynos5250/alternate_cbfs.c M src/soc/samsung/exynos5250/pinmux.c M src/soc/samsung/exynos5420/alternate_cbfs.c M src/soc/samsung/exynos5420/pinmux.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/lpc47n227/early_serial.c 56 files changed, 4 insertions(+), 53 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index f43bc02..291e4ee 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -18,7 +18,6 @@ #include <arch/mmu.h> #include <arch/transition.h> #include <arm_tf.h> -#include <assert.h> #include <bootmem.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 3f9f994..e283f4d 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -28,6 +28,7 @@ #include <lib.h> #include <string.h> #include <arch/acpigen.h> +#include <assert.h> #include <console/console.h> #include <device/device.h> diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 9e57693..6114667 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -18,7 +18,6 @@ #ifndef LIBACPI_H #define LIBACPI_H -#include <assert.h> #include <stdlib.h> #include <stdint.h> #include <arch/acpi.h> diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index a2d3094..1798c2c 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -18,7 +18,6 @@ #endif #include <arch/early_variables.h> -#include <assert.h> #include <commonlib/sdhci.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 2e1ae85..06f0156 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -19,7 +19,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/storage.h> #include <delay.h> diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index fd59bd0..348d3fe 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -20,7 +20,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <commonlib/storage.h> #include <delay.h> #include <endian.h> diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 5c85e99..19daa2e 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include "bouncebuf.h" #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index bf6f457..e320973 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <commonlib/sdhci.h> #include <commonlib/storage.h> #include <console/console.h> diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index d8ff4bc..f434a6c 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -21,7 +21,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <commonlib/storage.h> #include "sd_mmc.h" #include "storage.h" diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index e634f85..3c3e53a 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <pc80/mc146818rtc.h> #include <smp/spinlock.h> -#include <assert.h> #if CONFIG(PARALLEL_CPU_INIT) #error Intel hyper-threading requires serialized CPU init diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 85b0937..524e49c 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <console/console.h> #include <device/device.h> #include <arch/acpi.h> diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 00f6307..e26701b 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index be08504..11a5187 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -18,7 +18,6 @@ #include <spi_flash.h> #include <spi-generic.h> #include <string.h> -#include <assert.h> #include <delay.h> #include <lib.h> diff --git a/src/lib/gpio.c b/src/lib/gpio.c index ab473cb..8ea3b5e 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <base3.h> #include <console/console.h> #include <delay.h> diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index e357ee7..f2c6851 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <baseboard/variants.h> #include <soc/romstage.h> diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 4b1f09f..8b6706c 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <bootmode.h> #include <device/i2c_simple.h> #include <soc/i2c.h> diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 2b94daa..eca2f0c 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -33,7 +33,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <arch/acpigen.h> -#include <assert.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #if CONFIG(BINARYPI_LEGACY_WRAPPER) diff --git a/src/security/vboot/vbnv_flash.c b/src/security/vboot/vbnv_flash.c index 85cd04a..908846f 100644 --- a/src/security/vboot/vbnv_flash.c +++ b/src/security/vboot/vbnv_flash.c @@ -14,7 +14,6 @@ */ #include <arch/early_variables.h> -#include <assert.h> #include <commonlib/region.h> #include <console/console.h> #include <string.h> diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 6e0cb9c..6659cdf 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -23,7 +23,6 @@ #include <soc/addressmap.h> #include <soc/cavium/common/pci/chip.h> #include <soc/ecam.h> -#include <assert.h> #define CAVM_PCCPF_XXX_VSEC_CTL 0x108 #define CAVM_PCCPF_XXX_VSEC_SCTL 0x10c diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c index d29bcda..7137531 100644 --- a/src/soc/cavium/cn81xx/twsi.c +++ b/src/soc/cavium/cn81xx/twsi.c @@ -20,7 +20,6 @@ #include <soc/clock.h> #include <device/i2c.h> #include <device/i2c_simple.h> -#include <assert.h> #include <delay.h> #include <device/mmio.h> #include <soc/addressmap.h> diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index aaf9085..ae2a91f 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <soc/addressmap.h> #include <soc/ecam.h> -#include <assert.h> /** * Get PCI BAR address from cavium specific extended capability. diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 9696a58..6208c9c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> +#include <assert.h> #include <device/pci_ops.h> #include <cbmem.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index 265e613..b76c9b0 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <intelblocks/gpio.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index 037273c..99f4e4d 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <intelblocks/gpio.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 1a31e20..27be4e6 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -20,7 +20,6 @@ * shouldn't cause any fragmentation. */ -#include <assert.h> #include <console/console.h> #include <intelblocks/uart.h> #include <soc/gpio.h> diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 893f37d..c168da9 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <chip.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 1b72b24..2bd906a 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 3a4a533..2d4cc53 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index b89bf6f..a8e5792 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -14,7 +14,6 @@ */ #include <arch/acpi.h> -#include <assert.h> #include <cbmem.h> #include <console/uart.h> #include <device/device.h> diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c index 30851fd..7c45d40 100644 --- a/src/soc/intel/denverton_ns/gpio.c +++ b/src/soc/intel/denverton_ns/gpio.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <intelblocks/gpio.h> #include <intelblocks/pcr.h> #include <soc/pcr.h> diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index a61370a..b0a2b6c 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <chip.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 1b72b24..2bd906a 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> diff --git a/src/soc/intel/quark/spi.c b/src/soc/intel/quark/spi.c index 7ffa203..0bd0473 100644 --- a/src/soc/intel/quark/spi.c +++ b/src/soc/intel/quark/spi.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> -#include <assert.h> #include <bootstate.h> #include <console/console.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3e77b03..47d4841 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <arch/cpu.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 3d66fa4..39cbde6 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <intelblocks/gpio.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index d039e0b..ff5dd34 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -16,7 +16,6 @@ #ifndef SOC_MEDIATEK_RTC_COMMON_H #define SOC_MEDIATEK_RTC_COMMON_H -#include <assert.h> #include <bcd.h> #include <console/console.h> #include <rtc.h> diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c index 1b8bc5d..6785c0a 100644 --- a/src/soc/mediatek/common/pmic_wrap.c +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <soc/pmic_wrap.h> #include <timer.h> diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 01a32e3..0a8e69b 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <console/console.h> #include <stdlib.h> #include <soc/addressmap.h> diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index d4cd02a..be84668 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <boardid.h> #include <console/console.h> #include <soc/addressmap.h> diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index 6acaee2..af88343 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <console/console.h> #include <delay.h> #include <soc/infracfg.h> diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index d338e16..5803271 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <console/console.h> #include <soc/pmic_wrap.h> #include <soc/mt6358.h> diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index f5c9943..f20dada 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -29,7 +29,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <assert.h> #include <console/console.h> #include <device/i2c_simple.h> #include <stdlib.h> diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index cd57591..c81373f 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. */ -#include <assert.h> #include <console/console.h> #include <device/i2c_simple.h> #include <stdlib.h> diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 98381a0..91e2de9 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <console/console.h> #include <delay.h> #include <device/device.h> diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index ad0453b..e5da05e 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <soc/addressmap.h> #include <soc/grf.h> #include <soc/soc.h> diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 425d302..b4de270 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -20,7 +20,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <console/console.h> #include <delay.h> #include <edid.h> diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index a34105d..3223a4d 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <soc/clock.h> #include <soc/grf.h> #include <soc/pmu.h> diff --git a/src/soc/rockchip/rk3399/bl31_plat_params.c b/src/soc/rockchip/rk3399/bl31_plat_params.c index 647566b..9c11552 100644 --- a/src/soc/rockchip/rk3399/bl31_plat_params.c +++ b/src/soc/rockchip/rk3399/bl31_plat_params.c @@ -15,7 +15,6 @@ */ #include <arm_tf.h> -#include <assert.h> #include <cbmem.h> #include <soc/bl31_plat_params.h> diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index ee8cc2e..cc16563 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <console/console.h> #include <delay.h> #include <device/device.h> diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index d5aeccd..7ec24648 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <assert.h> #include <delay.h> #include <soc/clock.h> #include <soc/grf.h> diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index 9fef9ae..e431672 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <boot_device.h> #include <console/console.h> #include <soc/alternate_cbfs.h> diff --git a/src/soc/samsung/exynos5250/pinmux.c b/src/soc/samsung/exynos5250/pinmux.c index 10c8c95..9ddbea5 100644 --- a/src/soc/samsung/exynos5250/pinmux.c +++ b/src/soc/samsung/exynos5250/pinmux.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <console/console.h> #include <soc/gpio.h> #include <soc/pinmux.h> diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index a1e92a0..ba3f9a3 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -14,7 +14,6 @@ */ #include <arch/cache.h> -#include <assert.h> #include <boot_device.h> #include <console/console.h> #include <soc/alternate_cbfs.h> diff --git a/src/soc/samsung/exynos5420/pinmux.c b/src/soc/samsung/exynos5420/pinmux.c index d8c1378..999afa0 100644 --- a/src/soc/samsung/exynos5420/pinmux.c +++ b/src/soc/samsung/exynos5420/pinmux.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <soc/gpio.h> #include <soc/pinmux.h> #include <stdlib.h> diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index b200855..522d647 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -17,7 +17,6 @@ #include <device/pnp.h> #include <console/console.h> #include <device/smbus.h> -#include <assert.h> #include <stdlib.h> #include <pc80/keyboard.h> diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index c02b850..42213b7 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -17,7 +17,9 @@ /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ #include <arch/io.h> +#include <assert.h> #include <device/pnp_ops.h> + #include "lpc47n227.h" void pnp_enter_conf_state(pnp_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/26796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Gerrit-Change-Number: 26796 Gerrit-PatchSet: 16 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: src: Use include <console/console.h> when appropriate
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32214 Change subject: src: Use include <console/console.h> when appropriate ...................................................................... src: Use include <console/console.h> when appropriate Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/arm_tf.c M src/arch/riscv/boot.c M src/arch/riscv/sbi.c M src/commonlib/storage/sdhci_adma.c M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/device/oprom/include/x86emu/x86emu.h M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/heapmanager.c M src/drivers/amd/agesa/oem_s3.c M src/drivers/amd/agesa/state_machine.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/gpio_regulator/gpio_regulator.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/intel/fsp1_0/fsp_util.h M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/drivers/intel/gma/edid.c M src/drivers/intel/gma/int15.c M src/drivers/lenovo/wacom.c M src/drivers/spi/spi_flash.c M src/include/device/azalia_device.h M src/lib/cbfs.c M src/lib/cbmem_console.c M src/lib/fit.c M src/lib/generic_dump_spd.c M src/mainboard/amd/bettong/BiosCallOuts.c M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c M src/mainboard/amd/lamar/BiosCallOuts.c M src/mainboard/amd/olivehillplus/BiosCallOuts.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/asus/m4a785-m/acpi_tables.c M src/mainboard/bap/ode_e20XX/BiosCallOuts.c M src/mainboard/bap/ode_e21XX/BiosCallOuts.c M src/mainboard/biostar/am1ml/BiosCallOuts.c M src/mainboard/cubietech/cubieboard/bootblock.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dragonegg/romstage_fsp_params.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gru/bootblock.c M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nami/smihandler.c M src/mainboard/google/urara/bootblock.c M src/mainboard/intel/baskingridge/mainboard_smi.c M src/mainboard/intel/cannonlake_rvp/spd/spd_util.c M src/mainboard/intel/icelake_rvp/romstage_fsp_params.c M src/mainboard/intel/icelake_rvp/spd/spd_util.c M src/mainboard/intel/kblrvp/spd/spd_util.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/lippert/frontrunner-af/BiosCallOuts.c M src/mainboard/lippert/toucan-af/BiosCallOuts.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/pcengines/apu1/BiosCallOuts.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/roda/rk886ex/mptable.c M src/mainboard/sifive/hifive-unleashed/mainboard.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/amdht/h3ncmn.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d.h M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct/mcttmrl.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/via/vx900/memmap.c M src/northbridge/via/vx900/pci_util.c M src/northbridge/via/vx900/vx900.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/pi/refcode_loader.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/hob_mem.h M src/soc/intel/fsp_baytrail/i2c.c M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/lpc.c M src/soc/intel/icelake/systemagent.c M src/soc/intel/icelake/uart.c M src/soc/intel/quark/acpi.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/pmic_wrap.c M src/soc/mediatek/mt8183/auxadc.c M src/soc/mediatek/mt8183/mt6358.c M src/soc/nvidia/tegra210/funitcfg.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/gpio.c M src/soc/qualcomm/sdm845/clock.c M src/soc/rockchip/rk3288/crypto.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/amd8111/early_smbus.c M src/southbridge/amd/cimx/sb800/SBPLATFORM.h M src/southbridge/amd/cimx/sb900/SbPlatform.h M src/southbridge/amd/cimx/sb900/cfg.c M src/southbridge/amd/pi/hudson/smbus_spd.c M src/southbridge/amd/sb800/early_setup.c M src/southbridge/broadcom/bcm5785/early_smbus.c M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/mcp55/early_setup_car.c 119 files changed, 79 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32214/1 diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 7cf173b..f43bc02 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -21,6 +21,7 @@ #include <assert.h> #include <bootmem.h> #include <cbfs.h> +#include <console/console.h> #include <program_loading.h> /* diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 29064b1..edf5295 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -17,7 +17,6 @@ #include <vm.h> #include <arch/boot.h> #include <arch/encoding.h> -#include <console/console.h> #include <arch/smp/smp.h> #include <mcall.h> diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index a5f3fd4..e0d7c60 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -20,7 +20,6 @@ #include <sbi.h> #include <vm.h> #include <console/uart.h> -#include <console/console.h> #include <commonlib/helpers.h> static uintptr_t send_ipi(uintptr_t *pmask, intptr_t type) diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index e95742b..09492b7 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -20,6 +20,7 @@ #include <assert.h> #include <commonlib/sdhci.h> #include <commonlib/storage.h> +#include <console/console.h> #include <delay.h> #include <endian.h> #include "sdhci.h" diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 579cae5..2c6e08c 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -89,6 +89,7 @@ */ +#include <console/console.h> #include <cpu/amd/msr.h> #include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h> diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 76bc6d9..719d62f 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/amd/msr.h> #include <device/pci_ops.h> #include "init_cpus.h" diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index d09fc82..5d653d1 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -17,7 +17,6 @@ #define INIT_CPUS_H #include <stdlib.h> -#include <console/console.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index fa23e55..4ae82d9 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -42,7 +42,6 @@ #define __X86EMU_X86EMU_H #include <stddef.h> -#include <console/console.h> #if CONFIG(X86EMU_DEBUG) #define DEBUG #endif diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 92ccff8..81c1f03 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -21,6 +21,7 @@ #include <AGESA.h> #include <amdlib.h> #include "Ids.h" +#include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/dimmSpd.h> diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index a38696f..4740fff 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -16,6 +16,7 @@ #include <amdlib.h> #include <cbmem.h> +#include <console/console.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 586189b..e8806be 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <spi-generic.h> #include <spi_flash.h> #include <string.h> diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index c6e36b2..56c1984 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -21,7 +21,7 @@ #include <arch/cpu.h> #include <bootstate.h> #include <cbfs.h> - +#include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 6e18a8a..2cf8f28 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -15,7 +15,6 @@ #include <arch/acpi_device.h> #include <arch/acpigen.h> -#include <console/console.h> #include <device/device.h> #include <device/path.h> #include <string.h> diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 3b33525..3b7718c 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -15,7 +15,6 @@ #include <arch/acpi_device.h> #include <arch/acpigen.h> -#include <console/console.h> #include <device/device.h> #include <device/path.h> #include <string.h> diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 67760a0..7966875 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/smbus.h> #include <smbios.h> -#include <console/console.h> static void at24rf08c_init(struct device *dev) { diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e0da19e..e09bbd9 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -17,6 +17,8 @@ #define FSP_UTIL_H #include <chipset_fsp_util.h> +#include <console/console.h> + #include "fsp_values.h" #if CONFIG(ENABLE_MRC_CACHE) diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index fe6c4b3..00f6307 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/lapic.h> diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 6c464ee..2c7bf49 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -16,7 +16,6 @@ */ #include <device/mmio.h> -#include <console/console.h> #include <delay.h> #include "i915_reg.h" diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 5caa1b3..2a9e35a 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -16,6 +16,7 @@ #include <x86emu/x86emu.h> #include <arch/interrupt.h> +#include <console/console.h> #include "int15.h" static int active_lfp, pfit, display, panel_type; diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 9dcbf15..aa763a4 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -15,7 +15,6 @@ */ #include <types.h> -#include <console/console.h> #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 71dc660..8e14acb 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -10,6 +10,7 @@ #include <arch/early_variables.h> #include <assert.h> #include <boot_device.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <delay.h> #include <stdlib.h> diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 9ff332e..a56d18e 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -17,7 +17,6 @@ #define DEVICE_AZALIA_H #include <types.h> -#include <console/console.h> #include <arch/acpi.h> #include <device/mmio.h> #include <arch/interrupt.h> diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 728674f..91368fb 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -15,6 +15,7 @@ */ #include <assert.h> +#include <console/console.h> #include <string.h> #include <stdlib.h> #include <boot_device.h> diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index faa937b..df2d1ff 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <console/cbmem_console.h> #include <console/uart.h> #include <cbmem.h> diff --git a/src/lib/fit.c b/src/lib/fit.c index 4e2b75c..a8bca47 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -16,6 +16,7 @@ */ #include <assert.h> +#include <console/console.h> #include <endian.h> #include <stdint.h> #include <bootmem.h> diff --git a/src/lib/generic_dump_spd.c b/src/lib/generic_dump_spd.c index 63e47a2..fdde026 100644 --- a/src/lib/generic_dump_spd.c +++ b/src/lib/generic_dump_spd.c @@ -3,6 +3,8 @@ * It should go away either there or here, depending what fits better. */ +#include <console/console.h> + static void dump_spd_registers(const struct mem_controller *ctrl) { int i; diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 040de9b..eac83d1 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/pci_def.h> #include <device/device.h> #include <AGESA.h> diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index af5d34e..056daa2 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -15,6 +15,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <device/azalia.h> #include <FchPlatform.h> diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 8891abb..8e49e8e 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> #include <stdlib.h> diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index e3107b1..8975dc8 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> #include <stdlib.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 65ed138..583debc 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> +#include <console/console.h> #include <device/pci_ops.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index a1018b3..ce54741 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -17,6 +17,7 @@ #include <device/azalia.h> #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 2727904..f1dc6d9 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <console/console.h> #include <device/pnp_type.h> #include <device/pci_ops.h> diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index 1170ed7..cb263f9 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <device/pci.h> diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 9f7fbf8..7f8b2f0 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 1d86d53..6458b97 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> #include <stdlib.h> diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 43db0d7..17c25ae 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -16,6 +16,7 @@ #include <device/azalia.h> #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index e1eb820..05e3847 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -22,7 +22,6 @@ #include <device/mmio.h> #include <bootblock_common.h> #include <console/uart.h> -#include <console/console.h> #include <delay.h> #include <cpu/allwinner/a10/gpio.h> #include <cpu/allwinner/a10/clock.h> diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 47a7d40..1a9a98e 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <device/pci_ops.h> diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index 1a03f23..b3189f4 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -15,7 +15,6 @@ */ #include <arch/acpi.h> -#include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <cpu/x86/smm.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 65139bb..a08e047 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -14,7 +14,6 @@ */ #include <boot/coreboot_tables.h> -#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <soc/cpu.h> diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index e866c62..e357ee7 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -15,7 +15,6 @@ #include <assert.h> #include <baseboard/variants.h> -#include <console/console.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 024fd4c..ccad3ca 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -15,7 +15,6 @@ */ #include <boot/coreboot_tables.h> -#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <gpio.h> diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 7c18e12..79d9b0f 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <bootblock_common.h> -#include <console/console.h> #include <delay.h> #include <soc/grf.h> #include <gpio.h> diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 6883ab0..cb1f467 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -19,7 +19,6 @@ #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> -#include <console/console.h> #define SKU_UNKNOWN 0xFFFFFFFF diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index f507bd8..2af747e 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -15,7 +15,6 @@ #include <boot/coreboot_tables.h> #include <bootmode.h> -#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <soc/cpu.h> diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 836c97e..dff62c2 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -19,6 +19,7 @@ #include <cbfs.h> #include <chip.h> #include <commonlib/cbfs_serialized.h> +#include <console/console.h> #include <device/device.h> #include <drivers/intel/gma/opregion.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/poppy/variants/nami/smihandler.c b/src/mainboard/google/poppy/variants/nami/smihandler.c index 6816508..56c31e0 100644 --- a/src/mainboard/google/poppy/variants/nami/smihandler.c +++ b/src/mainboard/google/poppy/variants/nami/smihandler.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> -#include <console/console.h> #include <delay.h> #include "gpio.h" diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 5b0b29d..16e7580 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/mmio.h> #include <stdint.h> #include <soc/clocks.h> diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index 0fd0639..da6f8e8 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <arch/io.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 5ceff51..0682a98 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ #include <arch/byteorder.h> -#include <console/console.h> #include <stdint.h> #include <string.h> #include "spd.h" diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index dd33021..fcdc67f 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -14,7 +14,6 @@ */ #include <arch/byteorder.h> -#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> #include "spd/spd.h" diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index 6b73364..b08b3bf 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -14,7 +14,6 @@ */ #include <arch/byteorder.h> #include <arch/cpu.h> -#include <console/console.h> #include <intelblocks/mp_init.h> #include <stdint.h> #include <string.h> diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 12d9d10..b3d7e0b 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ #include <arch/byteorder.h> -#include <console/console.h> #include <stdint.h> #include <string.h> #include <soc/pei_data.h> diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 2edb7da..1b5d45e 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> -#include <console/console.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <stdint.h> diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index eca687c..9ce9ec7 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h> diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 4841008..7e6d0c4 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h> diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 0266eff..89a7075 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -16,6 +16,7 @@ */ #include <arch/io.h> +#include <console/console.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pnp.h> diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 906ecb6..9279047 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 535024a..edacb22 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include <AGESA.h> +#include <console/console.h> #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index cf87d7f..2db0f75 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> -#include <console/console.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <stdint.h> diff --git a/src/mainboard/sifive/hifive-unleashed/mainboard.c b/src/mainboard/sifive/hifive-unleashed/mainboard.c index 2d62cd0..6167504 100644 --- a/src/mainboard/sifive/hifive-unleashed/mainboard.c +++ b/src/mainboard/sifive/hifive-unleashed/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <soc/sdram.h> #include <symbols.h> diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index d29656c..8f58736 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <cbmem.h> #include <cf9_reset.h> +#include <console/console.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index f4a782d..9d3c34e 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -19,7 +19,6 @@ #include <inttypes.h> #include <device/pci.h> -#include <console/console.h> #include <cpu/amd/msr.h> #include "comlib.h" #include "h3finit.h" diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index d956315..8c8c5cf 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -34,6 +34,7 @@ */ #include <string.h> +#include <console/console.h> #include <cpu/amd/msr.h> #include <device/pci_ops.h> #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 5d31d44..e01f253 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -24,7 +24,6 @@ #include <inttypes.h> #include "mct_d_gcc.h" -#include <console/console.h> #include <northbridge/amd/amdfam10/debug.h> #include <northbridge/amd/amdfam10/raminit.h> diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 75fc8a4..de9f8d2 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/x86/cr.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 4689c7b..238bb9f 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/x86/cr.h> #include <cpu/amd/msr.h> #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 192288a..13e54e8 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/x86/cr.h> #include <cpu/amd/msr.h> #include "mct_d.h" diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 1cc7b7c..393b119 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -16,6 +16,7 @@ #include <AGESA.h> #include <cbfs.h> #include <cbmem.h> +#include <console/console.h> #include <delay.h> #include <cpu/x86/mtrr.h> #include <FchPlatform.h> diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 18d9635..668f249 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <console/console.h> #define MCU PCI_DEV(0, 0, 3) diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index afd35a1..07a9a71 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <console/console.h> + #include "vx900.h" #ifdef __SIMPLE_DEVICE__ diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 9e30638..96d821a 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -28,7 +28,6 @@ #include <device/pci_ops.h> #include <device/pci.h> -#include <console/console.h> u32 vx900_get_tolm(void); void vx900_set_chrome9hd_fb_size(u32 size_mb); diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 5295567..5dabc80 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <cbmem.h> +#include <console/console.h> #include <delay.h> #include <timestamp.h> #include <amdblocks/s3_resume.h> diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 0b119b7..6734b55 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -15,6 +15,7 @@ */ #include <cbfs.h> +#include <console/console.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <timer.h> diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 47402b6..3ffaf36 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <cbfs.h> #include <cbmem.h> +#include <console/console.h> #include <rmodule.h> #include <stage_cache.h> #include <amdblocks/agesawrapper.h> diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 1027ae0..d7f9672 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/device.h> #include <device/pci_def.h> #include <amdblocks/BiosCallOuts.h> diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index edd5c239..d688c34 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -21,6 +21,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> +#include <console/console.h> #include <stage_cache.h> #include <arch/bert_storage.h> #include <soc/northbridge.h> diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 63b457c..ed73a6e 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -14,6 +14,7 @@ */ #include <amdblocks/agesawrapper.h> +#include <console/console.h> #include <device/pci_def.h> #include <device/device.h> #include <soc/southbridge.h> diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 07cb2ad..c57f15c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -22,6 +22,7 @@ #include <arch/smp/mpspec.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <gpio.h> #include <intelblocks/acpi.h> diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ba1433c..5d0e196 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -18,6 +18,7 @@ #include <assert.h> #include <cbmem.h> #include "chip.h" +#include <console/console.h> #include <device/pci.h> #include <fsp/memmap.h> #include <intelblocks/smm.h> diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index e8e2661..1a31e20 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -21,6 +21,7 @@ */ #include <assert.h> +#include <console/console.h> #include <intelblocks/uart.h> #include <soc/gpio.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 421cafc..1b72b24 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> #include <intelblocks/lpss.h> diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c872e51..3a34c79 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -20,6 +20,7 @@ #include <bootstate.h> #include <cbmem.h> #include <cf9_reset.h> +#include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 342a120..0a59c56 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -15,6 +15,7 @@ #include <assert.h> #include <bootstate.h> +#include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 0065a6c..47e2817 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -13,7 +13,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include <assert.h> +#include <console/console.h> #include <intelblocks/gpio.h> #include <gpio.h> #include <intelblocks/itss.h> diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index f3e91ff..e969a04 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> - +#include <console/console.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/intel/denverton_ns/include/soc/hob_mem.h b/src/soc/intel/denverton_ns/include/soc/hob_mem.h index d98295b..44d73fa 100644 --- a/src/soc/intel/denverton_ns/include/soc/hob_mem.h +++ b/src/soc/intel/denverton_ns/include/soc/hob_mem.h @@ -19,6 +19,7 @@ #ifndef _DENVERTON_NS_HOB_MEM_H #define _DENVERTON_NS_HOB_MEM_H +#include <console/console.h> #include <fsp/util.h> void soc_display_fsp_smbios_memory_info_hob( diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index 68f5626..d368d8b 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> #include <soc/baytrail.h> diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h index 7b3a3c8..f0ae0b3 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h +++ b/src/soc/intel/fsp_baytrail/include/soc/i2c.h @@ -16,7 +16,6 @@ #ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ #define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ -#include <console/console.h> #include <device/pci_def.h> #include <stdlib.h> diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 2d35f5b..0940791 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 0e4388e..464c25e 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -14,7 +14,6 @@ */ #include <chip.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/lpc.c index a3bce93..ac66d9b 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/lpc.c @@ -14,7 +14,6 @@ */ #include "chip.h" -#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index 7903667..930e78e 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/systemagent.h> diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 421cafc..1b72b24 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> #include <intelblocks/lpss.h> diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 83bed34..2cb5adf 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <soc/acpi.h> #include <soc/ramstage.h> diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 3e7186a..334a757 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/mmio.h> #include <assert.h> #include <endian.h> diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 9e4cb11..636f895 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -15,6 +15,7 @@ #include <device/mmio.h> #include <assert.h> +#include <console/console.h> #include <delay.h> #include <stdlib.h> #include <soc/addressmap.h> diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index 469653a..6acaee2 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -15,6 +15,7 @@ #include <device/mmio.h> #include <assert.h> +#include <console/console.h> #include <delay.h> #include <soc/infracfg.h> #include <soc/pmic_wrap.h> diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c index caf9a03..a167d2b 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <assert.h> -#include <console/console.h> #include <delay.h> #include <soc/addressmap.h> #include <soc/auxadc.h> diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 3dc9fe2..d338e16 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <soc/pmic_wrap.h> #include <soc/mt6358.h> diff --git a/src/soc/nvidia/tegra210/funitcfg.c b/src/soc/nvidia/tegra210/funitcfg.c index a218862..887f9f0 100644 --- a/src/soc/nvidia/tegra210/funitcfg.c +++ b/src/soc/nvidia/tegra210/funitcfg.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/funitcfg.h> diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 54f4204..13fa1c6 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -15,6 +15,7 @@ #include <arch/lib_helpers.h> #include <arch/stages.h> +#include <console/console.h> #include <device/mmio.h> #include <gic.h> #include <soc/addressmap.h> diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index fe2d673..66c3103 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -33,7 +33,6 @@ #include <device/mmio.h> #include <boot/coreboot_tables.h> -#include <console/console.h> #include <console/uart.h> #include <delay.h> #include <gpio.h> diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 31fdc3d..8034d2e 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -14,7 +14,6 @@ #include <device/mmio.h> #include <types.h> -#include <console/console.h> #include <delay.h> #include <timer.h> #include <timestamp.h> diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index db8b7a1..66e0ba8 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <types.h> -#include <console/console.h> #include <delay.h> #include <timer.h> #include <timestamp.h> diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index bdbcfb8..177ddb3 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <types.h> -#include <console/console.h> #include <delay.h> #include <timer.h> #include <commonlib/helpers.h> diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index 90275ff..09c9c4b 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/mmio.h> #include <assert.h> #include <delay.h> diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 8a07565..efc35bd 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -18,7 +18,7 @@ #include <device/device.h> #include "hudson.h" #include <AGESA.h> - +#include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> extern FCH_DATA_BLOCK InitEnvCfgDefault; diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index cb2fbe7..3fb4797 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/pci_def.h> #include <device/device.h> diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index 2e6781a..bb3fb88 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <console/console.h> #include <device/pci_ops.h> #include "amd8111_smbus.h" diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 04b8abc..7ea2caa 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -53,7 +53,6 @@ #define IMC_ENABLE_OVER_WRITE 0x01 #endif -#include <console/console.h> #include "AmdSbLib.h" #include "Amd.h" #include <SB800.h> diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 660553f..f5c11d4 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -49,7 +49,6 @@ #endif #define FIXUP_PTR(ptr) ptr -#include <console/console.h> #include "AmdSbLib.h" #include "Amd.h" #include "Hudson-2.h" diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index bc7e742..a4ba798 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ - +#include <console/console.h> #include <string.h> #include "SbPlatform.h" #include "platform_cfg.h" diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index 8d67b1e..f75966e 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/pci_def.h> #include <device/device.h> diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 6a575e3..cf66069 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -17,6 +17,7 @@ #define _SB800_EARLY_SETUP_C_ #include <arch/io.h> +#include <console/console.h> #include <reset.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/reset.h> diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index bcbfb12..444772b 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <console/console.h> #include <device/pci_ops.h> #include "smbus.h" diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 1e357df..156c387 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -17,6 +17,7 @@ */ #include <arch/io.h> +#include <console/console.h> #include <reset.h> #include <southbridge/amd/common/reset.h> diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 3099a09..9a3eb27 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -16,6 +16,7 @@ */ #include <arch/io.h> +#include <console/console.h> #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); -- To view, visit https://review.coreboot.org/c/coreboot/+/32214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Gerrit-Change-Number: 32214 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019