coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src/{arch/arm64,soc/intel}: Add missing include 'console.h'
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32122 Change subject: src/{arch/arm64,soc/intel}: Add missing include 'console.h' ...................................................................... src/{arch/arm64,soc/intel}: Add missing include 'console.h' Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/arm_tf.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/icelake/uart.c M src/soc/intel/quark/acpi.c 7 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32122/1 diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 7cf173b..f43bc02 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -21,6 +21,7 @@ #include <assert.h> #include <bootmem.h> #include <cbfs.h> +#include <console/console.h> #include <program_loading.h> /* diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 07cb2ad..9696a58 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <arch/acpigen.h> +#include <console/console.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <device/pci_ops.h> @@ -34,6 +35,7 @@ #include <soc/pci_devs.h> #include <soc/systemagent.h> #include <string.h> + #include "chip.h" #define CSTATE_RES(address_space, width, offset, address) \ diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index e8e2661..1a31e20 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -21,6 +21,7 @@ */ #include <assert.h> +#include <console/console.h> #include <intelblocks/uart.h> #include <soc/gpio.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 421cafc..1b72b24 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> #include <intelblocks/lpss.h> diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index f3e91ff..e969a04 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> - +#include <console/console.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 421cafc..1b72b24 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> #include <intelblocks/lpss.h> diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 83bed34..2cb5adf 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <soc/acpi.h> #include <soc/ramstage.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Gerrit-Change-Number: 32122 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx/lpc: Use macros instead of magic numbers
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31310 Change subject: sb/intel/i82801gx/lpc: Use macros instead of magic numbers ...................................................................... sb/intel/i82801gx/lpc: Use macros instead of magic numbers Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/lpc.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31310/1 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7497c79..25e5ec7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -259,12 +259,12 @@ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 = inl(pmbase + PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 1); // enable C3->C0 transition on bus master - reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + reg32 |= BM_RLD; // enable C3->C0 transition on bus master + reg32 |= SCI_EN; + outl(reg32, pmbase + PM1_CNT); } static void i82801gx_configure_cstates(struct device *dev) @@ -489,11 +489,11 @@ fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x20; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x28; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; @@ -531,7 +531,7 @@ fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 0; @@ -545,21 +545,21 @@ fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Gerrit-Change-Number: 31310 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config
by Arthur Heymans (Code Review) 23 Apr '19

23 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32310 Change subject: src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config ...................................................................... src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config The pci_or_configx function makes the code shorter and more readable. Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/romstage.c 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32310/1 diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index ecff4b9..cdd12dc 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -28,8 +28,7 @@ /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index c91d40e..024c3e1 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -28,8 +28,7 @@ /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/32310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd Gerrit-Change-Number: 32310 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Klocwork: Fix the Null pointer derefernce found by klocwork
by Thejaswani Putta (Code Review) 23 Apr '19

23 Apr '19

Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32290 Change subject: Klocwork: Fix the Null pointer derefernce found by klocwork ...................................................................... Klocwork: Fix the Null pointer derefernce found by klocwork Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4 --- M src/lib/coreboot_table.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32290/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6e44f5d..808cfa7 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -233,8 +233,11 @@ vbwb = (struct lb_range *)lb_new_record(header); vbwb->tag = LB_TAB_VBOOT_WORKBUF; vbwb->size = sizeof(*vbwb); - vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; - vbwb->range_size = wd->buffer_size; + if(wd) + { + vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; + vbwb->range_size = wd->buffer_size; + } } __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4 Gerrit-Change-Number: 32290 Gerrit-PatchSet: 1 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to suppor...
by Robin Broda (Code Review) 23 Apr '19

23 Apr '19

Robin Broda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32285 Change subject: util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI devices ...................................................................... util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI devices Signed-off-by: Robin Broda <robin(a)broda.me> Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666 --- M util/intelmetool/intelmetool.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/32285/1 diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index ed86b23..27bf46d 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -454,6 +454,7 @@ #define PCI_DEVICE_ID_INTEL_LEWISBURG_IE1 0xA1F8 /* IE Lewisburg #1 */ #define PCI_DEVICE_ID_INTEL_LEWISBURG_IE2 0xA1F9 /* IE Lewisburg #2 */ #define PCI_DEVICE_ID_INTEL_LEWISBURG_IE3 0xA1FC /* IE Lewisburg #3 */ +#define PCI_DEVICE_ID_INTEL_CANNONLAKE 0xA360 /* Cannon Lake */ #define PCI_DEV_HAS_SUPPORTED_ME(x) ( \ ((x) == PCI_DEVICE_ID_INTEL_COUGARPOINT_1) || \ @@ -505,6 +506,7 @@ ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE1) || \ ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE2) || \ ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE3) || \ + ((x) == PCI_DEVICE_ID_INTEL_CANNONLAKE) || \ 0) #define BOOTGUARD_DISABLED 0x400000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/32285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666 Gerrit-Change-Number: 32285 Gerrit-PatchSet: 1 Gerrit-Owner: Robin Broda Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/U-Boot: Update to the latest stable 2019.4
by Arthur Heymans (Code Review) 23 Apr '19

23 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32306 Change subject: payloads/U-Boot: Update to the latest stable 2019.4 ...................................................................... payloads/U-Boot: Update to the latest stable 2019.4 Change-Id: I4740aa80e3c0faf9b18730390af778abcc92aac3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/U-Boot/Kconfig M payloads/external/U-Boot/Makefile 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/32306/1 diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index 2afe1cd..a2bc512 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -9,7 +9,7 @@ default UBOOT_STABLE config UBOOT_STABLE - bool "v2016.1" + bool "v2019.4" help Stable U-Boot version diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index b47e74c..5cd8956 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -13,8 +13,8 @@ ## GNU General Public License for more details. ## -# 2016-1 tag -STABLE_COMMIT_ID=fa85e826c16b9ce1ad302a57e9c4b24db0d8b930 +# 2019-4 tag +STABLE_COMMIT_ID=3c99166441bf3ea325af2da83cfe65430b49c066 TAG-$(CONFIG_UBOOT_MASTER)=origin/master TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID) -- To view, visit https://review.coreboot.org/c/coreboot/+/32306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4740aa80e3c0faf9b18730390af778abcc92aac3 Gerrit-Change-Number: 32306 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payload/U-Boot: Fix generating a default config on the master branch
by Arthur Heymans (Code Review) 23 Apr '19

23 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32305 Change subject: payload/U-Boot: Fix generating a default config on the master branch ...................................................................... payload/U-Boot: Fix generating a default config on the master branch The name of the default configuration file for x86 coreboot changed. Change-Id: I6544142a70bd3e1e13ee52eccbd5335f8375a4f6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/U-Boot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32305/1 diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index c17b67f..b47e74c 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -65,7 +65,7 @@ false endif else - cat $(project_dir)/configs/coreboot-x86_defconfig >> $(project_config_file) + cat $(project_dir)/configs/coreboot_defconfig >> $(project_config_file) endif $(MAKE) -C $(project_dir) olddefconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/32305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6544142a70bd3e1e13ee52eccbd5335f8375a4f6 Gerrit-Change-Number: 32305 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/U-Boot: Use a phony target for checking out a revision
by Arthur Heymans (Code Review) 23 Apr '19

23 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32304 Change subject: payloads/U-Boot: Use a phony target for checking out a revision ...................................................................... payloads/U-Boot: Use a phony target for checking out a revision Change-Id: I5ea4df33545f69c06e4ae2158a1a6c14ead784a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/U-Boot/Makefile 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32304/1 diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 653662f..c17b67f 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -51,11 +51,11 @@ touch $(project_dir)/$(STABLE_COMMIT_ID) endif -$(project_dir)/tag-$(TAG-y): fetch +checkout: fetch echo " Checking out $(project_name) revision $(TAG-y)" cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) -config: $(project_dir)/$(TAG-y) +config: checkout rm -f $(project_config_file) ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),) ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","") @@ -83,4 +83,4 @@ print-repo-info: echo "$(project_git_repo) $(project_dir)" -.PHONY: config build clean distclean fetch print-repo-info +.PHONY: checkout config build clean distclean fetch print-repo-info -- To view, visit https://review.coreboot.org/c/coreboot/+/32304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ea4df33545f69c06e4ae2158a1a6c14ead784a7 Gerrit-Change-Number: 32304 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: payloads/U-Boot: Unexport the coreboot_exports
by Arthur Heymans (Code Review) 23 Apr '19

23 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32303 Change subject: payloads/U-Boot: Unexport the coreboot_exports ...................................................................... payloads/U-Boot: Unexport the coreboot_exports Without this U-Boot ends up overwriting the coreboot .config when generating a configfile. Change-Id: I62fc0aa3ede0287ffc96915182a2ed5a4877f29d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/U-Boot/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/32303/1 diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 67c60c1..653662f 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -30,6 +30,7 @@ unexport KCONFIG_SPLITCONFIG unexport KCONFIG_TRISTATE unexport KCONFIG_NEGATIVES +unexport $(COREBOOT_EXPORTS) all: build -- To view, visit https://review.coreboot.org/c/coreboot/+/32303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62fc0aa3ede0287ffc96915182a2ed5a4877f29d Gerrit-Change-Number: 32303 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Add keyboard backlight support for Droid/Blorb
by Sheng-Liang Pan (Code Review) 23 Apr '19

23 Apr '19

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32298 Change subject: mb/google/octopus: Add keyboard backlight support for Droid/Blorb ...................................................................... mb/google/octopus: Add keyboard backlight support for Droid/Blorb Droid/Blorb supports keyboard backlight feature, so enable the ASL code. BUG=b:130330141 BRANCH=octopus TEST=Build and boot to OS, verify that the string 'KBLT' is in the DSDT. Change-Id: I74684e3905d34b61fa4b851798dbca018f986e5a Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bobba/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/32298/1 diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h index 16f931b..196d52e 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74684e3905d34b61fa4b851798dbca018f986e5a Gerrit-Change-Number: 32298 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019