coreboot-gerrit April 2019

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Change in ...coreboot[master]: configs: Add a target to buildtest the ivybridge mrc.bin bootpath
by Arthur Heymans (Code Review) 23 Apr '19

23 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32384 Change subject: configs: Add a target to buildtest the ivybridge mrc.bin bootpath ...................................................................... configs: Add a target to buildtest the ivybridge mrc.bin bootpath Change-Id: Iff15e9586cd3e39850d986582b5943cbb8a184a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A configs/config.lenovo_x220_mrc_bin 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32384/1 diff --git a/configs/config.lenovo_x220_mrc_bin b/configs/config.lenovo_x220_mrc_bin new file mode 100644 index 0000000..a51c498 --- /dev/null +++ b/configs/config.lenovo_x220_mrc_bin @@ -0,0 +1,3 @@ +CONFIG_VENDOR_LENOVO=y +CONFIG_BOARD_LENOVO_X220=y +# CONFIG_USE_NATIVE_RAMINIT is not set -- To view, visit https://review.coreboot.org/c/coreboot/+/32384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff15e9586cd3e39850d986582b5943cbb8a184a7 Gerrit-Change-Number: 32384 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TEST]arch/x86/car.ld: Make the vboot tpm log symbols conditional
by Arthur Heymans (Code Review) 23 Apr '19

23 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32383 Change subject: [TEST]arch/x86/car.ld: Make the vboot tpm log symbols conditional ...................................................................... [TEST]arch/x86/car.ld: Make the vboot tpm log symbols conditional Without vboot there is no need for these symbols. Change-Id: I96391b7817c79f760713c67bc469164b5514879e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32383/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 37fb087..93803a1 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -34,7 +34,9 @@ /* Vboot measured boot TCPA log measurements. * Needs to be transferred until CBMEM is available */ +#if CONFIG(VBOOT) VBOOT2_TPM_LOG(., 2K) +#endif /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96391b7817c79f760713c67bc469164b5514879e Gerrit-Change-Number: 32383 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Check if interleaved even if rank[4] size is zero
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31007 Change subject: nb/intel/i945: Check if interleaved even if rank[4] size is zero ...................................................................... nb/intel/i945: Check if interleaved even if rank[4] size is zero With this patch, the board can boot when interleaved but rank4 is 0. Tested on 945G-M4, it boot when: DIMM0 + DIMM2 populated: Ok DIMM0 + DIMM3 populated: Ok DIMM1 + DIMM2 populated: Ok DIMM1 + DIMM3 populated: Ok raminit.c still needs channelA populated. It will not boot if channel A is not populated. Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31007/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..a46677b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2551,9 +2551,6 @@ u32 bankaddr = 0, tmpaddr, mrsaddr = 0; for (i = 0, nonzero = -1; i < 8; i++) { - if (sysinfo->banksize[i] == 0) - continue; - printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i); switch (i) { case 0: @@ -2576,6 +2573,9 @@ bankaddr = 0; } + if (sysinfo->banksize[i] == 0) + continue; + /* We have a bank with a non-zero size.. Remember it * for the next offset we have to calculate */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Gerrit-Change-Number: 31007 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x: fix linking for non-native raminit case
by Matt DeVillier (Code Review) 23 Apr '19

23 Apr '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32382 Change subject: sb/intel/bd82x6x: fix linking for non-native raminit case ...................................................................... sb/intel/bd82x6x: fix linking for non-native raminit case Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x] moved early_pch_init() to the southbridge, but failed to include early_pch.c for the non-native raminit case, which now fails to link. As all boards default to native raminit, this was missed by the autobuilder. Adjust early_pch.c to be compiled regardles of ram init type used Test: build/boot google/stout with MRC ram init selected Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32382/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 7ce3da7..a950e5c 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -40,9 +40,10 @@ romstage-y += early_smbus.c me_status.c romstage-y += early_spi.c romstage-y += early_rcba.c +romstage-y += early_pch.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) -romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c +romstage-y += early_thermal.c early_me.c early_usb.c else romstage-y += early_me_mrc.c early_usb_mrc.c endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233 Gerrit-Change-Number: 32382 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ic7/i945: Use full_reset()
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32377 Change subject: ic7/i945: Use full_reset() ...................................................................... ic7/i945: Use full_reset() For full reset, use already defined full_reset() function. Change-Id: Iec7dcf285f3cb1cdc8f48d348ff8496879625db5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32377/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index be3d17a..d41b913 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -19,6 +19,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> #include <lib.h> @@ -272,9 +273,7 @@ if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); - outb(0x00, 0xcf9); - outb(0x0e, 0xcf9); - halt(); /* Wait for reset! */ + full_reset(); } } @@ -303,9 +302,7 @@ if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); - outb(0x00, 0xcf9); - outb(0x0e, 0xcf9); - halt(); /* Wait for reset! */ + full_reset(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec7dcf285f3cb1cdc8f48d348ff8496879625db5 Gerrit-Change-Number: 32377 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
by Patrick Georgi (Code Review) 23 Apr '19

23 Apr '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30315 ) Change subject: sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock ...................................................................... sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock This allows for serial console during the bootblock and enables console in general for the bootblock. Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asrock/h81m-hds/Makefile.inc A src/mainboard/asrock/h81m-hds/bootblock.c M src/mainboard/asrock/h81m-hds/romstage.c M src/northbridge/intel/haswell/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c 7 files changed, 56 insertions(+), 37 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Duncan Laurie: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index 7c1bf9e..de18bc5 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,3 +16,4 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/h81m-hds/bootblock.c b/src/mainboard/asrock/h81m-hds/bootblock.c new file mode 100644 index 0000000..7a841b8 --- /dev/null +++ b/src/mainboard/asrock/h81m-hds/bootblock.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + /* + * Don't know what's needed here, just set the same as the vendor + * firmware. + */ + pnp_set_logical_device(IR_DEV); + pnp_write_config(IR_DEV, 0xf1, 0x5c); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index a917722..3af82f2 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -23,8 +23,6 @@ #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -41,35 +39,6 @@ RCBA_END_CONFIG, }; -void mainboard_config_superio(void) -{ - const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); - const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); - const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); - const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); - - /* Select HWM/LED functions instead of floppy functions. */ - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); - - /* Power RAM in S3 and let the PCH handle power failure actions. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x70); - - /* - * Don't know what's needed here, just set the same as the vendor - * firmware. - */ - pnp_set_logical_device(IR_DEV); - pnp_write_config(IR_DEV, 0xf1, 0x5c); - - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e0c55d2..49466bc 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -23,7 +23,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK -# select BOOTBLOCK_CONSOLE TODO: route LPC + select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index fd00f6c..04e0bc9 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -46,6 +46,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c +bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-y += early_spi.c rcba.c pmutil.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 69fdd61..39e6925 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -79,4 +79,7 @@ /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_enable_lpc(); + mainboard_config_superio(); } diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index f615507..c362577 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -104,8 +104,6 @@ { int wake_from_s3; - pch_enable_lpc(); - pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) @@ -113,9 +111,6 @@ #else setup_pch_gpios(gpio_map); #endif - - mainboard_config_superio(); - pch_generic_setup(); /* Enable SMBus for reading SPDs. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 Gerrit-Change-Number: 30315 Gerrit-PatchSet: 48 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/amd/common: Remove AmdReadEventLog()
by Kyösti Mälkki (Code Review) 23 Apr '19

23 Apr '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31484 Change subject: soc/amd/common: Remove AmdReadEventLog() ...................................................................... soc/amd/common: Remove AmdReadEventLog() Parameter passing is incorrect here, it should pass complete StdHeader instead of attempting to fill in HeapStatus that should be treated as a field private to AGESA, based on where it is defined in the header files. Furthermore the while() loop did not evaluate the return value. Feature can be brought back at a later date after someone verifies it actually works correctly across different stages. Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c 2 files changed, 0 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31484/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 1726955..fb33f4d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -42,34 +42,6 @@ static void *AcpiIvrs; static void *AcpiCrat; -static AGESA_STATUS agesawrapper_readeventlog(uint8_t HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams = { - .StdHeader.CalloutPtr = &GetBiosCallout, - .StdHeader.HeapStatus = HeapStatus, - }; - - Status = AmdReadEventLog(&AmdEventParams); - if (AmdEventParams.EventClass) - printk(BIOS_DEBUG, "AGESA Event Log:\n"); - - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, " Class = %x, Info = %x," - " Param1 = 0x%x, Param2 = 0x%x" - " Param3 = 0x%x, Param4 = 0x%x\n", - (u32)AmdEventParams.EventClass, - (u32)AmdEventParams.EventInfo, - (u32)AmdEventParams.DataParam1, - (u32)AmdEventParams.DataParam2, - (u32)AmdEventParams.DataParam3, - (u32)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} - static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) { /* Should clone entire StdHeader here. */ @@ -108,8 +80,6 @@ status = AmdInitReset(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -131,8 +101,6 @@ status = AmdInitEarly(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -219,8 +187,6 @@ print_init_post_settings(PostParams); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(PostParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -243,8 +209,6 @@ status = AmdInitEnv(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -296,8 +260,6 @@ status = AmdInitMid(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -328,11 +290,6 @@ Status = AmdInitLate(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(LateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - DmiTable = LateParams->DmiTable; AcpiPstate = LateParams->AcpiPState; @@ -372,11 +329,6 @@ Status = AmdInitRtb(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - if (save_s3_info(RtbParams->S3DataBlock.NvStorage, RtbParams->S3DataBlock.NvStorageSize, RtbParams->S3DataBlock.VolatileStorage, @@ -406,8 +358,6 @@ status = AmdInitResume(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -436,10 +386,6 @@ Status = AmdS3LateRestore(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } AmdReleaseStruct(&AmdParamStruct); return Status; @@ -466,10 +412,6 @@ Status = AmdS3FinalRestore(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } AmdReleaseStruct(&AmdParamStruct); return Status; diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index c42df59..2efee4e 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -226,17 +226,3 @@ if (!Dispatcher) return AGESA_UNSUPPORTED; return Dispatcher(AmdApExeParams); } - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - Event->StdHeader.Func = AMD_READ_EVENT_LOG; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(Event); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5 Gerrit-Change-Number: 31484 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: soc/amd/common: Introduce agesa_execute_state()
by Kyösti Mälkki (Code Review) 23 Apr '19

23 Apr '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31483 Change subject: soc/amd/common: Introduce agesa_execute_state() ...................................................................... soc/amd/common: Introduce agesa_execute_state() Each entrypoint to AGESA goes through the same sequence and have same the function signature. To avoid introducing bunch of preprocessor magic, rename all the agesawrapper_amdXXX() functions that are actual entrypoints to AGESA API, make them static, and provide a single exposed entry function agesa_execute_state(). Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/amd_late_init.c M src/soc/amd/common/block/pi/amd_resume_final.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c 8 files changed, 76 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31483/1 diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 2f3b8a6..04db424 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -34,22 +34,11 @@ /* Return current dispatcher or NULL on error. */ MODULE_ENTRY agesa_get_dispatcher(void); +AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func); AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams); -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); void *agesawrapper_getlateinitptr(int pick); -AGESA_STATUS agesawrapper_amdinitrtb(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amds3finalrestore(void); -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly); void amd_initcpuio(void); diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h index 1188f05..86e32af 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h @@ -42,11 +42,11 @@ return statusStrings[sret]; } -static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) +static inline u32 do_agesawrapper(AGESA_STRUCT_NAME func, const char *name) { AGESA_STATUS ret; printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); - ret = func(); + ret = agesa_execute_state(func); printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", name, decodeAGESA_STATUS(ret)); return (u32)ret; diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index fc69b46..1726955 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2018 Kyösti Mälkki + * Copyright (C) 2018 - 2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -89,7 +89,7 @@ return interface_struct->NewStructPtr; } -AGESA_STATUS agesawrapper_amdinitreset(void) +static AGESA_STATUS amd_init_reset(void) { AGESA_STATUS status; AMD_RESET_PARAMS _ResetParams; @@ -114,7 +114,7 @@ return status; } -AGESA_STATUS agesawrapper_amdinitearly(void) +static AGESA_STATUS amd_init_early(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -171,7 +171,7 @@ uma_size / MiB, uma_start); } -AGESA_STATUS agesawrapper_amdinitpost(void) +static AGESA_STATUS amd_init_post(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -226,7 +226,7 @@ return status; } -AGESA_STATUS agesawrapper_amdinitenv(void) +static AGESA_STATUS amd_init_env(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -276,7 +276,7 @@ } } -AGESA_STATUS agesawrapper_amdinitmid(void) +static AGESA_STATUS amd_init_mid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -303,7 +303,7 @@ return status; } -AGESA_STATUS agesawrapper_amdinitlate(void) +static AGESA_STATUS amd_init_late(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -358,7 +358,7 @@ return AmdLateRunApTask(ApExeParams); } -AGESA_STATUS agesawrapper_amdinitrtb(void) +static AGESA_STATUS amd_init_rtb(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -388,7 +388,7 @@ return Status; } -AGESA_STATUS agesawrapper_amdinitresume(void) +static AGESA_STATUS amd_init_resume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -413,7 +413,7 @@ return status; } -AGESA_STATUS agesawrapper_amds3laterestore(void) +static AGESA_STATUS amd_s3late_restore(void) { AGESA_STATUS Status; AMD_S3LATE_PARAMS _S3LateParams; @@ -445,7 +445,7 @@ return Status; } -AGESA_STATUS agesawrapper_amds3finalrestore(void) +static AGESA_STATUS amd_s3final_restore(void) { AGESA_STATUS Status; AMD_S3FINAL_PARAMS _S3FinalParams; @@ -474,3 +474,55 @@ return Status; } + +static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) +{ + switch (StdHeader->Func) { + case AMD_INIT_RESET: + return amd_init_reset(); + case AMD_INIT_EARLY: + return amd_init_early(); + case AMD_INIT_POST: + return amd_init_post(); + case AMD_INIT_RESUME: + return amd_init_resume(); + default: + return AGESA_UNSUPPORTED; + } +} + +static AGESA_STATUS ramstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) +{ + switch (StdHeader->Func) { + case AMD_INIT_ENV: + return amd_init_env(); + case AMD_INIT_MID: + return amd_init_mid(); + case AMD_INIT_LATE: + return amd_init_late(); + case AMD_INIT_RTB: + return amd_init_rtb(); + case AMD_S3LATE_RESTORE: + return amd_s3late_restore(); + case AMD_S3FINAL_RESTORE: + return amd_s3final_restore(); + default: + return AGESA_UNSUPPORTED; + } +} + +AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) +{ + AGESA_STATUS status = AGESA_UNSUPPORTED; + AMD_CONFIG_PARAMS template = {}; + AMD_CONFIG_PARAMS *StdHeader = &template; + + StdHeader->Func = func; + + if (ENV_ROMSTAGE) + status = romstage_dispatch(StdHeader); + if (ENV_RAMSTAGE) + status = ramstage_dispatch(StdHeader); + + return status; +} diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 68cf3a1..81d42b7 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -178,12 +178,12 @@ if (acpi_is_wakeup_s3()) return; - do_agesawrapper(agesawrapper_amdinitlate, "amdinitlate"); + do_agesawrapper(AMD_INIT_LATE, "amdinitlate"); if (!acpi_s3_resume_allowed()) return; - do_agesawrapper(agesawrapper_amdinitrtb, "amdinitrtb"); + do_agesawrapper(AMD_INIT_RTB, "amdinitrtb"); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c index a282665..363ba83 100644 --- a/src/soc/amd/common/block/pi/amd_resume_final.c +++ b/src/soc/amd/common/block/pi/amd_resume_final.c @@ -18,7 +18,7 @@ static void agesawrapper_s3finalrestore(void *unused) { - do_agesawrapper(agesawrapper_amds3finalrestore, "amds3finalrestore"); + do_agesawrapper(AMD_S3FINAL_RESTORE, "amds3finalrestore"); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index a29c56c..0ecd3e9 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -163,12 +163,11 @@ psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); post_code(0x47); - do_agesawrapper(agesawrapper_amdinitenv, "amdinitenv"); + do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ post_code(0x46); - do_agesawrapper(agesawrapper_amds3laterestore, - "amds3laterestore"); + do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4a856a9..c10920f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -391,7 +391,7 @@ { /* Must be called after PCI enumeration and resource allocation */ if (!romstage_handoff_is_resume()) - do_agesawrapper(agesawrapper_amdinitmid, "amdinitmid"); + do_agesawrapper(AMD_INIT_MID, "amdinitmid"); } void domain_set_resources(struct device *dev) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9f8aed8..2769dfe 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -65,11 +65,11 @@ static void agesa_call(void) { post_code(0x37); - do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); + do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); post_code(0x38); /* APs will not exit amdinitearly */ - do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); + do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } static void bsp_agesa_call(void) @@ -102,7 +102,7 @@ if (!s3_resume) { post_code(0x40); - do_agesawrapper(agesawrapper_amdinitpost, "amdinitpost"); + do_agesawrapper(AMD_INIT_POST, "amdinitpost"); post_code(0x41); /* @@ -137,7 +137,7 @@ } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - do_agesawrapper(agesawrapper_amdinitresume, "amdinitresume"); + do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); post_code(0x61); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893 Gerrit-Change-Number: 31483 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: mb/google/sarein: Add power control for Arcada touchscreen
by Roy Mingi Park (Code Review) 23 Apr '19

23 Apr '19

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32311 Change subject: mb/google/sarein: Add power control for Arcada touchscreen ...................................................................... mb/google/sarein: Add power control for Arcada touchscreen This change will save touchscreen power leakage 2-3mW in S0iX BUG=b:129899315 TEST= Measure touchscreen power from Arcada during S0iX Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32311/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 1507214..14d8e77 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -302,8 +302,10 @@ register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "40" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" -- To view, visit https://review.coreboot.org/c/coreboot/+/32311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc Gerrit-Change-Number: 32311 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig
by Kane Chen (Code Review) 23 Apr '19

23 Apr '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32297 Change subject: soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig ...................................................................... soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig This change is mainly to control PlatformDebugConsent FSP UPD. If CONFIG_USE_DBC_CANNONLAKE=y, the PlatformDebugConsent be enabled. BUG=b:130203864 TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32297/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9796546..bcd3f30 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -289,4 +289,7 @@ depends on FSP_USE_REPO default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE +config USE_DBC_CANNONLAKE + bool "Support USB DBC for Cannonlake" + endif diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ffdcee4..53040ff 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -111,8 +111,12 @@ m_cfg->SmbusEnable = 0; else m_cfg->SmbusEnable = smbus->enabled; + /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + if (CONFIG(USE_DBC_CANNONLAKE)) + m_cfg->PlatformDebugConsent = DebugConsent_USB3_DBC; + else + m_cfg->PlatformDebugConsent = config->DebugConsent; mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29 Gerrit-Change-Number: 32297 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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