coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: 3rdparty/opensbi: Add submodule
by Philipp Deppenwiese (Code Review) 24 Apr '19

24 Apr '19

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32418 Change subject: 3rdparty/opensbi: Add submodule ...................................................................... 3rdparty/opensbi: Add submodule * Add opensbi for RISC-v Change-Id: I1a6baa6b6c05095ff5545492aabf7408a23af181 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M .gitmodules A 3rdparty/opensbi 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32418/1 diff --git a/.gitmodules b/.gitmodules index f4f7c4f..78e2c88 100644 --- a/.gitmodules +++ b/.gitmodules @@ -26,3 +26,6 @@ url = ../fsp.git update = none ignore = dirty +[submodule "opensbi"] + path = 3rdparty/opensbi + url = ../opensbi.git diff --git a/3rdparty/opensbi b/3rdparty/opensbi new file mode 160000 index 0000000..804b997 --- /dev/null +++ b/3rdparty/opensbi @@ -0,0 +1 @@ +Subproject commit 804b997ed415001097803e4b537fd63d043874b9 -- To view, visit https://review.coreboot.org/c/coreboot/+/32418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a6baa6b6c05095ff5545492aabf7408a23af181 Gerrit-Change-Number: 32418 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: Add UART support
by Nitheesh Sekar (Code Review) 24 Apr '19

24 Apr '19

Nitheesh Sekar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add UART support ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/#/c/29964/19/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/19/src/soc/qualcomm/qcs405/uart.c@272 PS19, Line 272: IS_ENABLED(CONFIG_DRIVERS_U > We have (and use) CONFIG(DRIVERS_UART) now, see also elsewhere Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 20 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 24 Apr 2019 06:53:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Nitheesh Sekar (Code Review) 24 Apr '19

24 Apr '19

Nitheesh Sekar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29962 ) Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... Patch Set 18: (2 comments) https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/clock.c@251 PS18, Line 251: clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, > This should probably go into uart_init(), not here. Done in CB:32240 https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/clock.c@259 PS18, Line 259: clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, > Clock configuration for individual peripheral drivers should be done by the peripheral driver (with […] Done in CB:32240 -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 18 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 24 Apr 2019 06:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Frans Hendriks (Code Review) 24 Apr '19

24 Apr '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 8: > Patch Set 8: Code-Review-1 > > > FSP MR2 does a check for ACPI mode and change the device mode. Supplying incorrect configuration will be corrected by FSP, but to be futher proof supply correct configuration to FSP. > > I can't say that I understand this yet. You are saying FSP > allows a value of 2 (PCH_ACPI_MODE). But then you say FSP > would be correcting incorrect configuration, which translates > to me as it reads the hardware state and ignores the diffe- > rence between a 1 and a 2. > > And about being future proof. That's generally a good idea, > but how can we anticipate the future here? How can we tell > that if FSP is being corrected, if the code will be made to > match the header file or the other way around? The goal is to supply correct mode settings to FSP. For this reason the modification is made. On the other hand FSP (MR2) will modify settings of the child devices if incorrect. What FSP is doing is not wrong, but for those without access to FSP sources, we should ensure that coreboot is configuring the correct mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 24 Apr 2019 05:46:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Toggle SSD reset pin on DVT2
by Lijian Zhao (Code Review) 24 Apr '19

24 Apr '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32434 Change subject: mb/google/sarien: Toggle SSD reset pin on DVT2 ...................................................................... mb/google/sarien: Toggle SSD reset pin on DVT2 SSD reset pin had been added on DVT2, the power sequnence requires toggle in boot stage. BUG=b:130741066 TEST=Boot up with simulated DVT2 platform and confirm SSD can be detected during warm reboot. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1 --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32434/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 2a0ead8..bc240e1 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -251,6 +251,9 @@ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 0, DEEP), /* M.2 SSD D3 cold */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 19fd45c..b228a16 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -236,6 +236,9 @@ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ +/* SSD RESET need to stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* /D3 cold RST */ +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 0, DEEP), /* M.2 SSD D3 cold */ /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/32434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1 Gerrit-Change-Number: 32434 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: I2C clock tuning for bloog
by Tony Huang (Code Review) 24 Apr '19

24 Apr '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32404 Change subject: mb/google/octopus: I2C clock tuning for bloog ...................................................................... mb/google/octopus: I2C clock tuning for bloog Tune I2C params for I2C buses 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:131132499, b:128998988 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/overridetree.cb 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32404/1 diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 20b5dd3..5435d9f 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -49,12 +49,32 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, + }" device domain 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/32404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21 Gerrit-Change-Number: 32404 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Add USB support on cheza platform
by T Michael Turney (Code Review) 23 Apr '19

23 Apr '19

T Michael Turney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25213 ) Change subject: sdm845: Add USB support on cheza platform ...................................................................... Patch Set 68: (1 comment) https://review.coreboot.org/#/c/25213/68/src/soc/qualcomm/sdm845/usb.c File src/soc/qualcomm/sdm845/usb.c: https://review.coreboot.org/#/c/25213/68/src/soc/qualcomm/sdm845/usb.c@791 PS68, Line 791: /* > Need to fix this one to get the Verified+1 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/25213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc Gerrit-Change-Number: 25213 Gerrit-PatchSet: 68 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Ciluveru chandana kishori <cchiluve(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chandana Kishori Chiluveru <cchiluve(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 23 Apr 2019 22:52:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform IP init
by T Michael Turney (Code Review) 23 Apr '19

23 Apr '19

T Michael Turney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25208 ) Change subject: sdm845: Add QCLib to RomStage to perform IP init ...................................................................... Patch Set 73: (17 comments) https://review.coreboot.org/#/c/25208/69/src/mainboard/google/cheza/chromeo… File src/mainboard/google/cheza/chromeos.fmd: https://review.coreboot.org/#/c/25208/69/src/mainboard/google/cheza/chromeo… PS69, Line 35: RW_NVRAM 16K > Where did RW_LIMITS_CFG and RW_DDR_TRAINING go (the spaces we want to preserve just in case an updat […] Ack https://review.coreboot.org/#/c/25208/73/src/mainboard/google/cheza/chromeo… File src/mainboard/google/cheza/chromeos.fmd: https://review.coreboot.org/#/c/25208/73/src/mainboard/google/cheza/chromeo… PS73, Line 28: RO_PRESERVE(PRESERVE) { > BTW we can remove RO_PRESERVE now and just write this as […] Ack https://review.coreboot.org/#/c/25208/73/src/mainboard/google/cheza/chromeo… PS73, Line 38: RW_LIMITS_CFG 4K > I think these two (RW_DDR_TRAINING and RW_LIMITS_CFG) should also be marked (PRESERVE). Ack https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/common/include/so… File src/soc/qualcomm/common/include/soc/qclib_common.h: https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/common/include/so… PS72, Line 79: void soc_blob_load(void); > Please prefix all external functions with qclib_ or something like that. Ack https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/common/qclib.c File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/common/qclib.c@135 PS72, Line 135: printk(BIOS_INFO, "Board Rev(0x%x)\n", board_id()); > This is already printed in ramstage once, do we need it here? Done https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/common/qclib.c@209 PS72, Line 209: ret_code = doit(&qclib_cb_if_table, NULL); > Now that we only have one argument, can we switch to using prog_run() for this? Done https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/Makefile.i… File src/soc/qualcomm/sdm845/Makefile.inc: https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/Makefile.i… PS73, Line 51: ifeq ($(CONFIG_QC_SDI_ENABLE),y) > Can we factor all this stuff out into a separate commit so we can check the code in while we're (sti […] If we pull this out, the build-bot will not be happy and give a -1, at least it has in the past. https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/memlayout.ld: https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/include/so… PS73, Line 36: REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) > Wasn't this reserved for the PBL shared data? If we're no longer using that, does it still need to b […] QCLib still uses the PBL shared data, CB is no longer responsible for passing it in. https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/include/so… PS73, Line 45: 0x100 > The align value just means the minimum alignment that this section needs to have, not what alignment […] I will play with the alignments at a later date, trying to address a number of more important items now. https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/include/so… PS73, Line 46: 0x1000 > Maybe write this as 4K so it can be more easily compared with the corresponding FMAP entry? (others […] Ack https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/include/so… PS73, Line 58: 160K > nit: This doesn't really have to do with our project, but for some other use cases people are starti […] Ack https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/qclib.h: https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/so… PS69, Line 52: #define QCLIB_GA_ENABLE_UART_LOGGING 0x00000001 > This used to be 0x2, was it updated in QcLib when you decided to remove SOC_DEBUG_FLOW? (In the futu […] OK, we will keep deprecated in list moving forward. Probably figured it didn't matter since it isn't upstream yet. https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/qclib.c File src/soc/qualcomm/sdm845/qclib.c: https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/qclib.c@47 PS73, Line 47: qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, _limits_cfg, size, 0); > Please fix. Ack https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… File src/soc/qualcomm/sdm845/qclib_execute.c: https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 1: /* > Please note that there are still many comments in CB:27360 that still apply here. I think I addressed all of the earlier comments when I created the common/ patch. I will double-check. https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 39: #define PBL_DATA_PTR 0x14810188 > This happened, right? So let's remove this. Ack https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 164: printk(BIOS_INFO, "Board Rev(0x%d)\n", board_id()); > This is already printed at the end of ramstage, I don't think it needs to be printed here. Ack https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 240: prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); > This is no longer used, right? Instead, please set &qclib_cb_if_table as argument here, and then use […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 73 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 23 Apr 2019 22:50:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus/variants/bloog: Add goodix touchscreen support
by Tony Huang (Code Review) 23 Apr '19

23 Apr '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32387 Change subject: mb/google/octopus/variants/bloog: Add goodix touchscreen support ...................................................................... mb/google/octopus/variants/bloog: Add goodix touchscreen support Add goodix touchscreen support BUG=none BRANCH=octopus TEST=emerge-octopus coreboot and verify that touchscreen works on bloog. Change-Id: I0b3b481ca806b6452d67ace5dfe53f12a14ac3be Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/32387/1 diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 20b5dd3..21a10f7 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -101,6 +101,20 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.has_power_resource" = "1" + register "generic.enable_delay_ms" = "10" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/32387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b3b481ca806b6452d67ace5dfe53f12a14ac3be Gerrit-Change-Number: 32387 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/northbridge/amd: Remove unused variables
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, Julius Werner, build bot (Jenkins), Patrick Georgi, Huang Jin, York Yang, Philipp Deppenwiese, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#38). Change subject: src/northbridge/amd: Remove unused variables ...................................................................... src/northbridge/amd: Remove unused variables Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 5 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 38 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2019