coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: sdm845: Add GPIO IRQ APIs
by T Michael Turney (Code Review) 24 Apr '19

24 Apr '19

T Michael Turney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30003 ) Change subject: sdm845: Add GPIO IRQ APIs ...................................................................... Patch Set 15: (6 comments) https://review.coreboot.org/#/c/30003/9/src/soc/qualcomm/sdm845/gpio.c File src/soc/qualcomm/sdm845/gpio.c: https://review.coreboot.org/#/c/30003/9/src/soc/qualcomm/sdm845/gpio.c@92 PS9, Line 92: & > Is this supposed to be a << instead of a & ? Ack https://review.coreboot.org/#/c/30003/9/src/soc/qualcomm/sdm845/gpio.c@94 PS9, Line 94: write32(&regs->intr_cfg, reg_val); > If this does need to be a read-modify-write operation, then please use clrsetbits_le32(). Ack https://review.coreboot.org/#/c/30003/11/src/soc/qualcomm/sdm845/gpio.c File src/soc/qualcomm/sdm845/gpio.c: https://review.coreboot.org/#/c/30003/11/src/soc/qualcomm/sdm845/gpio.c@90 PS11, Line 90: clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE > Please combine into a single access: […] Ack https://review.coreboot.org/#/c/30003/12/src/soc/qualcomm/sdm845/gpio.c File src/soc/qualcomm/sdm845/gpio.c: https://review.coreboot.org/#/c/30003/12/src/soc/qualcomm/sdm845/gpio.c@91 PS12, Line 91: << GPIO_INTR_RAW_STATUS_EN_SHIFT); > line over 80 characters Ack https://review.coreboot.org/#/c/30003/9/src/soc/qualcomm/sdm845/include/soc… File src/soc/qualcomm/sdm845/include/soc/gpio.h: https://review.coreboot.org/#/c/30003/9/src/soc/qualcomm/sdm845/include/soc… PS9, Line 382: IRQ_TYPE_LEVEL > Since the exact value of this is important, please write = 0 (and = 1, = 2, etc. […] Ack https://review.coreboot.org/#/c/30003/1/src/soc/qualcomm/sdm845/include/soc… File src/soc/qualcomm/sdm845/include/soc/gpio.h: https://review.coreboot.org/#/c/30003/1/src/soc/qualcomm/sdm845/include/soc… PS1, Line 77: #define GPIO_ENABLE 1 > Well, you need to update all use sites accordingly when you change it, of course. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/30003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f34e7bba17d9baad1db2bf025ba2db4afdfb58 Gerrit-Change-Number: 30003 Gerrit-PatchSet: 15 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Apr 2019 15:39:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/northbridge/amd: Remove unused variables
by Angel Pons (Code Review) 24 Apr '19

24 Apr '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src/northbridge/amd: Remove unused variables ...................................................................... Patch Set 38: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 38 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Apr 2019 13:38:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/southbridge/intel: Remove unused variables
by Angel Pons (Code Review) 24 Apr '19

24 Apr '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32427 ) Change subject: src/southbridge/intel: Remove unused variables ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5092aa076b9693f78c86ffb9b99805696bb0bb Gerrit-Change-Number: 32427 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Apr 2019 13:28:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Paul Menzel (Code Review) 24 Apr '19

24 Apr '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Apr 2019 11:48:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/ocp/monolake: add TPM and IPMI support
by Łukasz Siudut (Code Review) 24 Apr '19

24 Apr '19

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31525 Change subject: mb/ocp/monolake: add TPM and IPMI support ...................................................................... mb/ocp/monolake: add TPM and IPMI support Changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable by ipmi_si driver Signed-off-by: Lukasz Siudut <lsiudut(a)fb.com> Change-Id: I8f9fb17b9f1349272080e032991fe45a443a9d84 --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 5 files changed, 153 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31525/1 diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 76ecb48..2315ec6 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -11,6 +11,11 @@ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + +config INTEGRATED_UART + def_bool n config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 30d99c2..2d91b73 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -7,7 +7,14 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip drivers/generic/generic # BMC KCS + device pnp ca2.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller device pci 1f.5 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703..72b1c3c 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,6 +27,9 @@ { #include "acpi/platform.asl" + Name (IDTP, 0x0CA2) + Name (ICDP, 0x0CA6) + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -290,5 +293,97 @@ } } + Scope (_SB.PCI0.LPC0) + { + Device (SPMI) + { + Name (_HID, EisaId ("IPI0001")) + Name (_STR, Unicode ("IPMI_KCS")) + Name (_UID, 0x00) + OperationRegion (IPST, SystemIO, ICDP, 0x01) + Field (IPST, ByteAcc, NoLock, Preserve) + { + STAS, 8 + } + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } + Name (ICRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y01) + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y02) + + }) + Method (_CRS, 0, NotSerialized) + { + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) + + IPDB = IDTP + IPDH = IDTP + IPDL = 0x01 + + IPCB = ICDP + IPCH = ICDP + IPCL = 0x01 + + Return (ICRS) + } + Method (_IFT, 0, NotSerialized) { + Return (0x01) + } + Method(_SRV, 0, NotSerialized) { + Return (0x0200) + } + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, + 0x0CA2, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA6, + 0x0CA6, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA8, + 0x0CA8, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CAC, + 0x0CAC, + 0x01, + 0x01, + ) + }) + } + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index f1a3a20..934b757 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -15,17 +15,52 @@ */ #include <device/device.h> +#include <smbios.h> + #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif +#define BMC_KCS_BASE 0xca2 +#define INTERFACE_IS_IO 0x1 + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address + 0x40, + 0); // no IRQ + + return len; +} +#endif + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif + /* Enable access to the BMC IPMI via KCS */ + struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); + struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + res->base = BMC_KCS_BASE; + res->size = 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index cf52c01..58b2d17 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,8 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +26,14 @@ */ void early_mainboard_romstage_entry(void) { - + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, + 0x0c0681); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + 0x0c0ca1); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN3_DEC, + 0xfc0201); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN4_DEC, + 0xfc0601); } /** @@ -33,7 +42,6 @@ */ void late_mainboard_romstage_entry(void) { - } /** @@ -41,5 +49,4 @@ */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - } -- To view, visit https://review.coreboot.org/c/coreboot/+/31525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f9fb17b9f1349272080e032991fe45a443a9d84 Gerrit-Change-Number: 31525 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel: Add functions to retrieve top of usable DRAM
by Nico Huber (Code Review) 24 Apr '19

24 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32374 ) Change subject: intel: Add functions to retrieve top of usable DRAM ...................................................................... Patch Set 4: Why call it `_base`? There are already files for memory map related functions, please reuse those (and call or rename platform specific versions if they already exist). -- To view, visit https://review.coreboot.org/c/coreboot/+/32374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ae1f3540d13076469f73188351ae9f9d4b1c63b Gerrit-Change-Number: 32374 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 24 Apr 2019 11:44:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Prudhvi Yarlagadda (Code Review) 24 Apr '19

24 Apr '19

Prudhvi Yarlagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 ) Change subject: libpayload: Add UART for qcs405 ...................................................................... Patch Set 21: (9 comments) we have reviewed all comments and will be addressed soon in the next patch which is under progress. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/configs/config… File payloads/libpayload/configs/config.mistral: https://review.coreboot.org/#/c/29957/20/payloads/libpayload/configs/config… PS20, Line 6: CONFIG_LP_USB=y : CONFIG_LP_USB_EHCI=y : CONFIG_LP_USB_XHCI=y > strictly speaking this isn't covered by the commit message We will remove this in our next patch. Sricharan and team to add this in a separate gerrit. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… File payloads/libpayload/drivers/serial/qcs405.c: https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 286: .uart_dm_base = UART2_DM_BASE, > This should be taken from lib_sysinfo.serial->baseaddr rather than hardcoded. […] We will add this uart_fill_lb() functionality in our next patch. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 287: .blsp_uart = BLSP1_UART2, > This seems unused? We will remove this in our next patch. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 291: #define read32(addr) readl(addr) > These are already defined in <io.h>, don't define them again. We will remove this in our next patch. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 329: * @wait: indicates blocking call or not blocking call > This parameter is never set by this driver so you should get rid of it (and associated code). We will remove this part of the code in our next patch. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 347: readl > readl() is deprecated, use read32() for new code. We will change this in our next patch. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 373: if (*data == 0) > '\0' may be a legal input byte. Agree, We will remove this in our next patch. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 544: /* For simplicity sake let's rely on coreboot initalizing the UART. */ > You say it, but why aren't you actually doing it? Why do you need that big msm_boot_uart_dm_init() f […] We will remove this initialization part in our next patch. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 556: consout.putchar = serial_putchar; > These can be assigned in the struct initializer for consin/consout, they don't need to be here. We will do this assignment in the struct initializer for consin/consout in our next patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 21 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prudhvi Yarlagadda <pyarlaga(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2019 11:20:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/picasso: Update stoney paths to picasso
by Paul Menzel (Code Review) 24 Apr '19

24 Apr '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32412 ) Change subject: soc/amd/picasso: Update stoney paths to picasso ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b Gerrit-Change-Number: 32412 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Apr 2019 10:41:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek: Set processor voltage to 1.05v
by Tristan Hsieh (Code Review) 24 Apr '19

24 Apr '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32396 Change subject: mediatek: Set processor voltage to 1.05v ...................................................................... mediatek: Set processor voltage to 1.05v The maximum CPU frequency is 1417MHz with current processor voltage (0.8v). Set processor voltage to 1.05v for higher CPU frequency. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: I24ecdac2c85d3f012d9235449c0d727d727dc185 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/mt6358.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/32396/1 diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 3dc9fe2..321e5cf 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -493,6 +493,10 @@ /* [2:1]: RG_LDO_VSRAM_PROC12_TRACK_ON_CTRL */ /* [2:2]: RG_LDO_VSRAM_PROC12_TRACK_VPROC12_ON_CTRL */ {0x1B6C, 0x6, 0x6, 0}, + + /* Vproc11/Vproc12 to 1.05V */ + {0x13a6, 0x58, 0x7F, 0}, + {0x140a, 0x58, 0x7F, 0}, }; static struct pmic_setting lp_setting[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/32396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ecdac2c85d3f012d9235449c0d727d727dc185 Gerrit-Change-Number: 32396 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/seabios: Update the stable git hash of 1.12.1
by Martin Kepplinger (Code Review) 24 Apr '19

24 Apr '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32173 Change subject: payloads/seabios: Update the stable git hash of 1.12.1 ...................................................................... payloads/seabios: Update the stable git hash of 1.12.1 The Kconfig file has been updated to show 1.12.1 but this is only what gets displayed for the "stable" option. Fix this by updating the actual git hash for the SeaBIOS 1.12.1 release tag. Fixes: fb83ff1a8b ("Update stable from 1.12.0 to 1.12.1") Change-Id: I76dc0dc8b651df0c6ff6f3c02819a70bab8c04cd Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M payloads/external/SeaBIOS/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32173/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..fd05c0c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=a698c8995ffb2838296ec284fe3c4ad33dfca307 +TAG-$(CONFIG_SEABIOS_STABLE)=a5cab58e9a3fb6e168aba919c5669bea406573b4 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git -- To view, visit https://review.coreboot.org/c/coreboot/+/32173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76dc0dc8b651df0c6ff6f3c02819a70bab8c04cd Gerrit-Change-Number: 32173 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019