coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform IP init
by T Michael Turney (Code Review) 24 Apr '19

24 Apr '19

T Michael Turney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25208 ) Change subject: sdm845: Add QCLib to RomStage to perform IP init ...................................................................... Patch Set 73: (1 comment) https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/Makefile.i… File src/soc/qualcomm/sdm845/Makefile.inc: https://review.coreboot.org/#/c/25208/73/src/soc/qualcomm/sdm845/Makefile.i… PS73, Line 51: ifeq ($(CONFIG_QC_SDI_ENABLE),y) > If we pull this out, the build-bot will not be happy and give a -1, at least it has in the past. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 73 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 24 Apr 2019 19:33:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: T Michael Turney <mturney(a)codeaurora.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: x86/acpi: Add Kconfig to toggle 8259 reporting
by Nico Huber (Code Review) 24 Apr '19

24 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29832 ) Change subject: x86/acpi: Add Kconfig to toggle 8259 reporting ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29832/1/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/#/c/29832/1/src/arch/x86/acpi.c@223 PS1, Line 223: IS_ENABLED(CONFIG_ACPI_HAVE_PCAT_8259) > Switch to the new convention? […] Thanks! done. -- To view, visit https://review.coreboot.org/c/coreboot/+/29832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Gerrit-Change-Number: 29832 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 24 Apr 2019 18:35:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: x86/acpi: Add Kconfig to toggle 8259 reporting
by Nico Huber (Code Review) 24 Apr '19

24 Apr '19

Hello HAOUAS Elyes, Paul Menzel, Lance Zhao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29832 to look at the new patch set (#2). Change subject: x86/acpi: Add Kconfig to toggle 8259 reporting ...................................................................... x86/acpi: Add Kconfig to toggle 8259 reporting Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/Kconfig M src/arch/x86/acpi.c 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29832/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Gerrit-Change-Number: 29832 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: kohaku: Update overridetree.cb
by Tim Wawrzynczak (Code Review) 24 Apr '19

24 Apr '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32405 Change subject: kohaku: Update overridetree.cb ...................................................................... kohaku: Update overridetree.cb Add common SoC config. Disable PCIe WiFi. Add digitizer. Turn off native SD card interface. No WWAN. Change-Id: I17d5ba6ce4ec412384e4a1678474b8d26499ba40 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 108 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32405/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index e39f140..e5d27af 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -204,7 +204,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 on end #I2C #4 + device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6e6414e..9241644 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,12 +1,11 @@ chip soc/intel/cannonlake - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, @@ -15,4 +14,105 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Disable native SD detect + register "PcdSdDetectChk" = "0" + register "sd_acpi_mode" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Digitizer | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + } + .i2c[1] = { + .speed = I2C_SPEED_FAST, + } + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + } + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + device usb 2.5 off end + end + chip drivers/usb/acpi + device usb 3.4 off end + end + end + end + end + device pci 14.5 off end # SDCard + + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_D21_IRQ)" + register "generic.wake" = "GPE0_DW2_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C 0 + + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" + register "reset_delay_ms" = "1" + register "has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 09 on end + end + end # I2C #2 + device pci 19.0 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_H0_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + # No PCIe WiFi + device pci 1d.5 off end + end # domain + + # no native SD support + register "sdcard_cd_gpio" = "" end -- To view, visit https://review.coreboot.org/c/coreboot/+/32405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17d5ba6ce4ec412384e4a1678474b8d26499ba40 Gerrit-Change-Number: 32405 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cheza: configure gpios and gcc clocks for sound
by T Michael Turney (Code Review) 24 Apr '19

24 Apr '19

T Michael Turney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31083 ) Change subject: cheza: configure gpios and gcc clocks for sound ...................................................................... Patch Set 5: (7 comments) https://review.coreboot.org/#/c/31083/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@2 PS1, Line 2: RajendraBabu > Add a space between the names? Ack https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@7 PS1, Line 7: cheza: configure gpios and gcc clocks for sound > Use the SoC name as prefix? Ack https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@9 PS1, Line 9: Configure mi2s, codec reset gpios and enable : GCC LPASS clocks required for audio support. > Please use the fully allowed text width. Ack https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@14 PS1, Line 14: kumar > Capital K? Ack https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/bootblock.c File src/soc/qualcomm/sdm845/bootblock.c: https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/bootblock.c… PS1, Line 29: sdm845_sound_init(); > Any specific reason this must be done in the bootblock? If not, please do it in ramstage (from mainb […] Ack https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/sound.c File src/soc/qualcomm/sdm845/sound.c: https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/sound.c@30 PS1, Line 30: GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT); > Which I2S bus to use is board-specific, so this function has to go into mainboard.c. Ack https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/sound.c@46 PS1, Line 46: write32((void *)GCC_LPASS_Q6_AXI_CBCR, 0x80000001); > This function should be implemented in clock.c and use the GCC register overlay from there. I need to better understand the clock interface to make this change. This is deferred for now and function moved to mainboard.c with rest of this code. -- To view, visit https://review.coreboot.org/c/coreboot/+/31083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I130c4a0df88d0825debfa8e5c22a31f30be70df6 Gerrit-Change-Number: 31083 Gerrit-PatchSet: 5 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 24 Apr 2019 16:29:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/sconfig: Throw an error if override tree has no devices
by Furquan Shaikh (Code Review) 24 Apr '19

24 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32289 Change subject: util/sconfig: Throw an error if override tree has no devices ...................................................................... util/sconfig: Throw an error if override tree has no devices If override tree does not have any device, then the chip info structure in it cannot be associated with the correct device and ends up being added as a standalone chip info structure without any device actually using it. This change prevents this condition by throwing an error during compilation. BUG=b:130342895 Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/sconfig/main.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32289/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4ac935e..5382f47 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1316,6 +1316,11 @@ override_devtree = argv[OVERRIDE_DEVICEFILE_ARG]; parse_devicetree(override_devtree, &override_root_bus); + if (!dev_has_children(&override_root_dev)) { + fprintf(stderr, "ERROR: Override tree needs at least one device!\n"); + exit(1); + } + override_devicetree(&base_root_bus, &override_root_bus); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd Gerrit-Change-Number: 32289 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/var/kohaku: Skip UART0 config in FSP
by Furquan Shaikh (Code Review) 24 Apr '19

24 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32398 Change subject: mb/google/hatch/var/kohaku: Skip UART0 config in FSP ...................................................................... mb/google/hatch/var/kohaku: Skip UART0 config in FSP Similar to hatch(CB:32278), this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=b:130310626 Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/32398/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6e6414e..d564918 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -10,9 +10,12 @@ [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + device domain 0 on + end + end -- To view, visit https://review.coreboot.org/c/coreboot/+/32398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4 Gerrit-Change-Number: 32398 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Change POWER_OFF_ON_CR50_UPDATE so it can be disabled
by Keith Short (Code Review) 24 Apr '19

24 Apr '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32435 Change subject: security/tpm: Change POWER_OFF_ON_CR50_UPDATE so it can be disabled ...................................................................... security/tpm: Change POWER_OFF_ON_CR50_UPDATE so it can be disabled Modify the POWER_OFF_ON_CR50_UPDATE Kconfig option so that specific mainboard implementations can disable the option. BUG=b:126632503 BRANCH=none TEST=Build coreboot on sarien/arcada. TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots normally after sending TURN_UPDATE_ON to the Cr50. Change-Id: I3beefaae21de61e53ae232dbdc8ea9dbb2c78cd5 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/security/tpm/tss/vendor/cr50/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/32435/1 diff --git a/src/security/tpm/tss/vendor/cr50/Kconfig b/src/security/tpm/tss/vendor/cr50/Kconfig index 4d40c08..4a2ad4f 100644 --- a/src/security/tpm/tss/vendor/cr50/Kconfig +++ b/src/security/tpm/tss/vendor/cr50/Kconfig @@ -16,12 +16,12 @@ config TPM_CR50 bool default y if MAINBOARD_HAS_I2C_TPM_CR50 || MAINBOARD_HAS_SPI_TPM_CR50 - select POWER_OFF_ON_CR50_UPDATE if ARCH_X86 if TPM_CR50 config POWER_OFF_ON_CR50_UPDATE bool + default y if ARCH_X86 help Power off machine while waiting for CR50 update to take effect. -- To view, visit https://review.coreboot.org/c/coreboot/+/32435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3beefaae21de61e53ae232dbdc8ea9dbb2c78cd5 Gerrit-Change-Number: 32435 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarein: Remove touch VPD support and Melfas HID touch
by EricR Lai (Code Review) 24 Apr '19

24 Apr '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32437 Change subject: mb/google/sarein: Remove touch VPD support and Melfas HID touch ...................................................................... mb/google/sarein: Remove touch VPD support and Melfas HID touch Sarien will change Melfas from HID to I2C and change address from 0x10 to 0x34. So we don't need VPD to separate Elan and Melfas anymore. BUG=b:131194574 TEST=boot up and check no Melfas HID device exist Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic002f61b226743e1c18dbdbc51ce8b733916d8a0 --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/sarien/Makefile.inc M src/mainboard/google/sarien/variants/sarien/devicetree.cb D src/mainboard/google/sarien/variants/sarien/ramstage.c 4 files changed, 1 insertion(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32437/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 9d658fa..f1046ec 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -100,11 +100,6 @@ string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -config TOUCHSCREEN_HID - string "Specify the touchscreen HID enabled for the OS" - default "WCOM48E2" if BOARD_GOOGLE_ARCADA - default "ELAN900C" if BOARD_GOOGLE_SARIEN - config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/sarien/variants/sarien/Makefile.inc b/src/mainboard/google/sarien/variants/sarien/Makefile.inc index fa5b2ea..2bf028e 100644 --- a/src/mainboard/google/sarien/variants/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/variants/sarien/Makefile.inc @@ -14,6 +14,6 @@ ## bootblock-y += gpio.c -ramstage-y += gpio.c ramstage.c +ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 625655b..1b72058 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -306,19 +306,6 @@ device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid - register "generic.hid" = ""ACPI0C50"" - register "generic.desc" = ""Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" - register "generic.enable_off_delay_ms" = "100" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x0" - device i2c 10 on end - end - chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" diff --git a/src/mainboard/google/sarien/variants/sarien/ramstage.c b/src/mainboard/google/sarien/variants/sarien/ramstage.c deleted file mode 100644 index d20260c..0000000 --- a/src/mainboard/google/sarien/variants/sarien/ramstage.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootstate.h> -#include <console/console.h> -#include <device/device.h> -#include <drivers/i2c/hid/chip.h> -#include <drivers/vpd/vpd.h> -#include <soc/pci_devs.h> -#include <string.h> - -/* - * This board may have different touchscreen devices that are at the - * same I2C slave address but need different drivers or ACPI configuration. - * - * The default touchscreen to be enabled is specified in Kconfig by the - * ACPI HID of the device. If a board is connected to a different - * touchscreen device it can be enabled in Kconfig or by setting the - * VPD key 'touchscreen_hid'. - */ - -#define TOUCHSCREEN_I2C_ADDR 0x10 -#define TOUCHSCREEN_VPD_KEY "touchscreen_hid" - -static void disable_unused_touchscreen(void *unused) -{ - struct device *i2c0 = PCH_DEV_I2C0; - struct bus *i2c_slaves = i2c0->link_list; - struct device *slave = i2c_slaves->children; - char touchscreen_hid[9] = CONFIG_TOUCHSCREEN_HID; - struct drivers_i2c_hid_config *info; - - /* Look for VPD key that indicates which touchscreen is present */ - if (CONFIG(VPD) && - !vpd_gets(TOUCHSCREEN_VPD_KEY, touchscreen_hid, - ARRAY_SIZE(touchscreen_hid), VPD_ANY)) - printk(BIOS_INFO, "%s: VPD key '%s' not found, default to %s\n", - __func__, TOUCHSCREEN_VPD_KEY, touchscreen_hid); - - /* Go through all I2C slave devices on this bus */ - while (slave) { - /* Find all the I2C slaves with the matching address */ - if (slave->path.type == DEVICE_PATH_I2C && - slave->path.i2c.device == TOUCHSCREEN_I2C_ADDR) { - info = slave->chip_info; - /* Disable all devices except the matching HID */ - if (strncmp(info->generic.hid, touchscreen_hid, - ARRAY_SIZE(touchscreen_hid))) { - printk(BIOS_INFO, "%s: Disable %s\n", __func__, - info->generic.hid); - slave->enabled = 0; - } else { - printk(BIOS_INFO, "%s: Enable %s\n", __func__, - info->generic.hid); - } - } - slave = slave->sibling; - } -} -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - disable_unused_touchscreen, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/32437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic002f61b226743e1c18dbdbc51ce8b733916d8a0 Gerrit-Change-Number: 32437 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarein: Disable touch by strap pin GPP_B4
by EricR Lai (Code Review) 24 Apr '19

24 Apr '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32438 Change subject: mb/google/sarein: Disable touch by strap pin GPP_B4 ...................................................................... mb/google/sarein: Disable touch by strap pin GPP_B4 We want to disable touch for none touch sku. We can use strap pin GPP_B4 to identify it is connected with touch or not. If GPP_B4 is low level that means touch sku. If GPP_B4 is high level that means none-touch sku. BUG=b:131132419 TEST=boot up and check no touch device exist Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: If6681262c25e4b01e061a8520e38905d40345509 --- M src/drivers/i2c/hid/hid.c M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/32438/1 diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index d570892..6d93e2a 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -60,6 +60,23 @@ { struct drivers_i2c_hid_config *config = dev->chip_info; + if (!config) + return; + + /* Check if device is present by reading GPIO */ + if (config->generic.device_present_gpio) { + int present = gpio_get(config->generic.device_present_gpio); + present ^= config->generic.device_present_gpio_invert; + + printk(BIOS_INFO, "%s is %spresent\n", + dev->chip_ops->name, present ? "" : "not "); + + if (!present) { + dev->enabled = 0; + return; + } + } + dev->ops = &i2c_hid_ops; if (config && config->generic.desc) { diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 1b72058..dab92f3 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -316,6 +316,8 @@ register "generic.enable_off_delay_ms" = "100" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" device i2c 10 on end end chip drivers/i2c/generic @@ -326,6 +328,8 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" register "enable_delay_ms" = "5" register "has_power_resource" = "1" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" device i2c 34 on end end end # I2C #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6681262c25e4b01e061a8520e38905d40345509 Gerrit-Change-Number: 32438 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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