coreboot-gerrit April 2019

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Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 37 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: restore

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Change in ...coreboot[master]: soc/qualcomm/qcs405: add console.h include
by Patrick Georgi (Code Review) 23 Apr '19

23 Apr '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32422 Change subject: soc/qualcomm/qcs405: add console.h include ...................................................................... soc/qualcomm/qcs405: add console.h include Change-Id: I556d00e8b06f631a5ca51ae2b5ba646e5f536480 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/qcs405/clock.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32422/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index ebad13b..302652b 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/mmio.h> #include <types.h> #include <delay.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556d00e8b06f631a5ca51ae2b5ba646e5f536480 Gerrit-Change-Number: 32422 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/var/kohaku: Initialize common_soc_config
by Furquan Shaikh (Code Review) 23 Apr '19

23 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32402 Change subject: mb/google/hatch/var/kohaku: Initialize common_soc_config ...................................................................... mb/google/hatch/var/kohaku: Initialize common_soc_config This change initializes I2C and GSPI settings in common_soc_config in override tree for kohaku. BUG=b:130310626 Change-Id: Ibe3dc9b9313400c9f4d3f04f85e928204a029bd7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/32402/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index d564918..bd96def 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -15,6 +15,25 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/32402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe3dc9b9313400c9f4d3f04f85e928204a029bd7 Gerrit-Change-Number: 32402 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Patrick Georgi (Code Review) 23 Apr '19

23 Apr '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 ) Change subject: libpayload: Add UART for qcs405 ...................................................................... Patch Set 21: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 21 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 23 Apr 2019 18:17:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add support of GPIO IRQ APIs
by Name of user not set (Code Review) 23 Apr '19

23 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32241 Change subject: qcs405: Add support of GPIO IRQ APIs ...................................................................... qcs405: Add support of GPIO IRQ APIs Add support of GPIO IRQ APIs. Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c Signed-off-by: Shefali Jain <shefjain(a)codeaurora.org> Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/gpio.c M src/soc/qualcomm/qcs405/include/soc/gpio.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32241/1 diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index db8b7a1..d6f6196 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -74,3 +74,28 @@ gpio_configure(gpio, GPIO_FUNC_GPIO, GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); } + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_DISABLE); + + clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); + clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT); +} + +int gpio_irq_status(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK)) + return 0; + + write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE); + return 1; +} diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index fce4350..232e05e 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -30,6 +30,26 @@ #define TLMM_GPIO_IN_OUT_OFF 0x4 #define TLMM_GPIO_ID_STATUS_OFF 0x10 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + /* GPIO TLMM: Direction */ #define GPIO_INPUT 0 #define GPIO_OUTPUT 1 @@ -304,12 +324,23 @@ PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), }; +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + struct tlmm_gpio { uint32_t cfg; uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; }; void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); #endif // _SOC_QUALCOMM_QCS405_GPIO_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/32241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c Gerrit-Change-Number: 32241 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: clock: Update SPI API
by Name of user not set (Code Review) 23 Apr '19

23 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32240 Change subject: qcs405: clock: Update SPI API ...................................................................... qcs405: clock: Update SPI API Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405. Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain <shefjain(a)codeaurora.org> Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h 2 files changed, 111 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32240/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 31fdc3d..81bf7cb 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -20,7 +20,6 @@ #include <timestamp.h> #include <commonlib/helpers.h> #include <string.h> - #include <soc/clock.h> #define DIV(div) (div ? (2*div - 1) : 0) @@ -212,11 +211,35 @@ clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg)); } -void clock_configure_spi(int blsp, uint32_t hz) +void clock_configure_spi(int blsp, int qup, uint32_t hz) { - struct qcs405_clock *spi_clk = (blsp == 1) ? - (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk - : (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + struct qcs405_clock *spi_clk = 0; + + if (blsp == 1) + { + switch (qup) { + case 0: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup0_spi_clk; + break; + case 1: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup1_spi_clk; + break; + case 2: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup2_spi_clk; + break; + case 3: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup3_spi_clk; + break; + case 4: + spi_clk = (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk; + break; + } + } + else if (blsp == 2) + spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } @@ -231,38 +254,71 @@ clock_disable(&gcc->blsp1_uart2_apps_cbcr); } -void clock_enable_spi(int blsp) +void clock_enable_spi(int blsp, int qup) { - (blsp == 1) ? clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) + { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } + else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); } -void clock_disable_spi(int blsp) +void clock_disable_spi(int blsp, int qup) { - (blsp == 1) ? clock_disable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_disable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) + { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } + else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); + } void clock_init(void) { - clock_configure_gpll0(); - - clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, - ARRAY_SIZE(uart_cfg)); - - clock_enable(&gcc->blsp1_uart2_apps_cbcr); clock_enable_vote(&gcc->blsp1_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP1_AHB_CLK_ENA); - clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); - - clock_configure(&gcc->blsp2_qup0_spi_clk, spi_cfg, 50000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); clock_enable_vote(&gcc->blsp2_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP2_AHB_CLK_ENA); diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index d0f307b..8638128 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -21,7 +21,6 @@ #define BLSP2_AHB_CLK_ENA 20 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_800MHZ 1 -#define REG(addr) ((void *)addr) /** * USB BCR registers @@ -66,28 +65,48 @@ u32 blsp1_bcr; u32 blsp1_sleep_cbcr; u32 blsp1_ahb_cbcr; - u8 _res1[0x3028 - 0x100c]; + struct qcs405_rcg gcc_blsp_uart_sim_rcg; + u8 _res1[0x2000 - 0x1014]; + u32 blsp1_qup1_bcr; + u32 blsp1_qup1_spi_apps_cbcr; + u8 _res2[0x2024 - 0x2008]; + struct qcs405_clock blsp1_qup1_spi_clk; + u8 _res3[0x3008-0x2038]; + u32 blsp1_qup2_bcr; + u32 blsp1_qup2_spi_apps_cbcr; + u8 _res4[0x3014 - 0x3010]; + struct qcs405_clock blsp1_qup2_spi_clk; u32 blsp1_uart2_bcr; u32 blsp1_uart2_apps_cbcr; u32 blsp1_uart2_sim_cbcr; struct qcs405_clock blsp1_uart2_apps_clk; - u8 _res2[0x5018 - 0x3048]; + u8 _res5[0x4018 - 0x3048]; + u32 blsp1_qup3_bcr; + u32 blsp1_qup3_spi_apps_cbcr; + u8 _res6[0x4024 - 0x4020]; + struct qcs405_clock blsp1_qup3_spi_clk; + u8 _res7[0x5018 - 0x4038]; u32 blsp1_qup4_bcr; u32 blsp1_qup4_spi_apps_cbcr; - u8 _res3[0x5024 - 0x5020]; + u8 _res8[0x5024 - 0x5020]; struct qcs405_clock blsp1_qup4_spi_clk; - u8 _res4[0xB000 - 0x5038]; + u8 _res9[0x6020 - 0x5038]; + u32 blsp1_qup0_bcr; + u32 blsp1_qup0_spi_apps_cbcr; + u8 _res10[0x6034 - 0x6028]; + struct qcs405_clock blsp1_qup0_spi_clk; + u8 _res11[0xB000 - 0x6048]; u32 blsp2_bcr; u32 blsp2_sleep_cbcr; u32 blsp2_ahb_cbcr; - u8 _res5[0xC000 - 0xB00C]; + u8 _res12[0xC000 - 0xB00C]; u32 blsp2_qup0_bcr; u32 blsp2_qup0_spi_apps_cbcr; - u8 _res6[0xC024 - 0xC008]; + u8 _res13[0xC024 - 0xC008]; struct qcs405_clock blsp2_qup0_spi_clk; - u8 _res7[0x21000 - 0xC038]; + u8 _res14[0x21000 - 0xC038]; struct qcs405_gpll gpll0; - u8 _res8[0x45004 - 0x21024]; + u8 _res15[0x45004 - 0x21024]; u32 gcc_apcs_clock_branch_en_vote; }; @@ -160,10 +179,10 @@ int clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_uart(uint32_t hz); -void clock_configure_spi(int blsp, uint32_t hz); +void clock_configure_spi(int blsp, int qup, uint32_t hz); void clock_enable_uart(void); void clock_disable_uart(void); -void clock_enable_spi(int blsp); -void clock_disable_spi(int blsp); +void clock_enable_spi(int blsp, int qup); +void clock_disable_spi(int blsp, int qup); #endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/32240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39622571cb671f62312283a010129ceecb654f61 Gerrit-Change-Number: 32240 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Nico Huber (Code Review) 23 Apr '19

23 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 8: Code-Review-1 > FSP MR2 does a check for ACPI mode and change the device mode. Supplying incorrect configuration will be corrected by FSP, but to be futher proof supply correct configuration to FSP. I can't say that I understand this yet. You are saying FSP allows a value of 2 (PCH_ACPI_MODE). But then you say FSP would be correcting incorrect configuration, which translates to me as it reads the hardware state and ignores the diffe- rence between a 1 and a 2. And about being future proof. That's generally a good idea, but how can we anticipate the future here? How can we tell that if FSP is being corrected, if the code will be made to match the header file or the other way around? -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 23 Apr 2019 16:03:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus/variants/bloog: Disable unused I2C1
by Tony Huang (Code Review) 23 Apr '19

23 Apr '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32349 Change subject: mb/google/octopus/variants/bloog: Disable unused I2C1 ...................................................................... mb/google/octopus/variants/bloog: Disable unused I2C1 I2C1 is unused, so disable it. BUG=none BRANCH=octopus TEST=Verify reboot and s0ix suspend successfully Change-Id: I7ed5065cfd0b9780d13feb27cc78b8090d7a03a6 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32349/1 diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 20b5dd3..5f7605f 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -59,6 +59,7 @@ device domain 0 on device pci 16.0 off end # - I2C 0 + device pci 16.1 off end # - I2C 1 device pci 17.1 on chip drivers/i2c/da7219 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" -- To view, visit https://review.coreboot.org/c/coreboot/+/32349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ed5065cfd0b9780d13feb27cc78b8090d7a03a6 Gerrit-Change-Number: 32349 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [NOTFORMERGE]: Squashed away from BINARYPI_LEGACY_WRAPPER
by Kyösti Mälkki (Code Review) 23 Apr '19

23 Apr '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/19273 ) Change subject: [NOTFORMERGE]: Squashed away from BINARYPI_LEGACY_WRAPPER ...................................................................... Patch Set 6: > Patch Set 6: > > @Kyösti Mälkki why was this abandoned? It was NOTFORMERGE in the first place and I only had pushed that for the purpose of build testing as a proof-of-concept to show how ill all agesawrapper.c code and vendorcode/pi/AGESA.c is. I have lots of unpublished and/or rebased code for binaryPI, but with nobody doing even the simple reviews I have pushed so far on binaryPI, the work is essentially stalled in the status it had 2017. The evolution to POSCAR_STAGE and C_ENV_BOOTBLOCK and VBOOT are all somewhat problematic for binaryPI. I was hoping AMD / Silverback and connection with Chromebooks would have improved the older binaryPI side but I got over-frustrated with and lost most of the interest on architectural work on the topic. I put a lot of my own time on stoneyridge reviews, and that was a completely lost investment from my perspective. -- To view, visit https://review.coreboot.org/c/coreboot/+/19273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2db1482e60e59b060582310b2e86326051fb35f9 Gerrit-Change-Number: 19273 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Tue, 23 Apr 2019 15:55:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Matt DeVillier (Code Review) 23 Apr '19

23 Apr '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 8: just to clarify, this only affects the reporting of the mode (ACPI or PCI) for lpss devices in soc_display_silicon_init_params(), correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 23 Apr 2019 15:53:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2019