Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32406
Change subject: mb/supermicro/x10slm-f: Do SIO setup in bootblock
......................................................................
mb/supermicro/x10slm-f: Do SIO setup in bootblock
Lynx Point switched to doing mainboard-specific super I/O setup in the
bootblock with commit d893a2635fdd ("sb/intel/lynxpoint: Enable LPC/SIO
setup in bootblock"). The X10SLM+-F was added while that commit was in
review, and hence did not receive the necessary changes to SIO setup.
This patch has not been tested on hardware.
Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88
Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi>
---
M src/mainboard/supermicro/x10slm-f/Makefile.inc
A src/mainboard/supermicro/x10slm-f/bootblock.c
M src/mainboard/supermicro/x10slm-f/romstage.c
3 files changed, 42 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/32406/1
diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc
index ea9cc8a..301070b 100644
--- a/src/mainboard/supermicro/x10slm-f/Makefile.inc
+++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc
@@ -15,3 +15,4 @@
##
romstage-y += gpio.c
+bootblock-y += bootblock.c
diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm-f/bootblock.c
new file mode 100644
index 0000000..aeffa69
--- /dev/null
+++ b/src/mainboard/supermicro/x10slm-f/bootblock.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_superio(void)
+{
+ const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
+ const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
+ const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
+
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
+
+ /* Select HWM/LED functions instead of floppy functions. */
+ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
+ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
+
+ /* Power RAM in S3 and let the PCH handle power failure actions. */
+ pnp_set_logical_device(ACPI_DEV);
+ pnp_write_config(ACPI_DEV, 0xe4, 0x70);
+
+ nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
+}
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 84ad047..e43302a 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -17,14 +17,11 @@
#include <cpu/intel/haswell/haswell.h>
#include <cpu/intel/romstage.h>
-#include <device/pnp_ops.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <stdint.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct6776/nct6776.h>
static const struct rcba_config_instruction rcba_config[] = {
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
@@ -41,27 +38,6 @@
RCBA_END_CONFIG,
};
-void mainboard_config_superio(void)
-{
- const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
- const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
- const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
-
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
-
- /* Select HWM/LED functions instead of floppy functions. */
- pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
- pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
-
- /* Power RAM in S3 and let the PCH handle power failure actions. */
- pnp_set_logical_device(ACPI_DEV);
- pnp_write_config(ACPI_DEV, 0xe4, 0x70);
-
- nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
-}
-
void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88
Gerrit-Change-Number: 32406
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>
Gerrit-MessageType: newchange
Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32436
Change subject: mb/google/sarien: Disable POWER_OFF_ON_CR50_UPDATE
......................................................................
mb/google/sarien: Disable POWER_OFF_ON_CR50_UPDATE
Disable the POWER_OFF_ON_CR50_UPDATE option on sarien/arcada. This is
needed so that platform properly boots after doing a Cr50 firmware
update when running on battery.
BUG=b:126632503
BRANCH=none
TEST=Build coreboot on sarien/arcada.
TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots
normally after sending TURN_UPDATE_ON to the Cr50.
Change-Id: I0b687285eb95070eaffb68611a7d98eb8434ce2c
Signed-off-by: Keith Short <keithshort(a)chromium.org>
---
M src/mainboard/google/sarien/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32436/1
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 9d658fa..a2f8adc 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -59,6 +59,10 @@
int
default 82 # GPE0_DW2_18 (GPP_D18)
+config POWER_OFF_ON_CR50_UPDATE
+ bool
+ default n
+
config GBB_HWID
string
depends on CHROMEOS
--
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29683 )
Change subject: Revert "soc/intel/common/block: add VMX support"
......................................................................
Patch Set 5:
> > Any news about this?
>
> Let's ask Jenkins.
Still builds. And I think the conflicts with other patches
have been resolved.
--
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27068 )
Change subject: gma config: Make Config.CPU and Config.CPU_Var variable
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/27068/6/common/hw-gfx-gma-config.ads.templa…
File common/hw-gfx-gma-config.ads.template:
https://review.coreboot.org/#/c/27068/6/common/hw-gfx-gma-config.ads.templa…
PS6, Line 69: ,
> put those on the previous line?
It's an ugly trick, really: Ada doesn't allow a dangling comma
at the end of a list. So this makes it easier to kick these
lines out for the static-build case. cf. common/Makefile.inc:92
--
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Hello Patrick Rudolph, Aaron Durbin, ron minnich, Julius Werner, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29667
to look at the new patch set (#21).
Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
......................................................................
mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes
Working:
* Boots to Linux
* Boots to SeaBios
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
Broken:
* Entering SMM due to missing long mode setup
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
---
M Documentation/arch/x86/index.md
A Documentation/mainboard/emulation/qemu-i440fx.md
A Documentation/mainboard/emulation/qemu-q35.md
M Documentation/mainboard/index.md
M src/arch/x86/Kconfig
M src/cpu/qemu-x86/Kconfig
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
8 files changed, 171 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29667/21
--
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