coreboot-gerrit April 2019

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Change in ...coreboot[master]: nb/intel/i945: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31408 Change subject: nb/intel/i945: Use big enough type for left-shift ...................................................................... nb/intel/i945: Use big enough type for left-shift Change-Id: I7eb5850e4af3d5a41973a73737751b0f29c9d507 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c 4 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31408/1 diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 053815b..3fc1483 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -41,15 +41,15 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); max_buses = 256; break; case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); max_buses = 128; break; case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); max_buses = 64; break; default: // RSVD diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b82812e..fb504af 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -316,7 +316,7 @@ printk(BIOS_DEBUG, "ok\n"); /* Now enable VC1 */ - EPBAR32(EPVC1RCTL) |= (1 << 31); + EPBAR32(EPVC1RCTL) |= (1U << 31); printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ @@ -359,7 +359,7 @@ reg32 = RCBA32(V1CTL); reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24)); - reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); + reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1U << 31); RCBA32(V1CTL) = reg32; RCBA32(ESD) |= (2 << 16); @@ -408,7 +408,7 @@ DMIBAR32(DMIVC1RCTL) = reg32; /* Now enable VC1 */ - DMIBAR32(DMIVC1RCTL) |= (1 << 31); + DMIBAR32(DMIVC1RCTL) |= (1U << 31); printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ @@ -485,8 +485,8 @@ reg32 |= (0x02 << 26); DMIBAR32(0x200) = reg32; - DMIBAR32(DMIDRCCFG) &= ~(1 << 31); - DMIBAR32(DMICTL2) |= (1 << 31); + DMIBAR32(DMIDRCCFG) &= ~(1U << 31); + DMIBAR32(DMICTL2) |= (1U << 31); if (i945_silicon_revision() >= 3) { reg32 = DMIBAR32(0xec0); @@ -762,11 +762,11 @@ pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); - reg32 &= ~(1 << 31); + reg32 &= ~(1U << 31); pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); - reg32 |= (1 << 31); + reg32 |= (1U << 31); pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); if (i945_silicon_revision() >= 3) { diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 7c209dc..3973f80 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -45,13 +45,13 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); return 256; case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); return 128; case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); return 64; } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dece9bf..c86628b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1156,7 +1156,7 @@ sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) reg32 |= (1 << 7) | (1 << 5); else - reg32 |= (1 << 31); + reg32 |= (1U << 31); /* Is channel 1 populated? */ if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || @@ -2006,7 +2006,7 @@ reg32 = MCHBAR32(WCC); reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + reg32 |= (4U << 29) | (3 << 25) | (1 << 10); MCHBAR32(WCC) = reg32; MCHBAR32(SMVREFC) |= (1 << 6); -- To view, visit https://review.coreboot.org/c/coreboot/+/31408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb5850e4af3d5a41973a73737751b0f29c9d507 Gerrit-Change-Number: 31408 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31256 Change subject: sb/intel/i82801gx: Use big enough type for left-shift ...................................................................... sb/intel/i82801gx: Use big enough type for left-shift Change-Id: I4abe406adeee0aa5df9e4ee067b1685e2e964717 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/usb_ehci.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31256/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index f1866a5..d453809 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -243,7 +243,7 @@ // VCi Resource Control reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); + reg32 |= (1U << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map pci_write_config32(dev, 0x120, reg32); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 6679105..3c57614 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -42,7 +42,7 @@ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); + reg32 |= (1U << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); RCBA32(0x0088) = 0x0011d000; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7497c79..13380d2 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -316,7 +316,7 @@ /* Enable Clock Gating for most devices */ reg32 = RCBA32(CG); - reg32 |= (1 << 31); // LPC clock gating + reg32 |= (1U << 31); // LPC clock gating reg32 |= (1 << 30); // PATA clock gating // SATA clock gating reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index b40c83d..b58ef6b 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -36,7 +36,7 @@ pci_write_config32(dev, PCI_COMMAND, reg32); reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 31) | (1 << 27); + reg32 |= (1U << 31) | (1 << 27); pci_write_config32(dev, 0xdc, reg32); reg32 = pci_read_config32(dev, 0xfc); -- To view, visit https://review.coreboot.org/c/coreboot/+/31256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abe406adeee0aa5df9e4ee067b1685e2e964717 Gerrit-Change-Number: 31256 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801ix/sata.c: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31411 Change subject: sb/intel/i82801ix/sata.c: Use big enough type for left-shift ...................................................................... sb/intel/i82801ix/sata.c: Use big enough type for left-shift Change-Id: If052c7af67319e6b183eb1ba21834082e1695582 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/sata.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31411/1 diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 1968694..ee2ac53 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -43,7 +43,7 @@ /* Set AHCI access mode. No other ABAR registers should be accessed before this. */ reg32 = read32(abar + 0x04); - reg32 |= (1 << 31); + reg32 |= (1UL << 31); write32(abar + 0x04, reg32); /* CAP (HBA Capabilities) : enable power management */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If052c7af67319e6b183eb1ba21834082e1695582 Gerrit-Change-Number: 31411 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common/acpi/platform.asl: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30221 ) Change subject: sb/intel/common/acpi/platform.asl: Update _OSI strings and OSYS values ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b0cb0a516df43f7b9d6dbac89b7f8f32723ac41 Gerrit-Change-Number: 30221 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30468 Change subject: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values ...................................................................... mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/packardbell/ms2290/acpi/platform.asl 1 file changed, 67 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30468/1 diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14..e3f95ed 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -90,51 +90,101 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) + } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Gerrit-Change-Number: 30468 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30469 Change subject: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values ...................................................................... mb/lenovo/x201/acpi: Update _OSI strings and OSYS values Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x201/acpi/platform.asl 1 file changed, 68 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30469/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013b..1f55624 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -111,52 +111,103 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) + } + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Gerrit-Change-Number: 30469 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29852 ) Change subject: vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdef135aa7517477a10657bb01f866ec41f5bdf7 Gerrit-Change-Number: 29852 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 37 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29990 ) Change subject: sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Gerrit-Change-Number: 29990 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29726 ) Change subject: device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbc645ce5e50850c2ecc6e84835a5cb9659676f Gerrit-Change-Number: 29726 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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