coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: soc/intel/apollolake: Remove wrong comment on stddef.h
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31910 Change subject: soc/intel/apollolake: Remove wrong comment on stddef.h ...................................................................... soc/intel/apollolake: Remove wrong comment on stddef.h Change-Id: I4305ef052ff74a6a19977327c9b60b2a1282e028 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/meminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31910/1 diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 038fa9f..0f6506b 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -17,7 +17,7 @@ #include <fsp/util.h> #include <memory_info.h> #include <soc/meminit.h> -#include <stddef.h> /* required for FspmUpd.h */ +#include <stddef.h> #include <fsp/soc_binding.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4305ef052ff74a6a19977327c9b60b2a1282e028 Gerrit-Change-Number: 31910 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: include/spd_ddr2: Remove common SPD byte 2
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29725 ) Change subject: include/spd_ddr2: Remove common SPD byte 2 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29cf4184a32e9e72c1927b8f1f70f099394974af Gerrit-Change-Number: 29725 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: crossgcc: Upgrade acpica to version 20190405
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32215 Change subject: crossgcc: Upgrade acpica to version 20190405 ...................................................................... crossgcc: Upgrade acpica to version 20190405 Changes: https://acpica.org/node/169 Change-Id: I43f800bb459c8bef2658165baad55f30ac17d317 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20190405_iasl.patch D util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20190405.tar.gz.cksum 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32215/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5ee6638..6cf3068 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 -IASL_VERSION=20190108 +IASL_VERSION=20190405 PYTHON_VERSION=3.7.2 EXPAT_VERSION=2.2.6 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190405_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20190108_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190405_iasl.patch index 6532255..be1d84f 100644 --- a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190405_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20190108_/source/compiler/asloptions.c acpica-unix2-20190108/source/compiler/asloptions.c > acpica-unix2-20190108_iasl.patch ---- acpica-unix2-20190108_/source/compiler/asloptions.c -+++ acpica-unix2-20190108/source/compiler/asloptions.c +diff -Naur acpica-unix2-20190405_/source/compiler/asloptions.c acpica-unix2-20190405/source/compiler/asloptions.c > acpica-unix2-20190405_iasl.patch +--- acpica-unix2-20190405_/source/compiler/asloptions.c ++++ acpica-unix2-20190405/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum deleted file mode 100644 index c5cfb4c..0000000 --- a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -50d96dd38b89c69260ad209cf61035cda1fcdd67 tarballs/acpica-unix2-20190108.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190405.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190405.tar.gz.cksum new file mode 100644 index 0000000..b4de752 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190405.tar.gz.cksum @@ -0,0 +1 @@ +245771d956259ccb0281ee86790e87c74ebee5a0 tarballs/acpica-unix2-20190405.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/32215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f800bb459c8bef2658165baad55f30ac17d317 Gerrit-Change-Number: 32215 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: WIP: Make common macros double-evaluation safe
by Julius Werner (Code Review) 18 Apr '19

18 Apr '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32027 Change subject: WIP: Make common macros double-evaluation safe ...................................................................... WIP: Make common macros double-evaluation safe Just shaking the Jenkins tree to see what falls out for now... Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d --- M payloads/libpayload/include/compiler.h M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/stdlib.h M src/commonlib/include/commonlib/compiler.h M src/commonlib/include/commonlib/helpers.h 5 files changed, 113 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32027/1 diff --git a/payloads/libpayload/include/compiler.h b/payloads/libpayload/include/compiler.h index a830239..4ca9bad 100644 --- a/payloads/libpayload/include/compiler.h +++ b/payloads/libpayload/include/compiler.h @@ -26,4 +26,18 @@ #define __always_unused __attribute__((unused)) #define __must_check __attribute__((warn_unused_result)) +/* This evaluates to the first expression, unless that is constant in which case + it evalutates to the second. This is useful to write typeof() macros in a way + that they don't get hung up on the type of literal expressions (e.g. compare + an integer literal which is signed by default with a size_t variable). It is + generally a safe thing to do because if the constant doesn't fit into the + chosen type, you'll get a -Werror=overflow at compile time. */ +#define __SELECT_NON_CONST(expr, fallback_expr) __builtin_choose_expr( \ + __builtin_constant_p(expr), fallback_expr, expr) + +/* This creates a unique local variable name for use in macros. */ +#define __TMPNAME_3(i) __tmpname_##i +#define __TMPNAME_2(i) __TMPNAME_3(i) +#define __TMPNAME __TMPNAME_2(__COUNTER__) + #endif diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 0b9ab0d..c889605 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -66,10 +66,32 @@ #include <pci.h> #include <archive.h> -#define MIN(a,b) ((a) < (b) ? (a) : (b)) -#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) + +#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \ + __typeof__(__SELECT_NON_CONST(a, b)) var_a = a; \ + __typeof__(__SELECT_NON_CONST(b, a)) var_b = b; \ + var_a op var_b ? var_a : var_b; \ +}) + +#define __CMP(a, b, op) (__builtin_constant_p(a) && __builtin_constant_p(b) ? \ + __CMP_UNSAFE(a, b, op) : __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) + +#define MIN(a, b) __CMP(a, b, <) +#define MAX(a, b) __CMP(a, b, >) + +/* __typeof__ doesn't work on bitfield members, so provide these alternatives */ +#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <) +#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >) + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#define DIV_ROUND_UP(x, y) ({ \ + __typeof__(x) _div_local_x = x; \ + __typeof__(y) _div_local_y = y; \ + ((_div_local_x) + (_div_local_y) - 1) / (_div_local_y); \ +}) + static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; } #define LITTLE_ENDIAN 1234 diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index aaacc87..0b42ce2 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -35,8 +35,12 @@ #include <stddef.h> #include <string.h> +#define __ALIGN_MASK(x, mask) ({ \ + typeof(mask) _align_mask_local_mask = mask; \ + ((x) + _align_mask_local_mask) & ~_align_mask_local_mask; \ +}) + #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x,a) ALIGN((x),(a)) #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) #define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) diff --git a/src/commonlib/include/commonlib/compiler.h b/src/commonlib/include/commonlib/compiler.h index 2e0c454..e3d0f95 100644 --- a/src/commonlib/include/commonlib/compiler.h +++ b/src/commonlib/include/commonlib/compiler.h @@ -48,4 +48,18 @@ #define __always_inline inline __attribute__((always_inline)) #endif +/* This evaluates to the first expression, unless that is constant in which case + it evalutates to the second. This is useful to write typeof() macros in a way + that they don't get hung up on the type of literal expressions (e.g. compare + an integer literal which is signed by default with a size_t variable). It is + generally a safe thing to do because if the constant doesn't fit into the + chosen type, you'll get a -Werror=overflow at compile time. */ +#define __SELECT_NON_CONST(expr, fallback_expr) __builtin_choose_expr( \ + __builtin_constant_p(expr), fallback_expr, expr) + +/* This creates a unique local variable name for use in macros. */ +#define __TMPNAME_3(i) __tmpname_##i +#define __TMPNAME_2(i) __TMPNAME_3(i) +#define __TMPNAME __TMPNAME_2(__COUNTER__) + #endif diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index adc43ca..65c122e 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -23,41 +23,76 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #endif +#define __ALIGN_MASK(x, mask) ({ \ + __typeof__(mask) _align_mask_local_mask = mask; \ + ((x) + _align_mask_local_mask) & ~_align_mask_local_mask; \ +}) + #define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL) -#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x, a) ALIGN((x), (a)) #define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL)) #define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0) +#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) + +#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \ + __typeof__(__SELECT_NON_CONST(a, b)) var_a = a; \ + __typeof__(__SELECT_NON_CONST(b, a)) var_b = b; \ + var_a op var_b ? var_a : var_b; \ +}) + +#define __CMP(a, b, op) __builtin_choose_expr( \ + __builtin_constant_p(a) && __builtin_constant_p(b), \ + __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) + #ifndef MIN -#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MIN(a, b) __CMP(a, b, <) #endif #ifndef MAX -#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MAX(a, b) __CMP(a, b, >) #endif -#define ABS(a) (((a) < 0) ? (-(a)) : (a)) -#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) -#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) -#define SWAP(a, b) do { \ - typeof(a) tmp = a; \ - a = (typeof(a)) b; \ - b = (typeof(b)) tmp; \ - } while (0) + +/* __typeof__ doesn't work on bitfield members, so provide these alternatives */ +#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <) +#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >) + +#define ABS(a) ({ \ + __typeof__(a) _abs_local_a = a; \ + ((_abs_local_a) < 0) ? (-(_abs_local_a)) : (_abs_local_a); \ +}) + +#define IS_POWER_OF_2(x) ({ \ + __typeof__(x) _power_local_x = x; \ + ((_power_local_x) & ((_power_local_x) - 1)) == 0; \ +}) + +#define DIV_ROUND_UP(x, y) ({ \ + __typeof__(x) _div_local_x = x; \ + __typeof__(y) _div_local_y = y; \ + ((_div_local_x) + (_div_local_y) - 1) / (_div_local_y); \ +}) + +#define SWAP(a, b) do { \ + __typeof__(&a) _swap_local_a = &a; \ + __typeof__(&b) _swap_local_b = &b; \ + __typeof__(a) _swap_local_tmp = *_swap_local_a; \ + *_swap_local_a = *_swap_local_b; \ + *_swap_local_b = _swap_local_tmp; \ +} while (0) + /* * Divide positive or negative dividend by positive divisor and round * to closest integer. Result is undefined for negative divisors and * for negative dividends if the divisor variable type is unsigned. */ -#define DIV_ROUND_CLOSEST(x, divisor)( \ -{ \ - typeof(x) __x = x; \ - typeof(divisor) __d = divisor; \ - (((typeof(x))-1) > 0 || \ - ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ - (((__x) + ((__d) / 2)) / (__d)) : \ - (((__x) - ((__d) / 2)) / (__d)); \ -} \ -) +#define DIV_ROUND_CLOSEST(x, divisor)({ \ + __typeof__(x) _div_local_x = x; \ + __typeof__(divisor) _div_local_d = divisor; \ + (((__typeof__(x))-1) > 0 || \ + ((__typeof__(divisor))-1) > 0 || (_div_local_x) > 0) ? \ + (((_div_local_x) + ((_div_local_d) / 2)) / (_div_local_d)) : \ + (((_div_local_x) - ((_div_local_d) / 2)) / (_div_local_d)); \ +}) /* Standard units. */ #define KiB (1<<10) -- To view, visit https://review.coreboot.org/c/coreboot/+/32027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d Gerrit-Change-Number: 32027 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 30

Change in ...coreboot[master]: Add support for low power idle table
by Paul Menzel (Code Review) 18 Apr '19

18 Apr '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: Add support for low power idle table ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/32350/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32350/2//COMMIT_MSG@7 PS2, Line 7: Add support for low power idle table Please prefix with x86. https://review.coreboot.org/#/c/32350/2//COMMIT_MSG@9 PS2, Line 9: kernel Chromium OS kernel -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 18 Apr 2019 14:53:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 18 Apr '19

18 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 21: (2 comments) https://review.coreboot.org/#/c/30414/21/src/mainboard/facebook/fbg1701/irq… File src/mainboard/facebook/fbg1701/irqroute.h: https://review.coreboot.org/#/c/30414/21/src/mainboard/facebook/fbg1701/irq… PS21, Line 40: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/30414/21/src/mainboard/facebook/fbg1701/irq… PS21, Line 62: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 21 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Thu, 18 Apr 2019 12:45:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Revert "soc/intel/common/block: add VMX support"
by Angel Pons (Code Review) 18 Apr '19

18 Apr '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29683 ) Change subject: Revert "soc/intel/common/block: add VMX support" ...................................................................... Patch Set 4: Any news about this? -- To view, visit https://review.coreboot.org/c/coreboot/+/29683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a5d558b03497d106083eece10c5b34e0e7cbb2d Gerrit-Change-Number: 29683 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 18 Apr 2019 12:40:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: acpi: Upgrade acpi generate header
by Paul Menzel (Code Review) 18 Apr '19

18 Apr '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32328 ) Change subject: acpi: Upgrade acpi generate header ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/32328/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32328/3//COMMIT_MSG@9 PS3, Line 9: to be match with laetst the match the latest https://review.coreboot.org/#/c/32328/3//COMMIT_MSG@11 PS3, Line 11: What problem does this fix? Or is it just for being up to date? Please add the acpica commit hash you took the header from. -- To view, visit https://review.coreboot.org/c/coreboot/+/32328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128 Gerrit-Change-Number: 32328 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 18 Apr 2019 12:09:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Add support for low power idle table
by Patrick Rudolph (Code Review) 18 Apr '19

18 Apr '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: Add support for low power idle table ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/32350/2/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/#/c/32350/2/src/arch/x86/acpi.c@1108 PS2, Line 1108: #if CONFIG(ACPI_LPIT) no need for preprocessor https://review.coreboot.org/#/c/32350/2/src/arch/x86/acpi.c@1112 PS2, Line 1112: unsigned long current = (unsigned long)lpit + sizeof(acpi_table_lpit); can be removed https://review.coreboot.org/#/c/32350/2/src/arch/x86/acpi.c@1151 PS2, Line 1151: /* (Re)calculate length and checksum. */ why? you did not increase current? https://review.coreboot.org/#/c/32350/2/src/arch/x86/acpi.c@1343 PS2, Line 1343: #if CONFIG(ACPI_LPIT) use if(CONFIG(ACPI_LPIT)). The linker will drop unused code. -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Apr 2019 10:20:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/cnl: Generate ACPI DMAR table
by John Zhao (Code Review) 18 Apr '19

18 Apr '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31917 Change subject: soc/intel/cnl: Generate ACPI DMAR table ...................................................................... soc/intel/cnl: Generate ACPI DMAR table SoC is detected Vt-d capable. ACPI DMAR table is created and DMA-remapping hardware units entries are programmed. Device scope like IOAPIC and HPET will be added once cnl fsp upd update is available. Change-Id: I4e1ee5244c67affb13947436d81628c5dc665c9e Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/systemagent.h M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/systemagent.c M src/soc/intel/cannonlake/systemagent.c 8 files changed, 157 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31917/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 639f6c6..864cbe9 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -17,19 +17,22 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> #include <chip.h> +#include <device/mmio.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> +#include <intelblocks/p2sb.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/systemagent.h> #include <string.h> #include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> @@ -285,3 +288,78 @@ { return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); } + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; + + /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ + if (igfx_dev && igfx_dev->enabled && gfxvten && + gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; + + /* General VTBAR has to be set and in 32-bit space. */ + if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; + + /* P2SB may already be hidden. There's no clear rule, when. */ + const u8 p2sb_hidden = + pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); + + const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *dev, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + const struct soc_intel_cannonlake_config *const config = dev->chip_info; + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* Create DMAR table only if we have Vt-d capability */ + if ((config && config->ignore_vtd) || !soc_is_vtd_capable()) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 993e7f3..050e026 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -196,6 +196,7 @@ .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = &sa_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3e4bafc..1574b8e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -221,6 +221,9 @@ /* Estimated maximum platform power in Watts */ uint16_t psys_pmax; + /* Whether to ignore VT-d support of the SKU */ + int ignore_vtd; + /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; /* Enable VR specific mailbox command diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index ed9b29f..100bd11 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -52,6 +52,15 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfc000000 #define REG_BASE_SIZE 0x1000 diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h index da83c38..390bd56 100644 --- a/src/soc/intel/cannonlake/include/soc/systemagent.h +++ b/src/soc/intel/cannonlake/include/soc/systemagent.h @@ -30,10 +30,15 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) -#define BIOS_RESET_CPL 0x5da8 -#define EDRAMBAR 0x5408 -#define REGBAR 0x5420 +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define IPUVTBAR 0x7884 +#define VTVC0BAR 0x5410 +#define REGBAR 0x5420 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 @@ -43,4 +48,11 @@ #define IMRBASE 0x6A40 #define IMRLIMIT 0x6A48 +bool soc_is_vtd_capable(void); + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; #endif diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5597c4f..04a24a1 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -98,6 +98,7 @@ assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *t_cfg = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg, config); @@ -109,6 +110,15 @@ /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; + /* Enable VT-d and X2APIC */ + if (!config->ignore_vtd) { + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->X2ApicOptOut = 0; + t_cfg->VtdDisable = 0; + } + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c index 61db22e..6fb3917 100644 --- a/src/soc/intel/cannonlake/romstage/systemagent.c +++ b/src/soc/intel/cannonlake/romstage/systemagent.c @@ -16,10 +16,31 @@ */ #include <device/device.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/systemagent.h> +#include "chip.h" + +static void systemagent_vtd_init(void) +{ + const struct device *const dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct soc_intel_cannonlake_config *config = NULL; + + if (dev) + config = dev->chip_info; + if (config && config->ignore_vtd) + return; + + const bool vtd_capable = + !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + if (!vtd_capable) + return; + + sa_set_mch_bar(soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); +} void systemagent_early_init(void) { @@ -40,6 +61,9 @@ /* Set Fixed MMIO address into MCH base address */ sa_set_mch_bar(soc_fixed_mch_resources, ARRAY_SIZE(soc_fixed_mch_resources)); + + systemagent_vtd_init(); + /* Enable PAM registers */ enable_pam_region(); } diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 9c8d761..4ff4c1c 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -18,10 +18,19 @@ #include <device/device.h> #include <delay.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/systemagent.h> +#include "chip.h" + +bool soc_is_vtd_capable(void) +{ + struct device *const root_dev = SA_DEV_ROOT; + return root_dev && + !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); +} /* * SoC implementation @@ -31,6 +40,8 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { + const struct soc_intel_cannonlake_config *const config = dev->chip_info; + static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -54,6 +65,11 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) { + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); + } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/31917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1ee5244c67affb13947436d81628c5dc665c9e Gerrit-Change-Number: 31917 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

6 35

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2019