Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 )
Change subject: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/31902/1/src/soc/intel/cannonlake/pmutil.c
File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/#/c/31902/1/src/soc/intel/cannonlake/pmutil.c@1…
PS1, Line 146: pmc_clear_suspwrflr
> Can you please push a separate CL for this?
Done
https://review.coreboot.org/#/c/31902/1/src/soc/intel/cannonlake/pmutil.c@2…
PS1, Line 236: pmc_clear_suspwrflr
> I don't think this is the right place to do this. […]
Agree. I have made the necessary changes as suggested.
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Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31902
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
......................................................................
soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the SUS_PWR_FLR bit.
BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”
For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"
Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/soc/intel/cannonlake/include/soc/pm.h
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/cannonlake/pmutil.c
3 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31902/3
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Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31902
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
......................................................................
soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the SUS_PWR_FLR bit.
BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”
For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"
Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/soc/intel/cannonlake/include/soc/pm.h
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/cannonlake/pmutil.c
3 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31902/2
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Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30895
Change subject: 1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asus/f2a85-m
......................................................................
1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asus/f2a85-m
Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
---
A Documentation/mainboard/asus/f2a85-m.md
1 file changed, 271 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/30895/1
diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md
new file mode 100644
index 0000000..c4ee0cf
--- /dev/null
+++ b/Documentation/mainboard/asus/f2a85-m.md
@@ -0,0 +1,271 @@
+Disclaimer: This board is not widely sold any longer. However, refer to F2A85 series status for newer models. ASUS F2A85 PRO should be work in progress (WIP).
+Contents
+
+ 1 Status
+ 1.1 Supported processing units
+ 1.1.1 CPUs
+ 1.1.2 APUs
+ 1.2 Notes
+ 1.3 TODOs
+ 2 UEFI builds that allow flash chip access
+ 3 Hardware info
+ 3.1 DDR voltage controller
+ 3.2 The ASUS digi VRM
+ 3.3 Memory
+ 4 See also
+ 4.1 F2A85 series status
+ 5 References
+
+Status
+Device/functionality Status Comments
+CPU
+CPU works OK the board will start with an AMD A8-5500
+L1 cache enabled OK
+L2 cache enabled OK
+L3 cache enabled N/A
+Multiple CPU support OK
+Multi-core support OK
+Hardware virtualization Untested
+RAM
+EDO N/A
+SDRAM N/A
+SO-DIMM N/A
+DDR N/A
+DDR2 N/A
+DDR3 OK Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!
+Dual channel support OK
+ECC support N/A
+On-board Hardware
+On-board IDE 3.5" N/A
+On-board IDE 2.5" N/A
+On-board SATA OK Tested all ports of sixpack.
+On-board SCSI N/A
+On-board USB OK Issues with XHCI exist with Asus' BIOS as well
+On-board VGA OK Use dd to extract the legacy BIOS, HDMI untested
+On-board Ethernet OK
+On-board Audio OK tested with headphones in line-out (lime colored)
+On-board Modem N/A
+On-board FireWire N/A
+On-board Smartcard reader N/A
+On-board CompactFlash N/A
+On-board PCMCIA N/A
+On-board Wifi N/A
+On-board Bluetooth N/A
+On-board SD card reader N/A
+Add-on slots/cards
+ISA add-on cards N/A
+Audio/Modem-Riser (AMR/CNR) cards N/A
+PCI add-on cards OK
+Mini-PCI add-on cards N/A
+Mini-PCI-Express add-on cards Unknown
+PCI-X add-on cards N/A
+AGP graphics cards N/A
+PCI Express x1 add-on cards OK
+PCI Express x2 add-on cards N/A
+PCI Express x4 add-on cards OK
+PCI Express x8 add-on cards N/A
+PCI Express x16 add-on cards OK
+PCI Express x32 add-on cards N/A
+HTX add-on cards N/A
+Legacy / Super I/O
+Floppy N/A
+Serial port 1 (COM1) OK
+Serial port 2 (COM2) N/A
+Parallel port N/A
+PS/2 keyboard OK
+PS/2 mouse Untested
+Game port N/A
+Infrared ?
+PC speaker OK
+DiskOnChip N/A
+Input
+Trackpoint N/A
+Touchpad N/A
+Fn Hotkeys N/A
+Fingerprint Reader N/A
+Laptop
+Docking VGA N/A
+Docking LAN N/A
+Docking USB N/A
+Docking Audio N/A
+Docking Displayport N/A
+Thinklight N/A
+Webcam N/A
+Miscellaneous
+Sensors / fan control Untested
+Hardware watchdog Unknown
+SMBus Unknown
+CAN bus N/A
+CPU frequency scaling OK
+Other powersaving features ?
+ACPI OK ACPI power button event works, suspend is WIP (work in progress).
+Reboot OK warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot
+Poweroff OK
+Suspend OK
+Nonstandard LEDs OK
+High precision event timers (HPET) OK
+Random number generator (RNG) ?
+Wake on modem ring Untested
+Wake on LAN Untested
+Wake on keyboard Untested
+Wake on mouse Untested
+TPM Unknown
+Flashrom OK
+Supported processing units
+
+ASUS F2A85-M CPU specification:[1]
+
+ AMD Socket FM2 Athlon�/A- Series Processors
+ Supports CPU up to 4 cores
+ Supports AMD� Turbo Core 3.0 Technology
+ Addenum: AMD Sempron X2 250[2]
+
+Note: Only AMD Virgo: "Trinity" desktop processing units are supported (see list below) but with a hack also Richland desktop processing units might work (contact via mailing list for details). Wikipedia's list of Trinity processors might be more actively maintained.
+CPUs
+
+ AMD Athlon X2 340
+ AMD Athlon X4 740
+ AMD Athlon X4 750k
+
+APUs
+
+The CPU architecture in these APUs are Piledriver, and their GPU is TeraScale 3 (VLIW4-based).
+
+ AMD A4-5300
+ AMD A4-5300B
+ AMD A6-5400K
+ AMD A6-5400B
+ AMD A8-5500
+ AMD A8-5500B
+ AMD A8-5600K
+ AMD A10-5700
+ AMD A10-5800B
+ AMD A10-5800K
+ AMD FirePro A300 - Only sold by OEM
+ AMD FirePro A320 - Only sold by OEM
+
+Notes
+
+ Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+(source)
+
+For internal VGA: Boot the legacy BIOS, and use VGA_support chapter
+
+ Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.
+ If you use PS/2 de-select legacy free
+ De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios
+ It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read SeaBIOS for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.
+ its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:
+ CONFIG_VGA_ROM_RUN=y
+ CONFIG_PCI_ROM_RUN=y
+ CONFIG_ON_DEVICE_ROM_RUN=y
+ Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.
+
+TODOs
+
+ test virtualization
+ test IOMMU
+ test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.
+ blink in suspend mode (GP43, program LDN7 F8=23 and blink with F9=2 for 1s blinks)
+ fix mptable
+ fix resume with USB3.0 used (perhaps there is a bug in resume.c)
+ fix immediate resume after suspend (perhaps PCIe STS needs to be cleared)
+
+UEFI builds that allow flash chip access
+
+ v5016 is untested, but expected to work as well
+ v5018
+ v5103
+ v5104
+ v5107
+ v5202
+ v6002
+ v6004
+ v6102
+ v6402
+ v6404 (requires downgrading to v6402 to flash coreboot)
+ v6501 (requires downgrading to v6402 to flash coreboot)
+ v6502 (requires downgrading to v6402 to flash coreboot)
+
+Build v6502, v6501 and v6404 do not allow access to the flash chip.
+
+Fortunately it is possible to downgrade build v6502, v6501 and v6404 to v6402, with EZFlash.
+
+Downgrading is done by downloading build v6402 from ASUS' F2A85-M download page and copying it to (the root directory of) a FAT32 formatted USB flash drive.
+
+Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".
+Hardware info
+
+This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:
+Winbond 25Q64F
+
+The chip manual is available here
+
+For out of band flashing, I use a
+
+ 3M test clip model 923739-08-ND
+
+It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:
+
+\# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom
+flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)
+flashrom is free software, get the source code at http://www.flashrom.org
+
+Calibrating delay loop... OK.
+Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.
+Reading old flash chip contents... done.
+Erasing and writing flash chip... Erase/write done.
+Verifying flash... VERIFIED.
+
+real 35m35.409s
+user 0m55.976s
+sys 0m12.920s
+
+DDR voltage controller
+
+The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).
+The ASUS digi VRM
+
+The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)
+Memory
+
+If you use single dimm plug it to DIMM_A2 or DIMM_B2.
+
+I use:
+
+2x 2GB DDR3 modules in blue slots:
+
+\#modprobe i2c-piix4
+\#modprobe eeprom
+\#decode-dimms
+
+---=== Memory Characteristics ===---
+Fine time base 2.500 ps
+Medium time base 0.125 ns
+Maximum module speed 1333MHz (PC3-10666)
+Size 2048 MB
+Banks x Rows x Columns x Bits 8 x 14 x 10 x 64
+Ranks 2
+SDRAM Device Width 8 bits
+tCL-tRCD-tRP-tRAS 8-8-8-24
+Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T
+
+See also
+F2A85 series status
+
+Only boards with internal wiki page links are Supported Motherboards.
+
+ ASUS F2A85-M
+ ASUS F2A85-M LE
+ ASUS F2A85-M PRO[3] - the most available model in the entire F2A85 series. Be sure to check its status to see what works and what doesn't.
+ ASUS F2A85-M2 - Confirmed working in the #coreboot IRC channel 2015-03-04. Unsure if WIP.
+ ASUS F2A85-M/CSM - Unsure if WIP.
+
+References
+
+ Jump up ↑ https://www.asus.com/Motherboards/F2A85M/specifications/
+ Jump up ↑ http://support.asus.com/Cpusupport/List.aspx?SLanguage=en&m=F2A85-M&p=1&s=43
+ Jump up ↑ http://www.asus.com/Motherboards/F2A85M_PRO/
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 )
Change subject: device/pci: Rewrite PCI MMCONF with symbol reference
......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/#/c/31752/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31752/4//COMMIT_MSG@19
PS4, Line 19: value from a 'struct device *'.
Trying to read this without the OOB communication of the
past days in mind: We should somehow mention that this
applies to multiple writes to the same device.
https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h
File src/include/device/pci_mmio_cfg.h:
https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@29
PS4, Line 29: };
Doesn't the same apply to `arch/mmio.h`?
Just wondering if that's not the better place. And we could
use readxx()/writexx() below.
In any case, it doesn't seem very obvious why we have that
union. So I'd expect a comment here with the same reasoning
as in the commit message.
Wait... do we need the union? I would assume now, that a
struct, e.g. `struct pci8 { uint8_t reg[4096]; };` would
produce the same result. I wouldn't have a preference,
though.
https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@31
PS4, Line 31: extern u8 *const pci_mmconf;
Adding this variable seems unrelated now (not covered by
the commit message any more). Maybe make it two changes?
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 )
Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
......................................................................
Patch Set 55:
> > Yes @Idwer, can you please help me to know your requirements so
> that i can intercept the same in this CL or future CL as it
> required.
>
> I can't speak for Idwer, but he seemed to have similar thoughts.
> Here are mine:
>
> 1. Stop replacing open-source coreboot functionality with blobs.
> The justification for this change seems to be that the SkipMpInit
> option will vanish. To me, it seems like a huge offense to
> coreboot.
> There are hundreds of copyright holders on the open-source side
> and a single one on the blob side, yet the blob side enforces their
> will. This change shows me that even after the past 5 years of
> FSP integration and promises, we are still running coreboot down
> further and further. Maybe this is a strategy? only stop when
> coreboot development has become that expensive that nobody
> wants it anymore? At least for a smaller company, the one I work
> for, the costs for coreboot development exploded since the
> introduction of FSP.
>
> 2. In case 1. happens anyway, find a less offensive way to
> integrate the blob. Calling GPL code from the blob makes it
> harder for me to see them as separate works as requested by
> the GPL (not to mention the requested separate distribution).
> We have learned during the discussion of this change that there
> are alternatives that could avoid calling GPL code from the blob.
> In that case, coreboot and FSP would run redundant code and I
> assume things would be slowed down. So I see this change as a
> mitigation for the ugly design of FSP, spitting into the faces
> of contributors that saw their code protected by the GPL.
Patrick has already driving one discussion for the same matter, hopefully we will see some good direction soon.
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Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31023
Change subject: [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant
......................................................................
[TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant
This creates a phasal variant for octopus. Nothing is set in the variant
files here; everything is picked up from baseboard.
BUG=b:None
TEST=None
Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e
Signed-off-by: “raymondchung” <“raymondchung(a)ami.corp-partner.google.xn--com-9o0a>
---
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/octopus/Kconfig.name
A src/mainboard/google/octopus/variants/phasal/Makefile.inc
A src/mainboard/google/octopus/variants/phasal/gpio.c
A src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl
A src/mainboard/google/octopus/variants/phasal/include/variant/ec.h
A src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h
A src/mainboard/google/octopus/variants/phasal/overridetree.cb
A src/mainboard/google/octopus/variants/phasal/variant.c
9 files changed, 358 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31023/1
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index a237741..a62cd19 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -56,6 +56,7 @@
default "meep" if BOARD_GOOGLE_MEEP
default "ampton" if BOARD_GOOGLE_AMPTON
default "casta" if BOARD_GOOGLE_CASTA
+ default "phasal" if BOARD_GOOGLE_PHASAL
default "octopus" if BOARD_GOOGLE_OCTOPUS
config DEVICETREE
@@ -76,6 +77,7 @@
default "Meep" if BOARD_GOOGLE_MEEP
default "Ampton" if BOARD_GOOGLE_AMPTON
default "Casta" if BOARD_GOOGLE_CASTA
+ default "Phasal" if BOARD_GOOGLE_PHASAL
default "Octopus" if BOARD_GOOGLE_OCTOPUS
config MAINBOARD_FAMILY
@@ -93,6 +95,7 @@
default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP
default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON
default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA
+ default "PHASAL TEST 7167" if BOARD_GOOGLE_PHASAL
default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
config MAX_CPUS
diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name
index 498da36..71e5197 100644
--- a/src/mainboard/google/octopus/Kconfig.name
+++ b/src/mainboard/google/octopus/Kconfig.name
@@ -52,3 +52,9 @@
select BASEBOARD_OCTOPUS_LAPTOP
select BOARD_GOOGLE_BASEBOARD_OCTOPUS
select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
+
+config BOARD_GOOGLE_PHASAL
+ bool "-> Phasal"
+ select BASEBOARD_OCTOPUS_LAPTOP
+ select BOARD_GOOGLE_BASEBOARD_OCTOPUS
+ select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
diff --git a/src/mainboard/google/octopus/variants/phasal/Makefile.inc b/src/mainboard/google/octopus/variants/phasal/Makefile.inc
new file mode 100644
index 0000000..d54ed40
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-y += gpio.c
+
+ramstage-y += variant.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/octopus/variants/phasal/gpio.c b/src/mainboard/google/octopus/variants/phasal/gpio.c
new file mode 100644
index 0000000..322b44b
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/gpio.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+#include <console/console.h>
+
+#define SKU_UNKNOWN 0xFFFFFFFF
+
+static const struct pad_config default_override_table[] = {
+ PAD_NC(GPIO_52, UP_20K),
+ PAD_NC(GPIO_53, UP_20K),
+ PAD_NC(GPIO_67, UP_20K),
+ PAD_NC(GPIO_117, UP_20K),
+ PAD_NC(GPIO_143, UP_20K),
+
+ /* EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
+ DISPUPD),
+
+ PAD_NC(GPIO_161, DN_20K),
+
+ /* EN_PP3300_WLAN_L */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),
+
+ PAD_NC(GPIO_213, DN_20K),
+ PAD_NC(GPIO_214, DN_20K),
+};
+
+static const struct pad_config sku1_default_override_table[] = {
+ /* disable I2C7 SCL and SDA */
+ PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */
+ PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */
+
+ PAD_NC(GPIO_52, UP_20K),
+ PAD_NC(GPIO_53, UP_20K),
+ PAD_NC(GPIO_67, UP_20K),
+ PAD_NC(GPIO_117, UP_20K),
+ PAD_NC(GPIO_143, UP_20K),
+
+ /* EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
+ DISPUPD),
+
+ PAD_NC(GPIO_161, DN_20K),
+
+ /* EN_PP3300_WLAN_L */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0,
+ DISPUPD),
+
+ PAD_NC(GPIO_213, DN_20K),
+ PAD_NC(GPIO_214, DN_20K),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+ const struct pad_config *c;
+ uint32_t sku_id = SKU_UNKNOWN;
+
+ google_chromeec_cbi_get_sku_id(&sku_id);
+ if (sku_id == 1) {
+ c = sku1_default_override_table;
+ *num = ARRAY_SIZE(sku1_default_override_table);
+ } else {
+ c = default_override_table;
+ *num = ARRAY_SIZE(default_override_table);
+ }
+
+ return c;
+}
diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..cc17d56
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h
new file mode 100644
index 0000000..16f931b
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h
new file mode 100644
index 0000000..1fd1e11
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/octopus/variants/phasal/overridetree.cb b/src/mainboard/google/octopus/variants/phasal/overridetree.cb
new file mode 100644
index 0000000..b131173
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/overridetree.cb
@@ -0,0 +1,164 @@
+chip soc/intel/apollolake
+
+ # EMMC Tx CMD Delay
+ # Refer to EDS-Vol2-16.32.
+ # [14:8] steps of delay for DDR mode, each 125ps.
+ # [6:0] steps of delay for SDR mode, each 125ps.
+ register "emmc_tx_cmd_cntl" = "0x505"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-16.33.
+ # [14:8] steps of delay for HS400, each 125ps.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps.
+ register "emmc_tx_data_cntl1" = "0x0b0c"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-16.34.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_tx_data_cntl2" = "0x1c282929"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-16.35.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_rx_cmd_data_cntl1" = "0x00181b1b"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-16.37.
+ # [17:16] stands for Rx Clock before Output Buffer
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+ # [6:0] steps of delay for HS200, each 125ps.
+ register "emmc_rx_cmd_data_cntl2" = "0x10028"
+
+ # EMMC Rx Strobe Delay
+ # Refer to EDS-Vol2-16.36.
+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
+ register "emmc_rx_strobe_cntl" = "0x0b0b"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Digitizer |
+ #| I2C5 | Audio |
+ #| I2C6 | Trackpad |
+ #| I2C7 | Touchscreen |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 66,
+ .fall_time_ns = 90,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 104,
+ .fall_time_ns = 52,
+ },
+ .i2c[6] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 66,
+ .fall_time_ns = 90,
+ .data_hold_time_ns = 350,
+ },
+ .i2c[7] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 76,
+ .fall_time_ns = 164,
+ },
+ }"
+
+ device domain 0 on
+ device pci 16.0 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""WCOM50C1""
+ register "generic.desc" = ""WCOM Digitizer""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+ register "generic.reset_delay_ms" = "20"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x1"
+ device i2c 0x9 on end
+ end
+ end # - I2C 0
+ device pci 17.1 on
+ chip drivers/i2c/da7219
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
+ register "btn_cfg" = "50"
+ register "mic_det_thr" = "500"
+ register "jack_ins_deb" = "20"
+ register "jack_det_rate" = ""32ms_64ms""
+ register "jack_rem_deb" = "1"
+ register "a_d_btn_thr" = "0xa"
+ register "d_b_btn_thr" = "0x16"
+ register "b_c_btn_thr" = "0x21"
+ register "c_mic_btn_thr" = "0x3e"
+ register "btn_avg" = "4"
+ register "adc_1bit_rpt" = "1"
+ register "micbias_lvl" = "2600"
+ register "mic_amp_in_sel" = ""diff""
+ device i2c 1a on end
+ end
+ end # - I2C 5
+ device pci 17.2 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
+ register "wake" = "GPE0_DW3_27"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
+ register "generic.wake" = "GPE0_DW3_27"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 0x2c on end
+ end
+ end # - I2C 6
+ device pci 17.3 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
+ register "reset_delay_ms" = "20"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
+ register "enable_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ device i2c 10 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""SYTS7817""
+ register "generic.desc" = ""Synaptics Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
+ register "generic.reset_delay_ms" = "45"
+ register "generic.has_power_resource" = "1"
+ register "generic.disable_gpio_export_in_crs" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 20 on end
+ end
+ end # - I2C 7
+ end
+end
diff --git a/src/mainboard/google/octopus/variants/phasal/variant.c b/src/mainboard/google/octopus/variants/phasal/variant.c
new file mode 100644
index 0000000..22f4f71
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/variant.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+
+#define SKU_UNKNOWN 0xFFFFFFFF
+
+void variant_update_devtree(struct device *dev)
+{
+ uint32_t sku_id = SKU_UNKNOWN;
+ struct device *touchscreen_i2c_host;
+
+ touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7);
+
+ if (touchscreen_i2c_host == NULL)
+ return;
+
+ /* SKU ID 1 does not have a touchscreen device, hence disable it. */
+ google_chromeec_cbi_get_sku_id(&sku_id);
+ if (sku_id == 1)
+ touchscreen_i2c_host->enabled = 0;
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/31023
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e
Gerrit-Change-Number: 31023
Gerrit-PatchSet: 1
Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com>
Gerrit-MessageType: newchange
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 )
Change subject: soc/intel/cannonlake: Fix prev_sleep_state issue
......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31902/1/src/soc/intel/cannonlake/pmutil.c
File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/#/c/31902/1/src/soc/intel/cannonlake/pmutil.c@1…
PS1, Line 146: pmc_clear_suspwrflr
Can you please push a separate CL for this?
https://review.coreboot.org/#/c/31902/1/src/soc/intel/cannonlake/pmutil.c@2…
PS1, Line 236: pmc_clear_suspwrflr
I don't think this is the right place to do this. Probably pmc_init?
--
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Gerrit-Branch: master
Gerrit-Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Gerrit-Change-Number: 31902
Gerrit-PatchSet: 1
Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Comment-Date: Fri, 15 Mar 2019 06:51:08 +0000
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