coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: ec/google/wilco: coalesce tent mode to tablet mode
by Jett Rink (Code Review) 15 Mar '19

15 Mar '19

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31907 Change subject: ec/google/wilco: coalesce tent mode to tablet mode ...................................................................... ec/google/wilco: coalesce tent mode to tablet mode Both tent mode (0x01) and tablet mode (0x02) should be considered tablet mode by ChromeOS. BRANCH=none BUG=b:122052438 TEST=ChromeOS enters tablet mode when lid angle exceeds 180 Change-Id: I89ba8141350fc628c8cff89d5f33aa47c6ae6afe Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- M src/ec/google/wilco/acpi/ec_ram.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31907/1 diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index b7cfefa..59bd78e 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -116,7 +116,7 @@ Name (DRTQ, Package () { 0x38, 0xff, RD }) /* DPTF: Read Trip Query */ Name (ORST, Package () { 0x39, 0xff, RD }) /* Orientation State */ -Name (OTBL, Package () { 0x39, 0x02, RD }) /* Orientation: Tablet mode */ +Name (OTBL, Package () { 0x39, 0x03, RD }) /* Orient: Tablet/Tent mode */ Name (OREV, Package () { 0x3a, 0xff, RD }) /* Orientation Events */ Name (OECH, Package () { 0x3a, 0x01, RD }) /* Event: Orientation */ Name (OERL, Package () { 0x3a, 0x02, RD }) /* Event: Rotation Lock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89ba8141350fc628c8cff89d5f33aa47c6ae6afe Gerrit-Change-Number: 31907 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable TBMC device
by Dtrain Hsu (Code Review) 15 Mar '19

15 Mar '19

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31869 Change subject: mb/google/hatch: Enable TBMC device ...................................................................... mb/google/hatch: Enable TBMC device This change enables tablet mode ACPI device for all hatch boards. BUG=b:125355874 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I4d3818497172828d750b34fe91cbb6cc65e69fc5 --- M src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/31869/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index 75d583e..086914e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -74,6 +74,9 @@ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d3818497172828d750b34fe91cbb6cc65e69fc5 Gerrit-Change-Number: 31869 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: vboot: rename symbols for better consistency
by Joel Kitching (Code Review) 15 Mar '19

15 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31886 Change subject: vboot: rename symbols for better consistency ...................................................................... vboot: rename symbols for better consistency Symbols prefixed with vb2_ should be reserved for internal vboot library use. Anything outside of that may choose some other prefix. Here, we choose vboot_ instead. Also, add some documentation to security/vboot/misc.h, which provides headers for a number of different C files. BUG=b:124141368 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I5d9154fd2d5df25ee254bd5ce4a173afaa6588be Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/bootmode.c M src/security/vboot/common.c M src/security/vboot/misc.h M src/security/vboot/vboot_handoff.c M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c 6 files changed, 77 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31886/1 diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index fb1fc46..3fb693d 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -23,23 +23,23 @@ #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> -static int vb2_get_recovery_reason_shared_data(void) +static int vboot_get_recovery_reason_shared_data(void) { /* Shared data does not exist for Ramstage and Post-CAR stage. */ if (ENV_RAMSTAGE || ENV_POSTCAR) return 0; - struct vb2_shared_data *sd = vb2_get_shared_data(); + struct vb2_shared_data *sd = vboot_get_shared_data(); assert(sd); return sd->recovery_reason; } -void vb2_save_recovery_reason_vbnv(void) +void vboot_save_recovery_reason_vbnv(void) { if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) return; - int reason = vb2_get_recovery_reason_shared_data(); + int reason = vboot_get_recovery_reason_shared_data(); if (!reason) return; @@ -128,9 +128,9 @@ * verification is already complete and no slot was selected * i.e. recovery path was requested. */ - if (vboot_possibly_executed() && vb2_logic_executed() && - !vb2_is_slot_selected()) - return vb2_get_recovery_reason_shared_data(); + if (vboot_possibly_executed() && vboot_logic_executed() && + !vboot_is_slot_selected()) + return vboot_get_recovery_reason_shared_data(); return 0; } diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index ade1b2c..496ab78 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -36,7 +36,7 @@ * by the vboot2 core. Keep the struct CPU architecture agnostic as it crosses * stage boundaries. */ -struct vb2_working_data { +struct vboot_working_data { struct selected_region selected_region; /* offset of the buffer from the start of this struct */ uint32_t buffer_offset; @@ -44,7 +44,7 @@ }; /* TODO(kitching): Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE instead. */ -static size_t vb2_working_data_size(void) +static size_t vboot_working_data_size(void) { if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) return 12 * KiB; @@ -56,64 +56,64 @@ die("impossible!"); } -static struct vb2_working_data * const vb2_get_working_data(void) +static struct vboot_working_data * const vboot_get_working_data(void) { - struct vb2_working_data *wd = NULL; + struct vboot_working_data *wd = NULL; if (cbmem_possibly_online()) wd = cbmem_find(CBMEM_ID_VBOOT_WORKBUF); if (wd == NULL && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && preram_symbols_available()) - wd = (struct vb2_working_data *)_vboot2_work; + wd = (struct vboot_working_data *)_vboot2_work; assert(wd != NULL); return wd; } -void vb2_init_work_context(struct vb2_context *ctx) +void vboot_init_work_context(struct vb2_context *ctx) { - struct vb2_working_data *wd; + struct vboot_working_data *wd; /* First initialize the working data struct. */ - wd = vb2_get_working_data(); - memset(wd, 0, sizeof(struct vb2_working_data)); + wd = vboot_get_working_data(); + memset(wd, 0, sizeof(struct vboot_working_data)); /* * vboot prefers 16-byte alignment. This takes away 16 bytes * from the VBOOT2_WORK region, but the vboot devs said that's okay. */ wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - wd->buffer_size = vb2_working_data_size() - wd->buffer_offset; + wd->buffer_size = vboot_working_data_size() - wd->buffer_offset; /* Initialize the vb2_context. */ memset(ctx, 0, sizeof(*ctx)); - ctx->workbuf = (void *)vb2_get_shared_data(); + ctx->workbuf = (void *)vboot_get_shared_data(); ctx->workbuf_size = wd->buffer_size; } -void vb2_finalize_work_context(struct vb2_context *ctx) +void vboot_finalize_work_context(struct vb2_context *ctx) { /* - * Shrink buffer_size so that vb2_migrate_cbmem knows how much - * of vb2_working_data needs to be copied into CBMEM (if applicable), - * and so that downstream users know how much of the workbuf is - * currently used. + * Shrink buffer_size so that vboot_migrate_cbmem knows how + * much of vboot_working_data needs to be copied into CBMEM + * (if applicable), and so that downstream users know how much + * of the workbuf is currently used. */ - vb2_get_working_data()->buffer_size = ctx->workbuf_used; + vboot_get_working_data()->buffer_size = ctx->workbuf_used; } -struct vb2_shared_data *vb2_get_shared_data(void) +struct vb2_shared_data *vboot_get_shared_data(void) { - struct vb2_working_data *wd = vb2_get_working_data(); + struct vboot_working_data *wd = vboot_get_working_data(); return (void *)((uintptr_t)wd + wd->buffer_offset); } -int vb2_get_selected_region(struct region *region) +int vboot_get_selected_region(struct region *region) { const struct selected_region *reg = - &vb2_get_working_data()->selected_region; + &vboot_get_working_data()->selected_region; if (reg == NULL) return -1; @@ -127,9 +127,10 @@ return 0; } -void vb2_set_selected_region(const struct region *region) +void vboot_set_selected_region(const struct region *region) { - struct selected_region *reg = &vb2_get_working_data()->selected_region; + struct selected_region *reg = + &vboot_get_working_data()->selected_region; assert(reg != NULL); @@ -137,9 +138,10 @@ reg->size = region_sz(region); } -int vb2_is_slot_selected(void) +int vboot_is_slot_selected(void) { - struct selected_region *reg = &vb2_get_working_data()->selected_region; + struct selected_region *reg = + &vboot_get_working_data()->selected_region; assert(reg != NULL); @@ -151,29 +153,29 @@ * For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot * verification occurs before CBMEM is brought online, using pre-RAM. * In order to make vboot data structures available downstream, copy - * vb2_working_data from SRAM/CAR into CBMEM on platforms where this + * vboot_working_data from SRAM/CAR into CBMEM on platforms where this * memory later becomes unavailable. */ -static void vb2_migrate_cbmem(int unused) +static void vboot_migrate_cbmem(int unused) { - const struct vb2_working_data *wd_preram = - (struct vb2_working_data *)_vboot2_work; + const struct vboot_working_data *wd_preram = + (struct vboot_working_data *)_vboot2_work; size_t cbmem_size = wd_preram->buffer_offset + wd_preram->buffer_size; - struct vb2_working_data *wd_cbmem = + struct vboot_working_data *wd_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); printk(BIOS_DEBUG, - "VBOOT: copying vb2_working_data (%zu bytes) to CBMEM...\n", + "VBOOT: copying vboot_working_data (%zu bytes) to CBMEM...\n", cbmem_size); memcpy(wd_cbmem, wd_preram, cbmem_size); assert(wd_cbmem != NULL); } -ROMSTAGE_CBMEM_INIT_HOOK(vb2_migrate_cbmem) +ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) #elif CONFIG(VBOOT_STARTS_IN_ROMSTAGE) -static void vb2_setup_cbmem(int unused) +static void vboot_setup_cbmem(int unused) { - struct vb2_working_data *wd_cbmem = - cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb2_working_data_size()); + struct vboot_working_data *wd_cbmem = + cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vboot_working_data_size()); assert(wd_cbmem != NULL); } -ROMSTAGE_CBMEM_INIT_HOOK(vb2_setup_cbmem) +ROMSTAGE_CBMEM_INIT_HOOK(vboot_setup_cbmem) #endif diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index f1dff61..24e349d 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -21,18 +21,32 @@ struct vb2_context; struct vb2_shared_data; -void vboot_fill_handoff(void); - -void vb2_init_work_context(struct vb2_context *ctx); -void vb2_finalize_work_context(struct vb2_context *ctx); -struct vb2_shared_data *vb2_get_shared_data(void); +/* + * Source: security/vboot/common.c + */ +void vboot_init_work_context(struct vb2_context *ctx); +void vboot_finalize_work_context(struct vb2_context *ctx); +struct vb2_shared_data *vboot_get_shared_data(void); /* Returns 0 on success. < 0 on failure. */ -int vb2_get_selected_region(struct region *region); -void vb2_set_selected_region(const struct region *region); -int vb2_is_slot_selected(void); -int vb2_logic_executed(void); +int vboot_get_selected_region(struct region *region); -void vb2_save_recovery_reason_vbnv(void); +void vboot_set_selected_region(const struct region *region); +int vboot_is_slot_selected(void); + +/* + * Source: security/vboot/vboot_handoff.c + */ +void vboot_fill_handoff(void); + +/* + * Source: security/vboot/vboot_loader.c + */ +int vboot_logic_executed(void); + +/* + * Source: security/vboot/bootmode.c + */ +void vboot_save_recovery_reason_vbnv(void); #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 2bb26a8..e64775e 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -141,7 +141,7 @@ struct vboot_handoff *vh; struct vb2_shared_data *sd; - sd = vb2_get_shared_data(); + sd = vboot_get_shared_data(); sd->workbuf_hash_offset = 0; sd->workbuf_hash_size = 0; diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index dd8c15c..e0facc1 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -63,7 +63,7 @@ static int vboot_executed CAR_GLOBAL; -int vb2_logic_executed(void) +int vboot_logic_executed(void) { /* If we are in a stage that would load the verstage or execute the vboot logic directly, we store the answer in a global. */ @@ -91,7 +91,7 @@ /* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */ verstage_main(); car_set_var(vboot_executed, 1); - vb2_save_recovery_reason_vbnv(); + vboot_save_recovery_reason_vbnv(); } else if (verstage_should_load()) { struct cbfsf file; struct prog verstage = @@ -138,10 +138,10 @@ struct region selected_region; /* Don't honor vboot results until the vboot logic has run. */ - if (!vb2_logic_executed()) + if (!vboot_logic_executed()) return -1; - if (vb2_get_selected_region(&selected_region)) + if (vboot_get_selected_region(&selected_region)) return -1; props->offset = region_offset(&selected_region); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index d5bfa89..0b5763b 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -297,7 +297,7 @@ timestamp_add_now(TS_START_VBOOT); /* Set up context and work buffer */ - vb2_init_work_context(&ctx); + vboot_init_work_context(&ctx); /* Initialize and read nvdata from non-volatile storage. */ vbnv_init(ctx.nvdata); @@ -437,7 +437,7 @@ } printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B'); - vb2_set_selected_region(region_device_region(&fw_main)); - vb2_finalize_work_context(&ctx); + vboot_set_selected_region(region_device_region(&fw_main)); + vboot_finalize_work_context(&ctx); timestamp_add_now(TS_END_VBOOT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d9154fd2d5df25ee254bd5ce4a173afaa6588be Gerrit-Change-Number: 31886 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: inteltool: add 300 Series and C240 Series Northbridge (Coffeelake)
by Thomas Heijligen (Code Review) 15 Mar '19

15 Mar '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31500 Change subject: inteltool: add 300 Series and C240 Series Northbridge (Coffeelake) ...................................................................... inteltool: add 300 Series and C240 Series Northbridge (Coffeelake) Values from Intel doc 337347 rev4 Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31500/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 93a7ffe..37b3f2a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -250,6 +250,16 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q370, "Q370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B360, "B360" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C246, "C246" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C242, "C242" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM370, "QM370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM370, "HM370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM246, "CM246" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE, "C8 Mobile"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP, "C8 Desktop"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87, "Z87"}, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fb64811..6cf15fc 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -165,6 +165,18 @@ #define PCI_DEVICE_ID_INTEL_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_CM238 0xa154 + +#define PCI_DEVICE_ID_INTEL_H310 0xa303 +#define PCI_DEVICE_ID_INTEL_H370 0xa304 +#define PCI_DEVICE_ID_INTEL_Z390 0xa305 +#define PCI_DEVICE_ID_INTEL_Q370 0xa306 +#define PCI_DEVICE_ID_INTEL_B360 0xa308 +#define PCI_DEVICE_ID_INTEL_C246 0xa309 +#define PCI_DEVICE_ID_INTEL_C242 0xa30a +#define PCI_DEVICE_ID_INTEL_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_HM370 0xa30d +#define PCI_DEVICE_ID_INTEL_CM246 0xa30e + #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 -- To view, visit https://review.coreboot.org/c/coreboot/+/31500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Gerrit-Change-Number: 31500 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/amdfwtool: Allow 0-length blobs
by Marshall Dawson (Code Review) 15 Mar '19

15 Mar '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31891 Change subject: util/amdfwtool: Allow 0-length blobs ...................................................................... util/amdfwtool: Allow 0-length blobs A side effect of the change 8e0dca05 "util/amdfwtool: Add generic image copy function" was to treat a read operation of zero bytes as a failure. Some implementations exist that use zero length files as a means of removing functionality. This causes amdfwtool to exit with an error. Put the zero length capability back in, and generate the requested table entry with a length field of 0x0. Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31891/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 376887c..4a13b29 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -424,7 +424,7 @@ bytes = copy_blob(BUFF_CURRENT(*ctx), fw_table[i].filename, BUFF_ROOM(*ctx)); - if (bytes <= 0) { + if (bytes < 0) { free(ctx->rom); exit(1); } @@ -455,7 +455,7 @@ } else if (fw_table[i].filename != NULL) { bytes = copy_blob(BUFF_CURRENT(*ctx), fw_table[i].filename, BUFF_ROOM(*ctx)); - if (bytes <= 0) { + if (bytes < 0) { free(ctx->rom); exit(1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df Gerrit-Change-Number: 31891 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>'
by HAOUAS Elyes (Code Review) 15 Mar '19

15 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31861 Change subject: mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>' ...................................................................... mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>' Change-Id: I380ffe1348731b8c84855047e057365bec94a08c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31861/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index 01da624..060a35c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -14,7 +14,6 @@ */ #include <console/console.h> -#include <lib.h> #include <hwilib.h> #include <device/i2c_simple.h> #include <variant/ptn3460.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I380ffe1348731b8c84855047e057365bec94a08c Gerrit-Change-Number: 31861 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
by John Zhao (Code Review) 15 Mar '19

15 Mar '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31889 Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ...................................................................... vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake Update FSP header files for Cannonlake platform Change-Id: I7f1a1f61c32510062a440c14a897e95bed7a9718 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h 4 files changed, 267 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31889/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h index feb2022..e03408d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved. +Copyright (c) 2019, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index a625f00..770390d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved. +Copyright (c) 2019, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -182,15 +182,9 @@ **/ UINT8 ProbelessTrace; -/** Offset 0x00A3 - GDXC IOT SIZE - Size of IOT and MOT is in 8 MB chunks +/** Offset 0x00A3 **/ - UINT8 GdxcIotSize; - -/** Offset 0x00A4 - GDXC MOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcMotSize; + UINT8 UnusedUpdSpace0[2]; /** Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller. @@ -250,7 +244,9 @@ /** Offset 0x00B8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, + 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, + 0xFD:56MB, 0xFE:60MB **/ UINT8 IgdDvmt50PreAlloc; @@ -276,14 +272,14 @@ /** Offset 0x00BC - SA GV System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled + 2=FixedMid, 3=FixedHigh, and 4=Enabled. + 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled **/ UINT8 SaGv; /** Offset 0x00BD **/ - UINT8 UnusedUpdSpace0; + UINT8 UnusedUpdSpace1; /** Offset 0x00BE - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, @@ -331,9 +327,16 @@ **/ UINT8 ScramblerSupport; -/** Offset 0x00C8 +/** Offset 0x00C8 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize; 1: Skip + $EN_DIS **/ - UINT8 UnusedUpdSpace1[16]; + UINT8 SkipMpInit; + +/** Offset 0x00C9 +**/ + UINT8 UnusedUpdSpace2[15]; /** Offset 0x00D8 - SPD Profile Selected Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP @@ -479,7 +482,9 @@ UINT8 CpuTraceHubMemReg1Size; /** Offset 0x00F6 - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command; 0: Disable; 1: Enable. + Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message + to disable peci reset on C10 exit. The default value is 0: Disable for CNL, + and 1: Enable for all other CPU's $EN_DIS **/ UINT8 PeciC10Reset; @@ -492,7 +497,7 @@ /** Offset 0x00F8 **/ - UINT8 UnusedUpdSpace2[4]; + UINT8 UnusedUpdSpace3[4]; /** Offset 0x00FC - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -514,7 +519,7 @@ /** Offset 0x00FF **/ - UINT8 UnusedUpdSpace3; + UINT8 UnusedUpdSpace4; /** Offset 0x0100 - HECI1 BAR address BAR address of HECI1 @@ -685,7 +690,7 @@ /** Offset 0x0125 **/ - UINT8 UnusedUpdSpace4[3]; + UINT8 UnusedUpdSpace5[3]; /** Offset 0x0128 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -724,7 +729,7 @@ /** Offset 0x0146 **/ - UINT8 UnusedUpdSpace5[2]; + UINT8 UnusedUpdSpace6[2]; /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control Range: 0-15, 12 is default for each bundle, must be specified based upon platform design @@ -949,7 +954,7 @@ /** Offset 0x0205 - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-83 + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 **/ UINT8 CoreMaxOcRatio; @@ -959,13 +964,15 @@ **/ UINT8 CoreVoltageMode; -/** Offset 0x0207 +/** Offset 0x0207 - Program Cache Attributes + Program Cache Attributes; 0: Program; 1: Disable Program. + $EN_DIS **/ - UINT8 UnusedUpdSpace6; + UINT8 DisableMtrrProgram; /** Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-83 + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 **/ UINT8 RingMaxOcRatio; @@ -1114,9 +1121,13 @@ **/ UINT8 Txt; -/** Offset 0x0227 +/** Offset 0x0227 - DpSscMarginEnable TYPE:{Combo + Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down + spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used + on systems that exceeds allowed SSC modulation range as defined in VESA's spec + $EN_DIS **/ - UINT8 UnusedUpdSpace8; + UINT8 DpSscMarginEnable; /** Offset 0x0228 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 @@ -1182,7 +1193,12 @@ Reserved for Security Pre-Mem $EN_DIS **/ - UINT8 ReservedSecurityPreMem[15]; + UINT8 ReservedSecurityPreMem[3]; + +/** Offset 0x0264 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[3]; /** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1861,12 +1877,12 @@ UINT8 RhActProbability; /** Offset 0x04C1 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) + Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindX; /** Offset 0x04C2 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) + Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindY; @@ -1881,52 +1897,52 @@ UINT8 RaplLim1WindY; /** Offset 0x04C5 - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (224= Def) + range[0;2^14-1]= [2047.875;0]in W, (222= Def) **/ UINT16 RaplLim2Pwr; /** Offset 0x04C7 - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (224= Def) + range[0;2^14-1]= [2047.875;0]in W, (0= Def) **/ UINT16 RaplLim1Pwr; /** Offset 0x04C9 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm0; /** Offset 0x04CA - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm1; /** Offset 0x04CB - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm0; /** Offset 0x04CC - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm1; /** Offset 0x04CD - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm0; /** Offset 0x04CE - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm1; /** Offset 0x04CF - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm0; /** Offset 0x04D0 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm1; @@ -2072,7 +2088,7 @@ /** Offset 0x04ED - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Dfault is 0x30 + Default is 0x30 **/ UINT8 ThrtCkeMinTmr; @@ -2279,18 +2295,22 @@ **/ UINT8 EnBER; -/** Offset 0x050F - Dual Dimm Per-Channel Board Type - Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used - to limit maximum frequency for some SKUs. - 0:1DPC, 1:2DPC -**/ - UINT8 DualDimmPerChannelBoardType; - -/** Offset 0x0510 - CFL Reserved - Reserved FspmConfig CFL +/** Offset 0x050F - PEG IMR support + This option configures the IMR support for PEG.(def=Disable) $EN_DIS **/ - UINT8 ReservedFspmUpdCfl[3]; + UINT8 PegImrEnable; + +/** Offset 0x0510 - PEG IMR size + The size of IMR to be allocated for PEG EndPoint device.PegImrSize can vary from + 0 to 1024 MB in steps of 2 power N where N = 0 to 10 +**/ + UINT16 PegImrSize; + +/** Offset 0x0512 - PEG Root Port Selection + The Root Port for which the IMR to be allocated +**/ + UINT8 PegImrRpSelection; /** Offset 0x0513 - Memory Test on Warm Boot Run Base Memory Test on Warm Boot @@ -2298,9 +2318,27 @@ **/ UINT8 MemTestOnWarmBoot; -/** Offset 0x0514 +/** Offset 0x0514 - Throttler CKEMin Timer - LPDDR + Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + + BYTE_LENGTH (4). Default is 0x40 **/ - UINT8 ReservedFspmUpd[11]; + UINT8 ThrtCkeMinTmrLpddr; + +/** Offset 0x0515 - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x0516 - MRC Force training on Warm + Enables/Disable the MRC training on warm boot + $EN_DIS +**/ + UINT8 MrcTrainOnWarm; + +/** Offset 0x0517 +**/ + UINT8 ReservedFspmUpd[8]; } FSP_M_CONFIG; /** Fsp M Test Configuration @@ -2525,7 +2563,7 @@ /** Offset 0x0579 **/ - UINT8 UnusedUpdSpace9; + UINT8 UnusedUpdSpace8; /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default @@ -2560,11 +2598,24 @@ **/ UINT8 BdatTestType; -/** Offset 0x0584 - SaPreMemTestRsvd +/** Offset 0x0584 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0585 - Delta T12 Power Cycle Delay required in ms + Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate + T12 Delay to max 500ms + 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay +**/ + UINT16 DeltaT12PowerCycleDelayPreMem; + +/** Offset 0x0587 - SaPreMemTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ - UINT8 SaPreMemTestRsvd[12]; + UINT8 SaPreMemTestRsvd[9]; /** Offset 0x0590 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2608,14 +2659,13 @@ UINT8 SmbusSpdWriteDisable; /** Offset 0x059B - ChipsetInit HECI message - Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message. - If disabled, it prevents from sending ChipsetInit HECI message. + DEPRECATED $EN_DIS **/ UINT8 ChipsetInitMessage; /** Offset 0x059C - Bypass ChipsetInit sync reset. - 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message. + DEPRECATED $EN_DIS **/ UINT8 BypassPhySyncReset; @@ -2800,7 +2850,7 @@ /** Offset 0x051F **/ - UINT8 UnusedUpdSpace8; + UINT8 UnusedUpdSpace7; /** Offset 0x0520 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 3ead9b1..c9024eb 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved. +Copyright (c) 2019, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -101,7 +101,8 @@ UINT32 GraphicsConfigPtr; /** Offset 0x002C - Enable Device 4 - Enable/disable Device 4 + The Device 4 default value is 1: Enable for WHL, and 0: disable for + all other CPU's $EN_DIS **/ UINT8 Device4Enable; @@ -451,11 +452,27 @@ **/ UINT8 PmcDbgMsgEn; -/** Offset 0x0120 - PchPostMemRsvd +/** Offset 0x0120 - Pointer of ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x0124 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x0128 - PchDmiCwbEnable + Central Write Buffer feature configurable and disabled by default + $EN_DIS +**/ + UINT8 PchDmiCwbEnable; + +/** Offset 0x0129 - PchPostMemRsvd Reserved for PCH Post-Mem $EN_DIS **/ - UINT8 PchPostMemRsvd[37]; + UINT8 PchPostMemRsvd[28]; /** Offset 0x0145 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller. @@ -615,8 +632,8 @@ **/ UINT8 AmtKvmEnabled; -/** Offset 0x0161 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx +/** Offset 0x0161 - MEBX execution + Enable/Disable. 0: Disable, 1: enable, Force MEBX execution $EN_DIS **/ UINT8 ForcMebxSyncUp; @@ -667,7 +684,8 @@ UINT8 PmcModPhySusPgEnable; /** Offset 0x01FC - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable + Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping + CPU and 1 for all other CPUs. 0: Disable, 1: Enable $EN_DIS **/ UINT8 SlpS0WithGbeSupport; @@ -717,8 +735,8 @@ UINT8 PavpEnable; /** Offset 0x0217 - CdClock Frequency selection - 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz - 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz + 0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz + 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz **/ UINT8 CdClock; @@ -742,12 +760,12 @@ 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ - UINT8 X2ApicOptOut; + UINT8 X2ApicOptOutDeprecated; /** Offset 0x021C - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine **/ - UINT32 VtdBaseAddress[3]; + UINT32 VtdBaseAddressDeprecated[3]; /** Offset 0x0228 - Enable or disable eDP device 0=Disable, 1(Default)=Enable @@ -811,8 +829,7 @@ UINT8 SkipS3CdClockInit; /** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms + DEPRECATED 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay **/ UINT16 DeltaT12PowerCycleDelay; @@ -865,8 +882,7 @@ UINT8 ImonSlope[5]; /** Offset 0x0287 - Imon offset correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto + DEPRECATED **/ UINT8 ImonOffset[5]; @@ -1026,12 +1042,11 @@ **/ UINT8 UnusedUpdSpace9[6]; -/** Offset 0x030C - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip +/** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization + @deprecated SkipMpInit has been moved to FspmUpd $EN_DIS **/ - UINT8 SkipMpInit; + UINT8 SkipMpInitDeprecated; /** Offset 0x030D - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: @@ -1123,11 +1138,33 @@ **/ UINT8 RampDown; -/** Offset 0x032B - ReservedCpuPostMemProduction +/** Offset 0x032B - CpuMpPpi + Pointer for CpuMpPpi +**/ + UINT32 CpuMpPpi; + +/** Offset 0x032F - CpuMpHob + Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. +**/ + UINT32 CpuMpHob; + +/** Offset 0x0333 - Enable or Disable processor debug features + Enable or Disable processor debug features; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x0334 - Imon offset 1 correction + PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. + Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto +**/ + UINT16 ImonOffset1[5]; + +/** Offset 0x033E - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS **/ - UINT8 ReservedCpuPostMemProduction[27]; + UINT8 ReservedCpuPostMemProduction[8]; /** Offset 0x0346 - Enable DMI ASPM Deprecated. @@ -1209,9 +1246,15 @@ **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x036E +/** Offset 0x036E - USB LFPS Filter selection + For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, + 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. **/ - UINT8 UnusedUpdSpace11[15]; + UINT8 PchUsbHsioFilterSel[10]; + +/** Offset 0x0378 +**/ + UINT8 UnusedUpdSpace11[5]; /** Offset 0x037D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. @@ -1418,9 +1461,21 @@ **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x04E6 +/** Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters + Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for + controlling the input offset **/ - UINT8 UnusedUpdSpace14[24]; + UINT8 PchUsbHsioRxTuningParameters[10]; + +/** Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable + Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, + 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable +**/ + UINT8 PchUsbHsioRxTuningEnable[10]; + +/** Offset 0x04FA +**/ + UINT8 UnusedUpdSpace14[4]; /** Offset 0x04FE - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: @@ -1520,9 +1575,17 @@ **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0667 +/** Offset 0x0667 - Teton Glacier Support + Deprecated + $EN_DIS **/ - UINT8 UnusedUpdSpace17[2]; + UINT8 TetonGlacierSupport; + +/** Offset 0x0668 - Teton Glacier Cycle Router + Specify to which cycle router Teton Glacier is connected, it is valid only when + Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system +**/ + UINT8 TetonGlacierCR; /** Offset 0x0669 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. @@ -1546,9 +1609,12 @@ **/ UINT8 PcieRpImrSelection; -/** Offset 0x066F +/** Offset 0x066F - Teton Glacier Detection and Configuration Mode + Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Static + Configuration 2: Dynamic Configuration. Default is 0: Disabled + 0: Disabled, 1: Static Configuration, 2: Dynamic Configuration **/ - UINT8 UnusedUpdSpace18; + UINT8 TetonGlacierMode; /** Offset 0x0670 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. @@ -1635,9 +1701,15 @@ **/ UINT8 PchEnableDbcObs; -/** Offset 0x067D +/** Offset 0x067D - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. 0: Disable, 1: Enable + $EN_DIS **/ - UINT8 UnusedUpdSpace19[3]; + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x067E +**/ + UINT8 UnusedUpdSpace17[2]; /** Offset 0x0680 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. @@ -1671,7 +1743,7 @@ /** Offset 0x0685 **/ - UINT8 UnusedUpdSpace20; + UINT8 UnusedUpdSpace18; /** Offset 0x0686 - PCH Pm Disable Native Power Button Power button native mode disable. @@ -1711,7 +1783,7 @@ /** Offset 0x068C **/ - UINT8 UnusedUpdSpace21; + UINT8 UnusedUpdSpace19; /** Offset 0x068D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -1900,7 +1972,7 @@ /** Offset 0x0700 **/ - UINT8 UnusedUpdSpace22; + UINT8 UnusedUpdSpace20; /** Offset 0x0701 - PcdSerialIoUart0PinMuxing Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled. @@ -1910,7 +1982,7 @@ /** Offset 0x0702 **/ - UINT8 UnusedUpdSpace23[1]; + UINT8 UnusedUpdSpace21[1]; /** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS linesh. @@ -2183,7 +2255,7 @@ /** Offset 0x0753 **/ - UINT8 UnusedUpdSpace24; + UINT8 UnusedUpdSpace22; /** Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -2254,11 +2326,13 @@ **/ UINT8 SiCsmFlag; -/** Offset 0x07A1 +/** Offset 0x07A1 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. **/ UINT32 SiSsidTablePtr; -/** Offset 0x07A5 +/** Offset 0x07A5 - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. **/ UINT16 SiNumberOfSsidTableEntry; @@ -2362,7 +2436,7 @@ UINT8 PmSupport; /** Offset 0x07BC - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp + Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; @@ -2371,7 +2445,7 @@ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ - UINT8 VtdDisable; + UINT8 VtdDisableDeprecated; /** Offset 0x07BE - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -2400,31 +2474,28 @@ UINT8 SaPostMemTestRsvd[11]; /** Offset 0x07CB - 1-Core Ratio Limit - 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal - to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, - 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83 + 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core + Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, + 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, + 8-Core Ratio Limit. Range is 0 to 255 **/ UINT8 OneCoreRatioLimit; /** Offset 0x07CC - 2-Core Ratio Limit - 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 + 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core + Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 TwoCoreRatioLimit; /** Offset 0x07CD - 3-Core Ratio Limit - 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 + 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core + Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 ThreeCoreRatioLimit; /** Offset 0x07CE - 4-Core Ratio Limit - 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 + 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core + Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 FourCoreRatioLimit; @@ -2442,8 +2513,9 @@ UINT8 HdcControl; /** Offset 0x07D1 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) - 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 + Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. + Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 + , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; @@ -2511,7 +2583,8 @@ UINT8 NumberOfEntries; /** Offset 0x07DC - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 + Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 + to 128, 0 = AUTO **/ UINT8 Custom1PowerLimit1Time; @@ -2526,7 +2599,8 @@ UINT8 Custom1ConfigTdpControl; /** Offset 0x07DF - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 + Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 + to 128, 0 = AUTO **/ UINT8 Custom2PowerLimit1Time; @@ -2541,7 +2615,8 @@ UINT8 Custom2ConfigTdpControl; /** Offset 0x07E2 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 + Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 + to 128, 0 = AUTO **/ UINT8 Custom3PowerLimit1Time; @@ -2574,8 +2649,8 @@ UINT8 PsysPowerLimit1; /** Offset 0x07E8 - PL1 timewindow - PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 - , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 + PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) + 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; @@ -2610,8 +2685,8 @@ **/ UINT8 MachineCheckEnable; -/** Offset 0x07EE - Enable or Disable processor debug features - Enable or Disable processor debug features; 0: Disable; 1: Enable. +/** Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features + @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceEnable; @@ -2739,13 +2814,15 @@ UINT8 C1e; /** Offset 0x080D - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable + Enable or Disable Package Cstate Demotion. Policy will be ignored for CNL-U. 0: + Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; /** Offset 0x080E - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable + Enable or Disable Package Cstate UnDemotion. Policy will be ignored for CNL-U. Disable; + 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; @@ -2811,8 +2888,8 @@ UINT8 CstateLatencyControl5TimeUnit; /** Offset 0x0819 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. + Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: + No change. **/ UINT8 PpmIrmSetting; @@ -2978,40 +3055,36 @@ **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0899 - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT; 0: Disable; 1: Enable. +/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; /** Offset 0x089A - 5-Core Ratio Limit - 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 + 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core + Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 FiveCoreRatioLimit; /** Offset 0x089B - 6-Core Ratio Limit - 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 + 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core + Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SixCoreRatioLimit; /** Offset 0x089C - 7-Core Ratio Limit - 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 + 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core + Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SevenCoreRatioLimit; /** Offset 0x089D - 8-Core Ratio Limit - 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 + 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core + Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 EightCoreRatioLimit; @@ -3059,23 +3132,11 @@ **/ UINT8 MaxRingRatioLimit; -/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion - Enable or Disable C3 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateAutoDemotion; - -/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion - Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateUnDemotion; - -/** Offset 0x08A7 - ReservedCpuPostMemTest +/** Offset 0x08A5 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[19]; + UINT8 ReservedCpuPostMemTest[21]; /** Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -3225,7 +3286,7 @@ /** Offset 0x0A61 **/ - UINT8 UnusedUpdSpace25[17]; + UINT8 UnusedUpdSpace23[17]; /** Offset 0x0A72 - Skip POSTBOOT SAI Deprecated diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h index 90fae70..bef3ee5 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved. +Copyright (c) 2019, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -- To view, visit https://review.coreboot.org/c/coreboot/+/31889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f1a1f61c32510062a440c14a897e95bed7a9718 Gerrit-Change-Number: 31889 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/pci: Rewrite PCI MMCONF with symbol reference
by Kyösti Mälkki (Code Review) 15 Mar '19

15 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Rewrite PCI MMCONF with symbol reference ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h File src/include/device/pci_mmio_cfg.h: https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@29 PS4, Line 29: }; > Doesn't the same apply to `arch/mmio.h`? > > Just wondering if that's not the better place. And we could > use readxx()/writexx() below. I guess I would be looking at ton of different callers of readX()/writeX() should I change those signatures away from void *. > In any case, it doesn't seem very obvious why we have that > union. So I'd expect a comment here with the same reasoning > as in the commit message. Far from obvious to me as well, I'll replicate commit message in code. > Wait... do we need the union? I would assume now, that a > struct, e.g. `struct pci8 { uint8_t reg[4096]; };` would > produce the same result. I wouldn't have a preference, > though. You would cast thru u16* or u32*, respectively. https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@36 PS4, Line 36: volatile union pci_bank *cfg = (void *)&pci_mmconf[dev]; Adding u8* pci_mmconf is very much related. I don't know if I can split it. At least I don't want to split it, as the current form seems to create picture-perfect assembly code on x86. -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 15 Mar 2019 12:34:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Angel Pons (Code Review) 15 Mar '19

15 Mar '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 48: I just got one of these. Will try a few things at some point. -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 48 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Mar 2019 12:24:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
by Krishna P Bhat D (Code Review) 15 Mar '19

15 Mar '19

Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 ) Change subject: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/31902/2/src/soc/intel/cannonlake/pmutil.c File src/soc/intel/cannonlake/pmutil.c: https://review.coreboot.org/#/c/31902/2/src/soc/intel/cannonlake/pmutil.c@1… PS2, Line 154: if(suspwrflr_val & (SUS_PWR_FLR >> 16)) { > space required before the open parenthesis '(' Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Gerrit-Change-Number: 31902 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Mar 2019 12:19:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2019