Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 )
Change subject: device/pci: Rewrite PCI MMCONF with symbol reference
......................................................................
Patch Set 4:
(1 comment)
> Patch Set 4:
>
> (2 comments)
>
> Is that C standard/spec or compiler specific?
I would say it's the standard, implied by the aliasing rules in general.
https://review.coreboot.org/#/c/31752/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31752/4//COMMIT_MSG@20
PS4, Line 20:
> Is there any effect on the boot time?
We are just talking about some 10 assembly instructions that got repeated after every PCI config writes, and we avoid that now. MMIO operation on the bus is a different magnitude of delay, you might just see a millisecond for the entire ramstage that we save.
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31906 )
Change subject: [DoNotMerge]mb/google/sarien: Enable SPI console
......................................................................
Patch Set 1:
This change is ready for review.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/14921 )
Change subject: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/14921/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/14921/6//COMMIT_MSG@9
PS6, Line 9: New compilers
> Do you know since when, and if it is valid for GCC and Clang?
Sorry, I wrote this 2+ years ago, I have no idea. This just doesn't work on arm64 (I think it never did), and with this patch it does.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 )
Change subject: device/pci: Rewrite PCI MMCONF with symbol reference
......................................................................
Patch Set 4:
(2 comments)
Is that C standard/spec or compiler specific?
https://review.coreboot.org/#/c/31752/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31752/4//COMMIT_MSG@18
PS4, Line 18: avoid
avoids
https://review.coreboot.org/#/c/31752/4//COMMIT_MSG@20
PS4, Line 20:
Is there any effect on the boot time?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/14921 )
Change subject: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/14921/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/14921/6//COMMIT_MSG@9
PS6, Line 9: New compilers
Do you know since when, and if it is valid for GCC and Clang?
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Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31584 )
Change subject: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table"
......................................................................
Patch Set 4:
(2 comments)
> Patch Set 2:
>
> (2 comments)
https://review.coreboot.org/#/c/31584/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31584/2//COMMIT_MSG@9
PS2, Line 9: This reverts commit 5620b105461cc18cf1439f02013153237f372b4b.
> Please add a blank line below.
Done
https://review.coreboot.org/#/c/31584/2//COMMIT_MSG@11
PS2, Line 11:
> One space.
Done
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Hello Patrick Rudolph, AndreX Andraos, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31584
to look at the new patch set (#4).
Change subject: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table"
......................................................................
Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table"
This reverts commit 5620b105461cc18cf1439f02013153237f372b4b.
This patch is only to make suspend_stress_test work until the proper
fix for keyboard wake is found and should never be merged.
Change-Id: I090e69e0a20a1cc209c82bae914e1640f7fce90e
---
M src/mainboard/google/sarien/dsdt.asl
D src/soc/intel/cannonlake/acpi/lpit.asl
2 files changed, 0 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31584/4
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