coreboot-gerrit March 2019

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Change in ...coreboot[master]: x86/smbios: Untangle system and board tables
by Lijian Zhao (Code Review) 16 Mar '19

16 Mar '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29477 ) Change subject: x86/smbios: Untangle system and board tables ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Gerrit-Change-Number: 29477 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 15 Mar 2019 17:18:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: x86/smbios: Untangle system and board tables
by Richard Spiegel (Code Review) 16 Mar '19

16 Mar '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29477 ) Change subject: x86/smbios: Untangle system and board tables ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/29477/8/src/drivers/i2c/at24rf08c/Kconfig File src/drivers/i2c/at24rf08c/Kconfig: https://review.coreboot.org/#/c/29477/8/src/drivers/i2c/at24rf08c/Kconfig@1 PS8, Line 1: DRIVERS_I2C_AT24RF08C I don't see this new config being used. Separate commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/29477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Gerrit-Change-Number: 29477 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 15 Mar 2019 17:00:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci_ops: Have only default PCI bus ops available
by Aaron Durbin (Code Review) 16 Mar '19

16 Mar '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31753 ) Change subject: device/pci_ops: Have only default PCI bus ops available ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Gerrit-Change-Number: 31753 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 15 Mar 2019 15:59:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci: Rewrite PCI MMCONF with symbol reference
by Aaron Durbin (Code Review) 16 Mar '19

16 Mar '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Rewrite PCI MMCONF with symbol reference ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h File src/include/device/pci_mmio_cfg.h: https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@27 PS4, Line 27: 2 sizeof(uint16_t) https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@28 PS4, Line 28: 4 sizeof(uint32_t) https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@36 PS4, Line 36: dev I assume dev is encoded to have the 12 lower bits cleared? It's kinda subtle. Maybe add a comment or use an inline helper function to return the address and have a single comment there? https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@65 PS4, Line 65: > just divide by sizeof(uint16_t) and sizeof(uint32_t) below? -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 15 Mar 2019 15:44:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci: Rewrite PCI MMCONF with symbol reference
by Kyösti Mälkki (Code Review) 16 Mar '19

16 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Rewrite PCI MMCONF with symbol reference ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h File src/include/device/pci_mmio_cfg.h: https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@29 PS4, Line 29: }; > >> Doesn't the same apply to `arch/mmio.h`? […] You can cherry-pick testcases here CB:31811 I did not come up with a solution using writeX(). -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 15 Mar 2019 15:35:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco: Clear S0ix support bit at boot
by Duncan Laurie (Code Review) 16 Mar '19

16 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31903 Change subject: ec/google/wilco: Clear S0ix support bit at boot ...................................................................... ec/google/wilco: Clear S0ix support bit at boot To ensure the power button functions as expected in firmware ensure that the EC is not in "S0ix supported OS" mode and expecting the power button to be handled by the virtual button interface. BUG=b:128409889 TEST=Verify that the power button works at the developer screen when the system is rebooted from within Chrome OS. Also ensure that it works when external warm reset signal is asserted by H1. Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/Kconfig M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.h 3 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31903/1 diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index e905d5e..4202c1d 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -2,6 +2,7 @@ bool default n select EC_GOOGLE_COMMON_MEC + select EC_ACPI help Google Wilco Embedded Controller interface. diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index a9caaec..0858e1c 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <bootstate.h> #include <device/pnp.h> +#include <ec/acpi/ec.h> #include <pc80/keyboard.h> #include <stdint.h> #include <stdlib.h> @@ -55,6 +57,13 @@ if (!dev->enabled) return; + /* Disable S0ix support in EC RAM with ACPI EC interface */ + if (!acpi_is_wakeup_s3()) { + ec_set_ports(CONFIG_EC_BASE_ACPI_COMMAND, + CONFIG_EC_BASE_ACPI_DATA); + ec_write(EC_RAM_S0IX_SUPPORT, 0); + } + /* Print EC firmware information */ wilco_ec_print_all_info(); diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 53f6d0f..9c1685b 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -50,6 +50,11 @@ KB_BIOS_PROGRESS = 0xc2, }; +enum ec_ram_addr { + /* Indicate support for S0ix */ + EC_RAM_S0IX_SUPPORT = 0xb8, +}; + enum set_acpi_mode_cmd { ACPI_OFF = 0, ACPI_ON -- To view, visit https://review.coreboot.org/c/coreboot/+/31903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833 Gerrit-Change-Number: 31903 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: add ish firmware_variant field to _DSD
by Jett Rink (Code Review) 16 Mar '19

16 Mar '19

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31683 Change subject: mb/google/sarien: add ish firmware_variant field to _DSD ...................................................................... mb/google/sarien: add ish firmware_variant field to _DSD We want to publish "arcada_ish" as the fw variant name for ISH, so the kernel shim loader code can use it to construct the correct path in /lib/firmware/intel for the firmware load process. BRANCH=none BUG=b:122722008 TEST=Verify that shim loader CLs use new value when constructing firmware path Change-Id: I6299de82566a3bad8521f8158bb047d5c1ff0cf8 Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/arcada/devicetree.cb 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31683/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index a976d36..8919057 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -4,6 +4,7 @@ select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA select DRIVERS_SPI_ACPI select DRIVERS_PS2_KEYBOARD select DRIVERS_USB_ACPI diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 244ba7a..154053b 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -195,7 +195,12 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 13.0 on end # Integrated Sensor Hub + device pci 13.0 on # Integrated Sensor Hub + chip drivers/intel/ish + register "firmware_variant" = ""arcada_ish"" + device generic 0 on end + end + end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6299de82566a3bad8521f8158bb047d5c1ff0cf8 Gerrit-Change-Number: 31683 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: driver/intel/ish: add ish chip driver support
by Jett Rink (Code Review) 16 Mar '19

16 Mar '19

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31682 Change subject: driver/intel/ish: add ish chip driver support ...................................................................... driver/intel/ish: add ish chip driver support We want to be able to specify the firmware variant suffix in the devicetree.cb configuration for particular firmware builds. This driver allows us to specify the firmware_variant property in the device tree and have it populate a _DST table in the DDST ACPI table for the ISH device, thus making the suffix available to the kernel. BRANCH=none BUG=b:122722008 TEST=decompile DDST table and verify that new firmware-variant value is present. Also verfied that kernel can access this new field using the shim loader kernel CLs Change-Id: Id8be986185282521aee574027503eaf8968e1508 Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- A src/drivers/intel/ish/Kconfig A src/drivers/intel/ish/Makefile.inc A src/drivers/intel/ish/chip.h A src/drivers/intel/ish/ish.c M src/include/device/pci_ids.h 5 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31682/1 diff --git a/src/drivers/intel/ish/Kconfig b/src/drivers/intel/ish/Kconfig new file mode 100644 index 0000000..b4c92ef --- /dev/null +++ b/src/drivers/intel/ish/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_INTEL_ISH + bool "Support Intel ISH driver that publishes _DSD information" + depends on ARCH_X86 + help + When enabled, chip driver/intel/ish will publish information to the + SSDT _DSD table for the ISH device. \ No newline at end of file diff --git a/src/drivers/intel/ish/Makefile.inc b/src/drivers/intel/ish/Makefile.inc new file mode 100644 index 0000000..cab2b1d8 --- /dev/null +++ b/src/drivers/intel/ish/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_ISH) += ish.c diff --git a/src/drivers/intel/ish/chip.h b/src/drivers/intel/ish/chip.h new file mode 100644 index 0000000..426e6bf --- /dev/null +++ b/src/drivers/intel/ish/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> + +/* + * Intel Integrated Sensor Hub (ISH) + */ +struct drivers_intel_ish_config { + /* Firmware variant suffix used by kernel for loading */ + const char *firmware_variant; +}; diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c new file mode 100644 index 0000000..963eb05 --- /dev/null +++ b/src/drivers/intel/ish/ish.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" + +static void ish_fill_ssdt_generator(struct device *dev) +{ + struct drivers_intel_ish_config *config = dev->chip_info; + struct device *root = dev->bus->dev; + struct acpi_dp *dsd; + + if (!dev->enabled || !config || !config->firmware_variant) + return; + + acpigen_write_scope(acpi_device_scope(root)); + acpigen_write_device(acpi_device_name(root)); + + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_string(dsd, "firmware-variant", config->firmware_variant); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: Set firmware-variant: %s\n", + acpi_device_path(root), config->firmware_variant); +} + +static struct device_operations intel_ish_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_fill_ssdt_generator = ish_fill_ssdt_generator, +}; + +static void intel_ish_enable(struct device *dev) +{ + /* This dev is a generic device that is a child to the ISH PCI device */ + dev->ops = &intel_ish_ops; +} + +static struct pci_driver ish_intel_driver __pci_driver = { + .vendor = PCI_VENDOR_ID_INTEL, + /* .devices and .ops are during chip init if needed */ +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_ISHB, + 0 +}; + +static void ish_chip_init_update_pci_driver(void *unused) +{ + static struct device_operations pci_ish_device_ops; + + /* + * We know this chip driver is in use, so we need to enable the PCI + * driver to use the default pci ops with the addition of generic scan + * bus. We also make the PCI driver match the ISH PIDs. + * + * If this method is not called (i.e. the Intel ISH chip is not in use), + * then the PCI driver will not match anything on the system. + */ + + /* Use the default pci ops for ISH */ + memcpy(&pci_ish_device_ops, &default_pci_ops_dev, + sizeof(pci_ish_device_ops)); + /* Add generic bus scan */ + pci_ish_device_ops.scan_bus = &scan_generic_bus; + + /* Set new ops and enable PCI driver by setting device IDs */ + ish_intel_driver.ops = &pci_ish_device_ops; + ish_intel_driver.devices = pci_device_ids; +} + +struct chip_operations drivers_intel_ish_ops = { + CHIP_NAME("Intel ISH Chip") + .init = ish_chip_init_update_pci_driver, + .enable_dev = intel_ish_enable, +}; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 90b02cb..dc5e6a8 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2091,6 +2091,7 @@ #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 #define PCI_DEVICE_ID_INTEL_82437VX 0x7030 #define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_ISHB 0x9dfc /* Intel 82371FB (PIIX) */ #define PCI_DEVICE_ID_INTEL_82371FB_ISA 0x122e -- To view, visit https://review.coreboot.org/c/coreboot/+/31682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8be986185282521aee574027503eaf8968e1508 Gerrit-Change-Number: 31682 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/pci: Rewrite PCI MMCONF with symbol reference
by Nico Huber (Code Review) 15 Mar '19

15 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Rewrite PCI MMCONF with symbol reference ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h File src/include/device/pci_mmio_cfg.h: https://review.coreboot.org/#/c/31752/4/src/include/device/pci_mmio_cfg.h@29 PS4, Line 29: }; > > Doesn't the same apply to `arch/mmio.h`? […] >> Doesn't the same apply to `arch/mmio.h`? >> >> Just wondering if that's not the better place. And we could >> use readxx()/writexx() below. > > I guess I would be looking at ton of different callers of readX()/writeX() should I change those signatures away from void *. Would we have to change the signature? Below we have an interim (void *), too. I thought it's the dereference that matters? -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 15 Mar 2019 14:34:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
by Furquan Shaikh (Code Review) 15 Mar '19

15 Mar '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 ) Change subject: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c File src/soc/intel/cannonlake/pmutil.c: https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c@1… PS3, Line 146: pmc_clear_suspwrflr I am wondering if this should be more than just suspwrflr clear i.e. pmc_clear_pmcon_sts and then clear: GBL_RST_STS SUS_PWR_FLR PWR_FLR Also, why not just move this function to pmc.c. That way you don't have to expose it in the header file. https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c@1… PS3, Line 150: pmc_mmio_regs() + GEN_PMCON_A + 2 Just read the whole thing and update the right bits (preserving the ones that don't need to be reset) -- To view, visit https://review.coreboot.org/c/coreboot/+/31902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Gerrit-Change-Number: 31902 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Mar 2019 14:11:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2019