coreboot-gerrit March 2019

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Change in ...coreboot[master]: util/autoport: fix default headers
by Angel Pons (Code Review) 17 Mar '19

17 Mar '19

Hello Kyösti Mälkki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31927 to look at the new patch set (#2). Change subject: util/autoport: fix default headers ...................................................................... util/autoport: fix default headers Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31927/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Gerrit-Change-Number: 31927 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: util/autoport: fix default headers
by Kyösti Mälkki (Code Review) 17 Mar '19

17 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31927 ) Change subject: util/autoport: fix default headers ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31927/1/util/autoport/bd82x6x.go File util/autoport/bd82x6x.go: https://review.coreboot.org/#/c/31927/1/util/autoport/bd82x6x.go@313 PS1, Line 313: #include <device/pci_ops.h> device/mmio.h for read/writeX(), those were relocated away from arch/io.h -- To view, visit https://review.coreboot.org/c/coreboot/+/31927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Gerrit-Change-Number: 31927 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Mar 2019 15:23:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci_ops: Have only default PCI bus ops available
by Kyösti Mälkki (Code Review) 17 Mar '19

17 Mar '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31753 ) Change subject: device/pci_ops: Have only default PCI bus ops available ...................................................................... device/pci_ops: Have only default PCI bus ops available In the current state of the tree we do not utilise the mechanism of having per-device overrides for PCI bus ops. This change effectively inlines all PCI config accessors for ramstage as well. Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/arch/x86/Makefile.inc M src/arch/x86/include/arch/pci_ops.h D src/arch/x86/pci_ops.c D src/arch/x86/pci_ops_conf1.c M src/device/Makefile.inc D src/device/pci_ops_mmconf.c M src/include/device/device.h M src/include/device/pci.h M src/include/device/pci_ops.h 9 files changed, 7 insertions(+), 133 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Aaron Durbin: Looks good to me, approved diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e3151ef..6e4ee76 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -327,8 +327,6 @@ ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c -ramstage-y += pci_ops_conf1.c -ramstage-$(CONFIG_NO_MMCONF_SUPPORT) += pci_ops.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 67633f4..e706216 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -17,10 +17,4 @@ #include <arch/pci_io_cfg.h> #include <device/pci_mmio_cfg.h> -#ifndef __SIMPLE_DEVICE__ - -extern const struct pci_bus_operations pci_cf8_conf1; - -#endif - #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/x86/pci_ops.c b/src/arch/x86/pci_ops.c deleted file mode 100644 index f30bffe..0000000 --- a/src/arch/x86/pci_ops.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci_ops.h> - -const struct pci_bus_operations *pci_bus_default_ops(void) -{ - return &pci_cf8_conf1; -} diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c deleted file mode 100644 index 03c2b64..0000000 --- a/src/arch/x86/pci_ops_conf1.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <arch/pci_io_cfg.h> - -/* - * Functions for accessing PCI configuration space with type 1 accesses - */ - -const struct pci_bus_operations pci_cf8_conf1 = { - .read8 = pci_io_read_config8, - .read16 = pci_io_read_config16, - .read32 = pci_io_read_config32, - .write8 = pci_io_write_config8, - .write16 = pci_io_write_config16, - .write32 = pci_io_write_config32, -}; diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index c325a7e..711a403 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -33,7 +33,6 @@ ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c -ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c endif subdirs-y += oprom dram diff --git a/src/device/pci_ops_mmconf.c b/src/device/pci_ops_mmconf.c deleted file mode 100644 index 2fcb961..0000000 --- a/src/device/pci_ops_mmconf.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_mmio_cfg.h> - -#if (CONFIG_MMCONF_BASE_ADDRESS == 0) -#error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!" -#endif - -/* - * Functions for accessing PCI configuration space with mmconf accesses - */ - -static const struct pci_bus_operations pci_ops_mmconf = { - .read8 = pci_mmio_read_config8, - .read16 = pci_mmio_read_config16, - .read32 = pci_mmio_read_config32, - .write8 = pci_mmio_write_config8, - .write16 = pci_mmio_write_config16, - .write32 = pci_mmio_write_config32, -}; - -const struct pci_bus_operations *pci_bus_default_ops(void) -{ - return &pci_ops_mmconf; -} diff --git a/src/include/device/device.h b/src/include/device/device.h index 2e2cda9..7d7be73 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -17,7 +17,6 @@ struct device; struct pci_operations; -struct pci_bus_operations; struct i2c_bus_operations; struct smbus_bus_operations; struct pnp_mode_ops; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 14c4693..f1de7bf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> +#include <device/pci_ops.h> #include <device/pci_rom.h> #include <device/pci_type.h> @@ -33,19 +34,6 @@ void (*set_L1_ss_latency)(struct device *dev, unsigned int off); }; -/* Common pci bus operations */ -struct pci_bus_operations { - uint8_t (*read8)(pci_devfn_t dev, uint16_t reg); - uint16_t (*read16)(pci_devfn_t dev, uint16_t reg); - uint32_t (*read32)(pci_devfn_t dev, uint16_t reg); - void (*write8)(pci_devfn_t dev, uint16_t reg, uint8_t val); - void (*write16)(pci_devfn_t dev, uint16_t reg, uint16_t val); - void (*write32)(pci_devfn_t dev, uint16_t reg, uint32_t val); -}; - -// FIXME: Needs complete pci_bus_operations -#include <device/pci_ops.h> - struct pci_driver { const struct device_operations *ops; unsigned short vendor; diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index bb77754..454795f 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -39,13 +39,6 @@ #include <device/pci.h> -const struct pci_bus_operations *pci_bus_default_ops(void); - -static __always_inline const struct pci_bus_operations *pci_bus_ops(void) -{ - return pci_bus_default_ops(); -} - void __noreturn pcidev_die(void); static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -63,43 +56,37 @@ static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg) { - pci_devfn_t bdf = PCI_BDF(dev); - return pci_bus_ops()->read8(bdf, reg); + return pci_s_read_config8(PCI_BDF(dev), reg); } static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg) { - pci_devfn_t bdf = PCI_BDF(dev); - return pci_bus_ops()->read16(bdf, reg); + return pci_s_read_config16(PCI_BDF(dev), reg); } static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg) { - pci_devfn_t bdf = PCI_BDF(dev); - return pci_bus_ops()->read32(bdf, reg); + return pci_s_read_config32(PCI_BDF(dev), reg); } static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val) { - pci_devfn_t bdf = PCI_BDF(dev); - pci_bus_ops()->write8(bdf, reg, val); + pci_s_write_config8(PCI_BDF(dev), reg, val); } static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val) { - pci_devfn_t bdf = PCI_BDF(dev); - pci_bus_ops()->write16(bdf, reg, val); + pci_s_write_config16(PCI_BDF(dev), reg, val); } static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val) { - pci_devfn_t bdf = PCI_BDF(dev); - pci_bus_ops()->write32(bdf, reg, val); + pci_s_write_config32(PCI_BDF(dev), reg, val); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Gerrit-Change-Number: 31753 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: util/autoport: fix default headers
by Angel Pons (Code Review) 17 Mar '19

17 Mar '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31927 ) Change subject: util/autoport: fix default headers ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/31927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Gerrit-Change-Number: 31927 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 15:19:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci_ops: Reuse romstage PCI config for ramstage
by Kyösti Mälkki (Code Review) 17 Mar '19

17 Mar '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31685 Change subject: device/pci_ops: Reuse romstage PCI config for ramstage ...................................................................... device/pci_ops: Reuse romstage PCI config for ramstage Changing the signatures we do not need to define PCI config access functions twice. Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/pci_ops_conf1.c M src/console/die.c M src/device/pci_ops.c M src/device/pci_ops_mmconf.c M src/include/console/console.h M src/include/device/pci.h M src/include/device/pci_ops.h M src/include/device/pci_type.h 8 files changed, 54 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31685/1 diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c index 1180a82..03c2b64 100644 --- a/src/arch/x86/pci_ops_conf1.c +++ b/src/arch/x86/pci_ops_conf1.c @@ -14,65 +14,17 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <arch/pci_io_cfg.h> + /* * Functions for accessing PCI configuration space with type 1 accesses */ -#if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) -#define CONF_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \ - (devfn << 8) | (where & ~3)) -#else -#define CONF_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \ - (devfn << 8) | ((where & 0xff) & ~3) |\ - ((where & 0xf00)<<16)) -#endif - -static uint8_t pci_conf1_read_config8(int bus, int devfn, int where) -{ - outl(CONF_CMD(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); -} - -static uint16_t pci_conf1_read_config16(int bus, int devfn, int where) -{ - outl(CONF_CMD(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); -} - -static uint32_t pci_conf1_read_config32(int bus, int devfn, int where) -{ - outl(CONF_CMD(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - -static void pci_conf1_write_config8(int bus, int devfn, int where, - uint8_t value) -{ - outl(CONF_CMD(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); -} - -static void pci_conf1_write_config16(int bus, int devfn, int where, - uint16_t value) -{ - outl(CONF_CMD(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); -} - -static void pci_conf1_write_config32(int bus, int devfn, int where, - uint32_t value) -{ - outl(CONF_CMD(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); -} - -#undef CONF_CMD - const struct pci_bus_operations pci_cf8_conf1 = { - .read8 = pci_conf1_read_config8, - .read16 = pci_conf1_read_config16, - .read32 = pci_conf1_read_config32, - .write8 = pci_conf1_write_config8, - .write16 = pci_conf1_write_config16, - .write32 = pci_conf1_write_config32, + .read8 = pci_io_read_config8, + .read16 = pci_io_read_config16, + .read32 = pci_io_read_config32, + .write8 = pci_io_write_config8, + .write16 = pci_io_write_config16, + .write32 = pci_io_write_config32, }; diff --git a/src/console/die.c b/src/console/die.c index aedf66e..3fae3bd 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -37,4 +37,9 @@ die_notify(); halt(); } + +void __noreturn pcidev_die(void) +{ + die("PCI: dev is NULL!\n"); +} #endif diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 12c4e26..35f4261 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -16,61 +16,48 @@ */ #include <stdint.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <device/pci_type.h> static __always_inline const struct pci_bus_operations *pci_bus_ops(void) { return pci_bus_default_ops(); } -static void pcidev_assert(const struct device *dev) -{ - if (dev) - return; - die("PCI: dev is NULL!\n"); -} - u8 pci_read_config8(struct device *dev, unsigned int where) { - pcidev_assert(dev); - return pci_bus_ops()->read8(dev->bus->secondary, - dev->path.pci.devfn, where); + pci_devfn_t bdf = PCI_BDF(dev); + return pci_bus_ops()->read8(bdf, where); } u16 pci_read_config16(struct device *dev, unsigned int where) { - pcidev_assert(dev); - return pci_bus_ops()->read16(dev->bus->secondary, - dev->path.pci.devfn, where); + pci_devfn_t bdf = PCI_BDF(dev); + return pci_bus_ops()->read16(bdf, where); } u32 pci_read_config32(struct device *dev, unsigned int where) { - pcidev_assert(dev); - return pci_bus_ops()->read32(dev->bus->secondary, - dev->path.pci.devfn, where); + pci_devfn_t bdf = PCI_BDF(dev); + return pci_bus_ops()->read32(bdf, where); } void pci_write_config8(struct device *dev, unsigned int where, u8 val) { - pcidev_assert(dev); - pci_bus_ops()->write8(dev->bus->secondary, - dev->path.pci.devfn, where, val); + pci_devfn_t bdf = PCI_BDF(dev); + pci_bus_ops()->write8(bdf, where, val); } void pci_write_config16(struct device *dev, unsigned int where, u16 val) { - pcidev_assert(dev); - pci_bus_ops()->write16(dev->bus->secondary, - dev->path.pci.devfn, where, val); + pci_devfn_t bdf = PCI_BDF(dev); + pci_bus_ops()->write16(bdf, where, val); } void pci_write_config32(struct device *dev, unsigned int where, u32 val) { - pcidev_assert(dev); - pci_bus_ops()->write32(dev->bus->secondary, - dev->path.pci.devfn, where, val); + pci_devfn_t bdf = PCI_BDF(dev); + pci_bus_ops()->write32(bdf, where, val); } diff --git a/src/device/pci_ops_mmconf.c b/src/device/pci_ops_mmconf.c index 0af8f8e..d6fce1d 100644 --- a/src/device/pci_ops_mmconf.c +++ b/src/device/pci_ops_mmconf.c @@ -14,6 +14,7 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <device/pci_mmio_cfg.h> #if (CONFIG_MMCONF_BASE_ADDRESS == 0) #error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!" @@ -23,52 +24,13 @@ * Functions for accessing PCI configuration space with mmconf accesses */ -#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \ - ((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\ - (((SEGBUS) & 0xFFF) << 20) |\ - (((DEVFN) & 0xFF) << 12) |\ - ((WHERE) & 0xFFF)) & ~MASK)) - -static uint8_t pci_mmconf_read_config8(int bus, int devfn, int where) -{ - return read8(PCI_MMIO_ADDR(bus, devfn, where, 0)); -} - -static uint16_t pci_mmconf_read_config16(int bus, int devfn, int where) -{ - return read16(PCI_MMIO_ADDR(bus, devfn, where, 1)); -} - -static uint32_t pci_mmconf_read_config32(int bus, int devfn, int where) -{ - return read32(PCI_MMIO_ADDR(bus, devfn, where, 3)); -} - -static void pci_mmconf_write_config8(int bus, int devfn, int where, - uint8_t value) -{ - write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value); -} - -static void pci_mmconf_write_config16(int bus, int devfn, int where, - uint16_t value) -{ - write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value); -} - -static void pci_mmconf_write_config32(int bus, int devfn, int where, - uint32_t value) -{ - write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value); -} - static const struct pci_bus_operations pci_ops_mmconf = { - .read8 = pci_mmconf_read_config8, - .read16 = pci_mmconf_read_config16, - .read32 = pci_mmconf_read_config32, - .write8 = pci_mmconf_write_config8, - .write16 = pci_mmconf_write_config16, - .write32 = pci_mmconf_write_config32, + .read8 = pci_mmio_read_config8, + .read16 = pci_mmio_read_config16, + .read32 = pci_mmio_read_config32, + .write8 = pci_mmio_write_config8, + .write16 = pci_mmio_write_config16, + .write32 = pci_mmio_write_config32, }; const struct pci_bus_operations *pci_bus_default_ops(void) diff --git a/src/include/console/console.h b/src/include/console/console.h index 2b02334..06658f2 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -41,6 +41,7 @@ /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __noreturn die(const char *msg); +void __noreturn pcidev_die(void); /* * This function is weak and can be overridden to provide additional diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 0ead578..f254c70 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -36,12 +36,12 @@ /* Common pci bus operations */ struct pci_bus_operations { - uint8_t (*read8)(int bus, int devfn, int where); - uint16_t (*read16)(int bus, int devfn, int where); - uint32_t (*read32)(int bus, int devfn, int where); - void (*write8)(int bus, int devfn, int where, uint8_t val); - void (*write16)(int bus, int devfn, int where, uint16_t val); - void (*write32)(int bus, int devfn, int where, uint32_t val); + uint8_t (*read8)(pci_devfn_t dev, unsigned int where); + uint16_t (*read16)(pci_devfn_t dev, unsigned int where); + uint32_t (*read32)(pci_devfn_t dev, unsigned int where); + void (*write8)(pci_devfn_t dev, unsigned int where, uint8_t val); + void (*write16)(pci_devfn_t dev, unsigned int where, uint16_t val); + void (*write32)(pci_devfn_t dev, unsigned int where, uint32_t val); }; struct pci_driver { diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 6971ce4..f7ad181 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -18,6 +18,17 @@ #define pci_write_config16 pci_s_write_config16 #define pci_write_config32 pci_s_write_config32 #else + +/* FIXME: ROMCC chokes on this. */ +#include <console/console.h> + +static __always_inline pci_devfn_t pcidev_assert(const struct device *dev) +{ + if (!dev) + pcidev_die(); + return __PCI_BDF(dev); +} + u8 pci_read_config8(struct device *dev, unsigned int where); u16 pci_read_config16(struct device *dev, unsigned int where); u32 pci_read_config32(struct device *dev, unsigned int where); diff --git a/src/include/device/pci_type.h b/src/include/device/pci_type.h index 0b08e8d..2f03186 100644 --- a/src/include/device/pci_type.h +++ b/src/include/device/pci_type.h @@ -26,4 +26,7 @@ #define PCI_DEV_INVALID (0xffffffffU) +#define __PCI_BDF(dev) ((dev)->bus->secondary << 20 | (dev)->path.pci.devfn << 12) +#define PCI_BDF(dev) pcidev_assert((dev)) + #endif /* DEVICE_PCI_TYPE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00 Gerrit-Change-Number: 31685 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in ...coreboot[master]: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit
by Rizwan Qureshi (Code Review) 16 Mar '19

16 Mar '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 ) Change subject: soc/intel/cannonlake: Clear SUS_PWR_FLR status bit ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c File src/soc/intel/cannonlake/pmutil.c: https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c@1… PS3, Line 146: pmc_clear_suspwrflr > I am wondering if this should be more than just suspwrflr clear i.e. […] makes sense, If FSP is relying on these values we have to make we clear these after FSP is done initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/31902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Gerrit-Change-Number: 31902 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Mar 2019 12:05:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405: Add DRAM resources
by Patrick Georgi (Code Review) 16 Mar '19

16 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29954 ) Change subject: qcs405: Add DRAM resources ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Gerrit-Change-Number: 29954 Gerrit-PatchSet: 14 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 11:56:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Patrick Georgi (Code Review) 16 Mar '19

16 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29948 ) Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Gerrit-Change-Number: 29948 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 11:52:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by Patrick Georgi (Code Review) 16 Mar '19

16 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29950 ) Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 14 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 11:47:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src: Drop unused '#include <halt.h>'
by HAOUAS Elyes (Code Review) 16 Mar '19

16 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31921 Change subject: src: Drop unused '#include <halt.h>' ...................................................................... src: Drop unused '#include <halt.h>' Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/bouncebuf.c M src/commonlib/storage/sdhci.c M src/cpu/intel/haswell/romstage.c M src/ec/google/chromeec/ec.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/early_init.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c 29 files changed, 7 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31921/1 diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 6ddfb70..5d98c74 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -17,7 +17,6 @@ #include <arch/cache.h> #include "bouncebuf.h" -#include <halt.h> #include "storage.h" #include <string.h> #include <commonlib/stdlib.h> diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 8482488..06dffb1 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -24,7 +24,6 @@ #include <commonlib/storage.h> #include <delay.h> #include <endian.h> -#include <halt.h> #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1e5f3d3..e64643a 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -21,7 +21,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <halt.h> #include <lib.h> #include <timestamp.h> #include <device/pci_def.h> diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 629144c..57c1b58 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -23,7 +23,6 @@ #include <bootstate.h> #include <delay.h> #include <elog.h> -#include <halt.h> #include <reset.h> #include <rtc.h> #include <stdlib.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 726e561..6dfbfcb 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 46e2d60..66a503d0 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -27,7 +27,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" -#include <halt.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ce902be..da6b50d 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #include "ec/compal/ene932/ec.h" void pch_enable_lpc(void) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index f60f822..d76e9c1 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -26,7 +26,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #include <bootmode.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index a9b80e8..1259fe8 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -26,7 +26,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 6539cde..0ea982c 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -21,7 +21,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <halt.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 74d491f..1080689 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -28,7 +28,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #include "option_table.h" #if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 9450aa1..57fdbcb 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 8db6095..d29656c 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <halt.h> #include <smp/node.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 11dc203..4f28474 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/pci.h> -#include <halt.h> #include <string.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 5aea59e..fa5122a 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <delay.h> -#include <halt.h> #include <lib.h> #include "pineview.h" #include "raminit.h" diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 757e272..cf1da63 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <halt.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index c979897..d48bac4 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -27,7 +27,6 @@ #include <cpu/intel/romstage.h> #include <device/pci_def.h> #include <device/device.h> -#include <halt.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 5ccc77e..d019ffd 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -26,7 +26,6 @@ #include <pc80/mc146818rtc.h> #include "x4x.h" #include <console/console.h> -#include <halt.h> #include <romstage_handoff.h> void x4x_early_init(void) diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index dfc5366..62f8e42 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <halt.h> #include <mrc_cache.h> #include <soc/gpio.h> #include <soc/iomap.h> diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 8c166cf..37d1365 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -30,7 +30,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <halt.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/intel/fsp_broadwell_de/smihandler.c b/src/soc/intel/fsp_broadwell_de/smihandler.c index 038375b..36a01c6 100644 --- a/src/soc/intel/fsp_broadwell_de/smihandler.c +++ b/src/soc/intel/fsp_broadwell_de/smihandler.c @@ -23,13 +23,11 @@ #include <cpu/x86/smm.h> #include <spi-generic.h> #include <elog.h> -#include <halt.h> #include <soc/lpc.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/smm.h> - /** * @brief Set the EOS bit */ diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index ea9a41b..fa2411d 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -29,7 +29,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <halt.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 5ea0902..b517e6d 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <console/console.h> #include <intelblocks/pmclib.h> -#include <halt.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/tco.h> #include <stdlib.h> diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 65604a1..08ebe98 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -17,7 +17,6 @@ #define SOC_MEDIATEK_MT8183_RTC_H #include <soc/rtc_common.h> -#include <halt.h> /* RTC registers */ enum { diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 64eedfb..d67315b 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <halt.h> #include <soc/rtc_common.h> #include <soc/rtc.h> #include <soc/mt6358.h> diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 7cc3204..4f219e4 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <halt.h> #include <stdint.h> /* Function unit addresses. */ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 51e75f5..ddd1f4f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <halt.h> #include <stdint.h> /* Function unit addresses. */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index c7f668b..374a9d9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -22,11 +22,6 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> -#include <halt.h> -#include "pch.h" - -#include "nvs.h" - #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> @@ -34,6 +29,9 @@ #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/finalize.h> +#include "pch.h" +#include "nvs.h" + static global_nvs_t *gnvs; global_nvs_t *smm_get_gnvs(void) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index cf7f277..31306fb 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -19,7 +19,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> -#include <halt.h> #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmutil.h> #include "i82801gx.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/31921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Gerrit-Change-Number: 31921 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019