coreboot-gerrit March 2019

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Change in ...coreboot[master]: src: Drop unused 'include <device/pciexp.h>'
by HAOUAS Elyes (Code Review) 16 Mar '19

16 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31924 Change subject: src: Drop unused 'include <device/pciexp.h>' ...................................................................... src: Drop unused 'include <device/pciexp.h>' Change-Id: I9b4d72116a66d5a256659fa82682497ef3481e77 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_class.c M src/soc/intel/broadwell/serialio.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/lynxpoint/serialio.c 4 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31924/1 diff --git a/src/device/pci_class.c b/src/device/pci_class.c index aa28ce8..d9c3a4f 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <device/pciexp.h> #include <device/pci_ids.h> #include <stdlib.h> diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 59fb4f7..12e458c 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pciexp.h> #include <device/pci_ids.h> #include <stdlib.h> #include <soc/iobp.h> diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index ea48d9e..8ff41b3 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -19,7 +19,7 @@ #include <arch/acpigen.h> #include <device/device.h> #include <device/pci.h> -#include <device/pciexp.h> + #include "pciehp.h" void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 5224f68..f5c52ef 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pciexp.h> #include <device/pci_ids.h> #include <stdlib.h> #include "pch.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/31924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b4d72116a66d5a256659fa82682497ef3481e77 Gerrit-Change-Number: 31924 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by Patrick Georgi (Code Review) 16 Mar '19

16 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29949 ) Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 11:45:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: FIX CBMEM FUCKUP
by Patrick Rudolph (Code Review) 16 Mar '19

16 Mar '19

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31522 ) Change subject: FIX CBMEM FUCKUP ...................................................................... Abandoned fixed by https://review.coreboot.org/c/coreboot/+/29563 -- To view, visit https://review.coreboot.org/c/coreboot/+/31522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I127fcfac0a404cd13a828058e4814283245bcb10 Gerrit-Change-Number: 31522 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Patrick Rudolph (Code Review) 16 Mar '19

16 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31549 ) Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... Patch Set 8: (12 comments) https://review.coreboot.org/#/c/31549/7/Documentation/arch/x86/pae.md File Documentation/arch/x86/pae.md: https://review.coreboot.org/#/c/31549/7/Documentation/arch/x86/pae.md@13 PS7, Line 13: uint64_t > Can’t this bee offset_t or size_t? No https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c File src/cpu/x86/pae/pgtbl.c: https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@114 PS7, Line 114: vmem_addr > documentation shim is already out of sync Done https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@115 PS7, Line 115: aligned 2 MiB > either `2MiB aligned` or `aligned to 2MiB`, afaik Done https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@116 PS7, Line 116: are > is Done https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@122 PS7, Line 122: * @param pat The pattern to write to the pyhsical memory > AIUI, this is used as a byte pattern? Please mention that in […] It the same what regular memset does. https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@123 PS7, Line 123: * > Document the return value? Use CB_SUCCESS macro? Done https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@125 PS7, Line 125: size_t > What if `length >= 4GiB`? Done https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@126 PS7, Line 126: struct pg_table > This `struct pg_table *` makes it look like the caller would […] Done https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@128 PS7, Line 128: ssize_t offset; > Why not `offset_t`? it does not exist https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@132 PS7, Line 132: page-tables > Above you spell it *pagetables*. I’d prefer *page tables* though. […] Done https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@140 PS7, Line 140: ((uintptr_t)dest < (uintptr_t)vmem_addr)); > However, `pgtbl_buf` and `vmem_addr` must not overlap because of […] Yes thats true, I didn't thought about that case. https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@177 PS7, Line 177: ~((1UL << PDE_IDX_SHIFT) - 1) > PDE_ADDR_MASK? yes, but that assumes no PAE 4KiB PDE mode. That MASK for PAE 2MiB PDE mode is ~((1UL << PDE_IDX_SHIFT) - 1). -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 16 Mar 2019 09:10:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by Patrick Rudolph (Code Review) 16 Mar '19

16 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31550 ) Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... Patch Set 8: (9 comments) https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md File Documentation/arch/x86/pae.md: https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md@13 PS7, Line 13: arch > if it's arch-agnostic, it shouldn't be documented here where should it be documented instead? https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md@17 PS7, Line 17: 4GiB > Space after 4? Done https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c File src/arch/x86/memory_clear.c: https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@48 PS7, Line 48: causes exception > This should be fixed. What did you try? clearing in PAE mode? […] found the problem: CBMEM_FSP_HOB_PTR residing in the first page https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@50 PS7, Line 50: /* Hole at 0xa0000 */ > This hole may contain RAM. Even security critical RAM (probably […] Needs to be fixed by implemented an API that returns memory ranges based on PAMx registers. https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@51 PS7, Line 51: memranges_insert(&mem, 0xf0000, 0x10000, BM_MEM_RAM); > Isn't this usually (flash) ROM? not in coreboot https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@56 PS7, Line 56: BM_MEM_RESERVED); > and BSS? and stack? […] looking at it _programm and _stack are useless on FSP1.0 platforms, as FSP relocates into DRAM after FSP-M. https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@61 PS7, Line 61: memranges_each_entry(r, mem_soc) { : memranges_insert(&mem, range_entry_base(r), range_entry_size(r), : range_entry_tag(r)); : } : > Could also use memranges_clone() instead from the beginning. memranges_clone works only in ramstage https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@67 PS7, Line 67: * Reserve CBMEM - Used as scratch memory for memcpy_pae. > If we were in postcar, CBMEM would already be initialized? Correct, removed postcar https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@82 PS7, Line 82: intptr_t start = (uintptr_t)cbmem_top() - cbmem_size; : void *scratch2 = (void *)ALIGN_UP(start, 2 * MiB); : start = (uintptr_t)scratch2 + 2 * MiB; : void *scratch = (void *)ALIGN_UP(start, 4 * KiB); > This is not easy to follow. Maybe draw some ascii art? […] reworked the logic using an additional reserved range for page tables. -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 16 Mar 2019 09:08:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Deduplicate code
by Patrick Rudolph (Code Review) 16 Mar '19

16 Mar '19

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31713 ) Change subject: drivers/intel/fsp1_0: Deduplicate code ...................................................................... drivers/intel/fsp1_0: Deduplicate code Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0. Allows to have a common entry after FSP-M. Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Jay Talbott <JayTalbott(a)sysproconsulting.com> --- M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/include/soc/romstage.h M src/southbridge/intel/fsp_rangeley/romstage.h 8 files changed, 15 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved Jay Talbott: Looks good to me, but someone else must approve David Guckian: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 2da07d5..4e50abae 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -23,6 +23,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <cpu/intel/microcode.h> +#include <cf9_reset.h> #ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ @@ -63,6 +64,17 @@ #ifdef __PRE_RAM__ +/* The FSP returns here after the fsp_early_init call */ +static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) +{ + *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; + + if (Status == 0xFFFFFFFF) + system_reset(); + + romstage_main_continue(Status, HobListPtr); +} + /* * Call the FSP to do memory init. The FSP doesn't return to this function. * The FSP returns to the romstage_main_continue(). diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index f781329..e0da19e 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -32,10 +32,12 @@ void print_fsp_info(void); void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); -void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); void *find_saved_temp_mem(void *hob_list_ptr); void *find_fsp_reserved_mem(void *hob_list_ptr); +/* function in romstage.c */ +void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); + /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ec36c06..04a696c 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <bootstate.h> #include <cbmem.h> -#include <cf9_reset.h> #include <device/device.h> #include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp1_0/fsp_util.h> @@ -166,16 +165,4 @@ return; } -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, - VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; - - if (Status == 0xFFFFFFFF) { - system_reset(); - } - romstage_main_continue(Status, HobListPtr); -} - #endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c9cbcfe..7e90142 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -336,16 +336,4 @@ return; } -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, - VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; - - if (Status == 0xFFFFFFFF) { - system_reset(); - } - romstage_main_continue(Status, HobListPtr); -} - #endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 9cbc95c..5f0bd8d 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -27,7 +27,6 @@ #include <drivers/intel/fsp1_0/fsp_util.h> void main(FSP_INFO_HEADER *fsp_info_header); -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 54e796d..fd8ca38 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -20,7 +20,6 @@ #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> -#include <cf9_reset.h> #include <device/device.h> #include <device/pci_def.h> #include <drivers/intel/fsp1_0/fsp_util.h> @@ -140,15 +139,3 @@ return; } - -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; - - if (Status == 0xFFFFFFFF) { - system_reset(); - } - - romstage_main_continue(Status, HobListPtr); -} diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h index 877b0a0..63b7fba 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h @@ -24,8 +24,6 @@ #include <stdint.h> #include <fsp.h> -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); - #define NUM_ROMSTAGE_TS 4 void early_mainboard_romstage_entry(void); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 2613577..5827b0f 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -29,6 +29,4 @@ void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask); -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); - #endif /* _RANGELEY_ROMSTAGE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Gerrit-Change-Number: 31713 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by build bot (Jenkins) (Code Review) 16 Mar '19

16 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31549 ) Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/31549/8/src/cpu/x86/pae/pgtbl.c File src/cpu/x86/pae/pgtbl.c: https://review.coreboot.org/#/c/31549/8/src/cpu/x86/pae/pgtbl.c@158 PS8, Line 158: printk(BIOS_ERR, "%s: destination overlaps page tables\n", __func__); line over 80 characters https://review.coreboot.org/#/c/31549/8/src/cpu/x86/pae/pgtbl.c@166 PS8, Line 166: printk(BIOS_ERR, "%s: vmem address overlaps page tables\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 16 Mar 2019 09:00:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by Patrick Rudolph (Code Review) 16 Mar '19

16 Mar '19

Hello Kyösti Mälkki, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31550 to look at the new patch set (#8). Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... arch/x86: Introduce helper to clear memory using PAE * Add Documentation. * Add x86 helper function to clear DRAM on a typical x86 memory map Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/pae.md M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/memory_clear.h A src/arch/x86/memory_clear.c 4 files changed, 162 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31550/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Patrick Rudolph (Code Review) 16 Mar '19

16 Mar '19

Hello Kyösti Mälkki, Aaron Durbin, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31549 to look at the new patch set (#8). Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... cpu/x86/pae/pgtbl: Add memset with PAE To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation. Tested on wedge100s. Takes less than 2 seconds to clear 8GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/index.md A Documentation/arch/x86/pae.md M Documentation/security/memory_clearing.md M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 5 files changed, 183 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31549/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security: Add memory subfolder
by Patrick Rudolph (Code Review) 16 Mar '19

16 Mar '19

Hello Aaron Durbin, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31548 to look at the new patch set (#6). Change subject: security: Add memory subfolder ...................................................................... security: Add memory subfolder Add files to introduce a memory clearing framework. Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by platforms, that are able to clear all DRAM. Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user selectable to always clear DRAM on non S3 boot. The function security_clear_dram_request tells the calling platform when to wipe all DRAM. Will be extended by TEE frameworks. Add Documentation for the new security API. Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/index.md M Documentation/security/index.md A Documentation/security/memory_clearing.md M src/security/Kconfig M src/security/Makefile.inc A src/security/memory/Kconfig A src/security/memory/Makefile.inc A src/security/memory/memory.c A src/security/memory/memory.h 9 files changed, 130 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31548/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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