coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/cannonlake: Add required FSP UPD changes for CML
by Maulik V Vaghela (Code Review) 17 Mar '19

17 Mar '19

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31284 to review the following change. Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML ...................................................................... soc/intel/cannonlake: Add required FSP UPD changes for CML This patch adds required FSP UPD changes for CometLake SoC. Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/serialio.h M src/soc/intel/cannonlake/romstage/fsp_params.c 4 files changed, 62 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31284/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index cb9ad38..f30116b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +36,8 @@ #include <soc/gpio_defs.h> #endif +#define SOC_INTEL_UART_DEV_MAX 3 + struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ @@ -101,7 +103,7 @@ * For CNL, options are as following * When enabled, memory will be training at three different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled - * For WHL/CFL options are as following + * For WHL/CFL/CML options are as following * When enabled, memory will be training at two different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/ enum { @@ -286,6 +288,19 @@ DebugConsent_XDP, /* XDP/Mipi60 */ DebugConsent_USB2_DBC, } DebugConsent; +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[SOC_INTEL_UART_DEV_MAX]; +#else /* * SerialIO device mode selection: * @@ -310,7 +325,7 @@ * PchSerialIoHidden */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; - +#endif /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 866d9c8..ecd22d4 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2018-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,6 +34,16 @@ } const config_t *config = dev->chip_info; +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + + for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) + params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; + + for (int i = 0; i < SOC_INTEL_UART_DEV_MAX; i++) + params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; +#else const int SerialIoDev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -60,6 +70,7 @@ config->SerialIoDevMode[i] == PchSerialIoHidden) params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; } +#endif } /* UPD parameters to be initialized before SiliconInit */ @@ -165,8 +176,11 @@ /* Enable CNVi Wifi if enabled in device tree */ dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + params->CnviMode = dev->enabled; +#else params->PchCnviMode = dev->enabled; - +#endif /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index e152770..fad7283 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,8 +22,33 @@ PchSerialIoPci, PchSerialIoAcpi, PchSerialIoHidden, +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + PchSerialIoSkipInit +#endif } PCH_SERIAL_IO_MODE; +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5 +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2 +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2 +}; +#else typedef enum { PchSerialIoIndexI2C0, PchSerialIoIndexI2C1, @@ -39,5 +64,6 @@ PchSerialIoIndexUART2, PchSerialIoIndexMAX } PCH_SERIAL_IO_CONTROLLER; +#endif #endif diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index b8b2c17..c436e50 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by -- To view, visit https://review.coreboot.org/c/coreboot/+/31284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d Gerrit-Change-Number: 31284 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: fix default headers
by HAOUAS Elyes (Code Review) 17 Mar '19

17 Mar '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31927 ) Change subject: util/autoport: fix default headers ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/31927/2/util/autoport/bd82x6x.go File util/autoport/bd82x6x.go: https://review.coreboot.org/#/c/31927/2/util/autoport/bd82x6x.go@309 PS2, Line 309: #include <lib.h> : #include <timestamp.h> : #include <arch/byteorder.h> Maybe I'm wrong, but I would drop this... and if it is needed, the compiler will complain :p https://review.coreboot.org/#/c/31927/2/util/autoport/bd82x6x.go@316 PS2, Line 316: #include <cpu/x86/lapic.h> : #include <arch/acpi.h> also I would drop https://review.coreboot.org/#/c/31927/2/util/autoport/bd82x6x.go@323 PS2, Line 323: #include <arch/cpu.h> : #include <cpu/x86/msr.h> and this. -- To view, visit https://review.coreboot.org/c/coreboot/+/31927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Gerrit-Change-Number: 31927 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 16 Mar 2019 20:42:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/{hatch,octopus}: Drop unused 'include <memory_info.h>'
by HAOUAS Elyes (Code Review) 17 Mar '19

17 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31937 Change subject: mb/google/{hatch,octopus}: Drop unused 'include <memory_info.h>' ...................................................................... mb/google/{hatch,octopus}: Drop unused 'include <memory_info.h>' Change-Id: Ic0fc03c4dcf03fae71a5eb9a9de7c10f7e9a6454 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/hatch/romstage.c M src/mainboard/google/octopus/romstage.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31937/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index bdf951b..e4a7fd7 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -16,7 +16,6 @@ #include <baseboard/variants.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <memory_info.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <string.h> diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index c5bd996..6e00c5a 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -17,7 +17,6 @@ #include <boardid.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <memory_info.h> #include <soc/meminit.h> #include <soc/romstage.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0fc03c4dcf03fae71a5eb9a9de7c10f7e9a6454 Gerrit-Change-Number: 31937 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by Nico Huber (Code Review) 17 Mar '19

17 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31550 ) Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... Patch Set 8: (13 comments) https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md File Documentation/arch/x86/pae.md: https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md@13 PS7, Line 13: arch > where should it be documented instead? It's an API. I'd suggest the header file. https://review.coreboot.org/#/c/31550/7/src/arch/x86/Makefile.inc File src/arch/x86/Makefile.inc: https://review.coreboot.org/#/c/31550/7/src/arch/x86/Makefile.inc@281 PS7, Line 281: postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory_clear.c > postcar has global variables in RAM, doesn't it? […] Done https://review.coreboot.org/#/c/31550/7/src/arch/x86/include/arch/memory_cl… File src/arch/x86/include/arch/memory_clear.h: https://review.coreboot.org/#/c/31550/7/src/arch/x86/include/arch/memory_cl… PS7, Line 2: * This file is part of the coreboot project. : * : * Copyright (C) 2019 9elements Agency GmbH : * Copyright (C) 2019 Facebook Inc. : * : * Redistribution and use in source and binary forms, with or without : * modification, are permitted provided that the following conditions : * are met: : * 1. Redistributions of source code must retain the above copyright : * notice, this list of conditions and the following disclaimer. : * 2. Redistributions in binary form must reproduce the above copyright : * notice, this list of conditions and the following disclaimer in the : * documentation and/or other materials provided with the distribution. : * 3. The name of the author may not be used to endorse or promote products : * derived from this software without specific prior written permission. : * : * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND : * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE : * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE : * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE : * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL : * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS : * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) : * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT : * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY : * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF : * SUCH DAMAGE. > Unlikely to apply to an interface anyway... Done https://review.coreboot.org/#/c/31550/7/src/arch/x86/include/arch/memory_cl… PS7, Line 29: * > Remove this line? Done https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c File src/arch/x86/memory_clear.c: https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@38 PS7, Line 38: const struct memranges *mem_soc) > Why not make it simply a pre-filled `struct memranges *`? […] Done https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@61 PS7, Line 61: memranges_each_entry(r, mem_soc) { : memranges_insert(&mem, range_entry_base(r), range_entry_size(r), : range_entry_tag(r)); : } : > memranges_clone works only in ramstage Ack https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@67 PS7, Line 67: * Reserve CBMEM - Used as scratch memory for memcpy_pae. > Correct, removed postcar Done https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@82 PS7, Line 82: intptr_t start = (uintptr_t)cbmem_top() - cbmem_size; : void *scratch2 = (void *)ALIGN_UP(start, 2 * MiB); : start = (uintptr_t)scratch2 + 2 * MiB; : void *scratch = (void *)ALIGN_UP(start, 4 * KiB); > reworked the logic using an additional reserved range for page tables. Done https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@85 PS7, Line 85: void *scratch = (void *)ALIGN_UP(start, 4 * KiB); > NB. Weaker alignment makes this a no-op. Done https://review.coreboot.org/#/c/31550/8/src/arch/x86/memory_clear.c File src/arch/x86/memory_clear.c: https://review.coreboot.org/#/c/31550/8/src/arch/x86/memory_clear.c@56 PS8, Line 56: 20 * KiB Maybe we should make this a constant as part of the memset_pae() interface? https://review.coreboot.org/#/c/31550/8/src/arch/x86/memory_clear.c@79 PS8, Line 79: 2 * MiB This too, constant for the interface? Hmmm, in case, for the alignments too. https://review.coreboot.org/#/c/31550/8/src/arch/x86/memory_clear.c@73 PS8, Line 73: found = 0; : /* Find a spot for virtual memory address */ : memranges_each_entry(r, &mem) { : if (range_entry_tag(r) != BM_MEM_RAM) : continue; : : if (ALIGN_UP(range_entry_base(r) + 2 * MiB, 2 * MiB) + 2 * MiB > : range_entry_end(r)) : continue; : : vmem_addr = ALIGN_UP(range_entry_base(r) + 2 * MiB, 2 * MiB); : found = 1; : break; : } : : if (!found) { : printk(BIOS_ERR, "%s: Couldn't place vmem address\n", __func__); : return 1; : } Move into a helper function? https://review.coreboot.org/#/c/31550/8/src/arch/x86/memory_clear.c@100 PS8, Line 100: /* fastpath */ Is it really faster? -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 16 Mar 2019 19:27:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by mikeb mikeb (Code Review) 17 Mar '19

17 Mar '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28425 ) Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... Patch Set 7: Code-Review+1 Added the return values to "check_ucode_patches.sh" script, and had to rebase also. -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 7 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 19:27:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by build bot (Jenkins) (Code Review) 17 Mar '19

17 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28425 ) Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... Patch Set 7: (4 comments) https://review.coreboot.org/#/c/28425/7/apply_ucode_patches.sh File apply_ucode_patches.sh: https://review.coreboot.org/#/c/28425/7/apply_ucode_patches.sh@4 PS7, Line 4: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/7/apply_ucode_patches.sh@9 PS7, Line 9: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters https://review.coreboot.org/#/c/28425/7/get_ucode_patches.sh File get_ucode_patches.sh: https://review.coreboot.org/#/c/28425/7/get_ucode_patches.sh@5 PS7, Line 5: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/7/get_ucode_patches.sh@11 PS7, Line 11: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 7 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 19:19:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by build bot (Jenkins) (Code Review) 17 Mar '19

17 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28425 ) Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... Patch Set 6: (4 comments) https://review.coreboot.org/#/c/28425/6/apply_ucode_patches.sh File apply_ucode_patches.sh: https://review.coreboot.org/#/c/28425/6/apply_ucode_patches.sh@4 PS6, Line 4: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/6/apply_ucode_patches.sh@9 PS6, Line 9: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters https://review.coreboot.org/#/c/28425/6/get_ucode_patches.sh File get_ucode_patches.sh: https://review.coreboot.org/#/c/28425/6/get_ucode_patches.sh@5 PS6, Line 5: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/6/get_ucode_patches.sh@11 PS6, Line 11: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 6 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 16 Mar 2019 19:17:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by mikeb mikeb (Code Review) 17 Mar '19

17 Mar '19

Hello Paul Menzel, Mike Banon, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28425 to look at the new patch set (#6). Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates These scripts will help you to securely and conveniently apply the two changes 28273 and 28370 to update AMD microcodes for f15tn and f16kb family processors. Save to ./coreboot/ then run ./get_ucode_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/28273 src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 https://review.coreboot.org/c/coreboot/+/28370 src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> --- A apply_ucode_patches.sh A check_ucode_patches.sh A get_ucode_patches.sh A sha256sums_correct.txt 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/28425/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 6 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/foxconn/g41m: Fix overridetree
by Arthur Heymans (Code Review) 17 Mar '19

17 Mar '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31935 ) Change subject: mb/foxconn/g41m: Fix overridetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If507c8ea9c865ff86e127226b93a8579bcf39d8d Gerrit-Change-Number: 31935 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Mar 2019 19:01:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/sconfig: Emit array of PNP UART devices
by Kyösti Mälkki (Code Review) 17 Mar '19

17 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31934 ) Change subject: util/sconfig: Emit array of PNP UART devices ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/31934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9330bcd5545ec3f94c1c14ed4a639f1ef0548e43 Gerrit-Change-Number: 31934 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Mar 2019 18:55:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2019