coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

1 participants
1542 discussions

Change in ...coreboot[master]: mb/google/poppy/variant/atlas: change speaker IV channels
by Jenny Tc (Code Review) 03 Apr '19

03 Apr '19

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31637 Change subject: mb/google/poppy/variant/atlas: change speaker IV channels ...................................................................... mb/google/poppy/variant/atlas: change speaker IV channels Change speaker IV channels for max98373 to match with 24 bit topology firmware BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: Ib572e6ae219f899f332dcdb0661eb4eee36fc019 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31637/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 5b49884..d653993 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -310,16 +310,16 @@ device pci 19.1 off end # I2C #5 device pci 19.2 on chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" register "uid" = "0" register "desc" = ""RIGHT SPEAKER AMP"" register "name" = ""MAXR"" device i2c 31 on end end chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" + register "vmon_slot_no" = "3" + register "imon_slot_no" = "2" register "uid" = "1" register "desc" = ""LEFT SPEAKER AMP"" register "name" = ""MAXL"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib572e6ae219f899f332dcdb0661eb4eee36fc019 Gerrit-Change-Number: 31637 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: change speaker IV channels
by Jenny Tc (Code Review) 03 Apr '19

03 Apr '19

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31636 Change subject: mb/google/poppy/variant/nocturne: change speaker IV channels ...................................................................... mb/google/poppy/variant/nocturne: change speaker IV channels Change speaker IV channels for max98373 to match with 24 bit topology firmware BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I5d94d473b25b23e206c998ca9bd8bd776b76d2bb Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31636/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 4d9403c..5b84c96 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -403,16 +403,16 @@ end # I2C #5 device pci 19.2 on chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" register "uid" = "0" register "desc" = ""RIGHT SPEAKER AMP"" register "name" = ""MAXR"" device i2c 32 on end end chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" + register "vmon_slot_no" = "3" + register "imon_slot_no" = "2" register "uid" = "1" register "desc" = ""LEFT SPEAKER AMP"" register "name" = ""MAXL"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d94d473b25b23e206c998ca9bd8bd776b76d2bb Gerrit-Change-Number: 31636 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proo...
by John Looney (Code Review) 02 Apr '19

02 Apr '19

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32081 Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept ...................................................................... Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept Change-Id: I8c31fa79e13be237a752f47e72a6a7025fe9dffd --- M src/arch/x86/acpi.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.h M src/mainboard/emulation/qemu-q35/Kconfig 4 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/32081/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401..7bbbd2f 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -38,7 +38,6 @@ */ #include <console/console.h> -#include <string.h> #include <arch/acpi.h> #include <arch/acpi_ivrs.h> #include <arch/acpigen.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..2c5124b 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -225,6 +225,8 @@ BiosLinkerLoaderEntry *s; unsigned long *addrs, current; uint8_t *ptr; + acpi_rsdp_t *rsdp = NULL; + acpi_header_t *ssdt; int i, j, src, dst, max; if (fw_cfg_check_file(&f, "etc/table-loader")) @@ -251,6 +253,10 @@ printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", s[i].alloc.file, current, f.size); + if(!strncmp(s[i].alloc.file, "etc/acpi/rsdp", 13)) { + printk(BIOS_DEBUG, "Found RSDP at 0x%lx\n", current); + rsdp = (acpi_rsdp_t *) current; + } fw_cfg_get(f.select, (void *)current, f.size); addrs[i] = current; current += f.size; @@ -322,6 +328,16 @@ }; } + if(rsdp) { + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(acpi_header_t)) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + current = acpi_align_current(current); + } + } + printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n"); free(s); free(addrs); diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h index 975801b..070d61d 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h @@ -14,6 +14,7 @@ #define FW_CFG_H #include "fw_cfg_if.h" +int is_rsdp(char *); void fw_cfg_get(uint16_t entry, void *dst, int dstlen); int fw_cfg_check_file(FWCfgFile *file, const char *name); int fw_cfg_max_cpus(void); diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 815b93b..0672092 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -54,4 +54,8 @@ hex default 0x4000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_EMULATION_QEMU_X86_Q35 -- To view, visit https://review.coreboot.org/c/coreboot/+/32081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c31fa79e13be237a752f47e72a6a7025fe9dffd Gerrit-Change-Number: 32081 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: TEST
by HAOUAS Elyes (Code Review) 02 Apr '19

02 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32128 Change subject: TEST ...................................................................... TEST Change-Id: Id50a0d3c875c9d71a78b22cba1a0cc9410786c91 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/smaug/romstage.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/32128/1 diff --git a/src/mainboard/google/smaug/romstage.c b/src/mainboard/google/smaug/romstage.c index fd7c07f..affb04f 100644 --- a/src/mainboard/google/smaug/romstage.c +++ b/src/mainboard/google/smaug/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +/* Just for test */ #include <delay.h> #include <soc/addressmap.h> #include <device/i2c_simple.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id50a0d3c875c9d71a78b22cba1a0cc9410786c91 Gerrit-Change-Number: 32128 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 12

Change in ...coreboot[master]: payloads/tianocore: Don't fail on resetting boot logo
by Matt DeVillier (Code Review) 02 Apr '19

02 Apr '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32133 Change subject: payloads/tianocore: Don't fail on resetting boot logo ...................................................................... payloads/tianocore: Don't fail on resetting boot logo If using a commit/branch which doesn't use a boot logo, we don't want the build to fail unnecessarily Test: build with upstream Tianocore commit hash, avoid failure after successful compilation. Change-Id: Ic41bacbb97926e9538f434aecc0f0eebc5f6326f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32133/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 2c7439c..d5e26de 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -100,7 +100,7 @@ fi; \ build $(BUILD_STR); \ mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ - git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 + git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 | true clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic41bacbb97926e9538f434aecc0f0eebc5f6326f Gerrit-Change-Number: 32133 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Little bit more helpful, giving back the lines for each file if any
by Balázs Vinarz (Code Review) 02 Apr '19

02 Apr '19

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30988 Change subject: Little bit more helpful, giving back the lines for each file if any ...................................................................... Little bit more helpful, giving back the lines for each file if any Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30988/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index f9b7891..b2011e7 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -20,7 +20,7 @@ # shellcheck disable=SC2086,SC2046 if uname | grep -qi "linux"; then - grep -l "[[:space:]][[:space:]]*$" \ + grep -n -H "[[:space:]][[:space:]]*$" \ $(git ls-files $INCLUDELIST | \ grep -Ev "($EXCLUDELIST)" ) | \ sed -e "s,^.*$,File & has lines ending with whitespace.," -- To view, visit https://review.coreboot.org/c/coreboot/+/30988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 Gerrit-Change-Number: 30988 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: bootmode: display_init_required() to check VBOOT and OPROM_MATTERS
by Julius Werner (Code Review) 02 Apr '19

02 Apr '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32112 Change subject: bootmode: display_init_required() to check VBOOT and OPROM_MATTERS ...................................................................... bootmode: display_init_required() to check VBOOT and OPROM_MATTERS Skipping display init on normal-mode boot is a vboot feature, not specific to Chrome OS. Fix the code in display_init_required() to check CONFIG_VBOOT rather than CONFIG_CHROMEOS now that the two aren't always the same anymore. Also add a check to guarantee at compile time that VBOOT_OPROM_MATTERS is enabled on all platforms that make a check to this function (when VBOOT is also enabled). The whole display skipping mechanism is based on the oprom_needed NVRAM flag, and skipping display init without enabling the option to tell vboot that it needs to pay attention to that flag would make the whole thing not work right. Change-Id: I5d6421509bdcdaa61b78015af3fa6241fe75bb7f Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/lib/bootmode.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32112/1 diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index e402536..b7ab649 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -35,8 +36,12 @@ int display_init_required(void) { /* For Chrome OS always honor vboot_handoff_skip_display_init(). */ - if (CONFIG(CHROMEOS)) + if (CONFIG(VBOOT)) { + if (!CONFIG(VBOOT_OPROM_MATTERS)) + dead_code("If you call display_init_required() anywhere" + ", you need to select VBOOT_OPROM_MATTERS!"); return !vboot_handoff_skip_display_init(); + } /* By default always initialize display. */ return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/32112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d6421509bdcdaa61b78015af3fa6241fe75bb7f Gerrit-Change-Number: 32112 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in ...coreboot[master]: mediatek/mt8183: Fix RTC initialization flow
by Ran Bi (Code Review) 02 Apr '19

02 Apr '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31968 Change subject: mediatek/mt8183: Fix RTC initialization flow ...................................................................... mediatek/mt8183: Fix RTC initialization flow 1. fix RTC initialization flow 2. fix RTC lpd settings BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136 Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8173/include/soc/rtc.h M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 6 files changed, 77 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31968/1 diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 41e772e..b652ad5 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -99,7 +99,6 @@ int rtc_writeif_unlock(void); void rtc_xosc_write(u16 val); int rtc_reg_init(void); -u8 rtc_check_state(void); void rtc_boot_common(void); #endif /* SOC_MEDIATEK_RTC_COMMON_H */ diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index fd40cb5..647ae1e 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -137,7 +137,7 @@ return rtc_write_trigger(); } -u8 rtc_check_state(void) +static u8 rtc_check_state(void) { u16 con; u16 pwrky1; @@ -147,6 +147,9 @@ pwrap_read(RTC_POWERKEY1, &pwrky1); pwrap_read(RTC_POWERKEY2, &pwrky2); + printk(BIOS_INFO, "[RTC] con = %x, pwrkey1 = %x, pwrkey2 = %x\n", + con, pwrky1, pwrky2); + if (con & RTC_CON_LPSTA_RAW) return RTC_STATE_INIT; diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index fe5cbac..0ee944a 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -112,7 +112,7 @@ /* external API */ void rtc_osc_init(void); -int rtc_init(u8 recover); +bool rtc_init(u8 recover); void rtc_boot(void); #endif /* SOC_MEDIATEK_MT8173_RTC_H */ diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 5b7d486..056c051 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -71,15 +71,15 @@ } /* rtc init check */ -int rtc_init(u8 recover) +bool rtc_init(u8 recover) { printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); if (!rtc_writeif_unlock()) - return 0; + return false; if (!rtc_gpio_init()) - return 0; + return false; /* Use SW to detect 32K mode instead of HW */ if (recover) @@ -94,7 +94,7 @@ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); if (!rtc_write_trigger()) - return 0; + return false; if (recover) pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9); @@ -102,11 +102,11 @@ rtc_xosc_write(0); if (!rtc_reg_init()) - return 0; + return false; if (!rtc_lpd_init()) - return 0; + return false; - return 1; + return true; } /* enable rtc bbpu */ diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 08ebe98..b0c1d4a 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -106,6 +106,14 @@ RTC_REG_XOSC32_ENB = 1 << 15 }; +enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13, + RTC_LPD_OPT_EOSC_LPD = 1 << 13, + RTC_LPD_OPT_XOSC_LPD = 2 << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13, + RTC_LPD_OPT_MASK = 3 << 13 +}; + /* PMIC TOP Register Definition */ enum { PMIC_RG_SCK_TOP_CON0 = 0x050C @@ -142,7 +150,7 @@ /* external API */ void rtc_bbpu_power_on(void); void rtc_osc_init(void); -int rtc_init(u8 recover); +bool rtc_init(u8 recover); void rtc_boot(void); #endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index d67315b..69e4f0c 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -64,7 +64,8 @@ /* Export 32K clock RTC_32K2V8 */ pwrap_read(RTC_CON, &con); - con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN + | RTC_CON_XOSC32_LPEN); con |= (RTC_CON_GPEN | RTC_CON_GOE); con &= ~(RTC_CON_F32KOB); pwrap_write(RTC_CON, con); @@ -81,9 +82,17 @@ /* low power detect setting */ static int rtc_lpd_init(void) { - u16 con; + u16 con, sec; - con = pwrap_read(RTC_CON, &con) | RTC_CON_XOSC32_LPEN; + /* set RTC_LPD_OPT */ + pwrap_read(RTC_AL_SEC, &sec); + sec |= RTC_LPD_OPT_F32K_CK_ALIVE; + pwrap_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) + return 0; + + pwrap_read(RTC_CON, &con); + con |= RTC_CON_XOSC32_LPEN; con &= ~RTC_CON_LPRST; pwrap_write(RTC_CON, con); if (!rtc_write_trigger()) @@ -99,7 +108,8 @@ if (!rtc_write_trigger()) return 0; - con = pwrap_read(RTC_CON, &con) | RTC_CON_EOSC32_LPEN; + pwrap_read(RTC_CON, &con); + con |= RTC_CON_EOSC32_LPEN; con &= ~RTC_CON_LPRST; pwrap_write(RTC_CON, con); if (!rtc_write_trigger()) @@ -115,6 +125,18 @@ if (!rtc_write_trigger()) return 0; + pwrap_read(RTC_CON, &con); + con &= ~RTC_CON_XOSC32_LPEN; + pwrap_write(RTC_CON, con); + + /* set RTC_LPD_OPT */ + pwrap_read(RTC_AL_SEC, &sec); + sec &= ~RTC_LPD_OPT_MASK; + sec |= RTC_LPD_OPT_EOSC_LPD; + pwrap_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) + return 0; + return 1; } @@ -142,36 +164,46 @@ } /* rtc init check */ -int rtc_init(u8 recover) +bool rtc_init(u8 recover) { printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); - if (!rtc_writeif_unlock()) - return 0; - - if (!rtc_gpio_init()) - return 0; - - /* using dcxo 32K clock */ - rtc_enable_dcxo(); - - if (recover) - mdelay(20); - /* write powerkeys */ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); if (!rtc_write_trigger()) - return 0; + return false; + + if (!rtc_writeif_unlock()) + return false; + + /* using dcxo 32K clock */ + rtc_enable_dcxo(); + if (recover) + mdelay(20); + + if (!rtc_gpio_init()) + return false; + + if (!rtc_hw_init()) + return false; if (!rtc_reg_init()) - return 0; - if (!rtc_lpd_init()) - return 0; - if (!rtc_hw_init()) - return 0; + return false; - return 1; + if (!rtc_lpd_init()) + return false; + + /* write powerkeys again to enable lpd */ + pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + if (!rtc_write_trigger()) + return false; + + if (!rtc_writeif_unlock()) + return false; + + return true; } /* enable rtc bbpu */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136 Gerrit-Change-Number: 31968 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

6 12

Change in ...coreboot[master]: mb/google/poppy/variants/nami: update sku_ids for Pantheon
by Frank Wu (Code Review) 02 Apr '19

02 Apr '19

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32098 Change subject: mb/google/poppy/variants/nami: update sku_ids for Pantheon ...................................................................... mb/google/poppy/variants/nami: update sku_ids for Pantheon The sku ids are updated for Pantheon. Sync'ing the sku_ids list in the master sku sheet for Pantheon. BUG=b:121207221 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/include/variant/sku.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/32098/1 diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 835864e..70f2008 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -24,8 +24,8 @@ #define SKU_0_PANTHEON 0x3F63 #define SKU_1_PANTHEON 0x3F67 #define SKU_2_PANTHEON 0x3F62 -#define SKU_3_PANTHEON 0xBF63 -#define SKU_4_PANTHEON 0xBF62 +#define SKU_3_PANTHEON 0x8000BF63 +#define SKU_4_PANTHEON 0x8000BF62 #define SKU_0_SONA 0x3AE2 #define SKU_1_SONA 0x3AE3 #define SKU_0_AKALI 0x29E1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0 Gerrit-Change-Number: 32098 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mb/google/hatch: Change GPIO_E1 setting for EVT
by John Su (Code Review) 02 Apr '19

02 Apr '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32099 Change subject: mb/google/hatch: Change GPIO_E1 setting for EVT ...................................................................... mb/google/hatch: Change GPIO_E1 setting for EVT For HW require to change GPIO_E1. Change GOIO_E1 setting from NF2(SATAPCIE1) to NF1(SATAGP1). BUG=b:123730924 TEST=flash BIOS and make sure hatch boots up properly Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32099/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 68bbaab..dbe4048 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -232,8 +232,8 @@ /* E0 : GPP_E0 ==> NC */ PAD_NC(GPP_E0, NONE), - /* E1 : SATAGP1 */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* E1 : SATAPCIE1 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E2 : GPP_E2 ==> NC */ PAD_NC(GPP_E2, NONE), /* E3 : GPP_E3 ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911 Gerrit-Change-Number: 32099 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2019