Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32110
Change subject: mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST
......................................................................
mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST
GPP_A12 is being GPIO padlocked and cannot used in kernel. Unlock the
GPIO pads to export this pin in kernel to be used as FPMCU_RST.
GPP_A_12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay
resuming to S0. If this pad is not locked and platform was not initially
designed for this functionality, malware could reconfigure this pads
setting under OS (switch to Native3), which would make platform not able
to resume until G3 is applied. To prevent misuse of this pad,
re-configure this pad before entering S3 and S5 to guarantee that the
pad configuration is correct.
BUG=b:128686027
Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32110/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index b974e49..8529d5916 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -411,8 +411,12 @@
return gpio_table;
}
-/* Default GPIO settings before entering sleep. */
+/*
+ * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL
+ * as GPO before entering sleep.
+ */
static const struct pad_config default_sleep_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
};
/*
@@ -421,6 +425,7 @@
* turn off EN_PP3300_WWAN.
*/
static const struct pad_config s5_sleep_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
};
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 6173403..57d004f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -328,6 +328,9 @@
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
+
+ /* Unlock all GPIO pads */
+ tconfig->PchUnlockGpioPads = 1;
}
/* Mainboard GPIO Configuration */
--
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Gerrit-Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4
Gerrit-Change-Number: 32110
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32079 )
Change subject: drivers/intel/fsp2_0: Use same stack with coreboot
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32079/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/32079/3//COMMIT_MSG@9
PS3, Line 9: This patch ensures to have same stack base for FSP and coreboot.
:
: Feature added in FSP2.1
: - Remove stack swapping from FSP.
: - Stack will be shared between coreboot and FSP.
Isn't this CL actually correcting the stack base pointer passed into FSP rather than enabling the feature? I believe the feature was already enabled here CB:28358, just that the stack base pointer was set incorrectly?
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Simon Newton has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32080
Change subject: : mainboard/asus/p8h61-m_pro : Add TPM module
......................................................................
: mainboard/asus/p8h61-m_pro : Add TPM module
modified mainboard/asus/p8h61-m_pro/Kconfig to include MAINBOARD_HAS_LPC_TPM
modified mainboard/asus/p8h61-m_pro/devicetree.cb to include drivers/pc80/tpm on device pnp 4e.0
Tested with TPM 1.2 and 2.0. Seaboot payload, Linux OS
Change-Id: Icdad9a41b61221b536f2ac695f44319f6b0599e7
Signed-off-by: Simon Newton <simon.newton(a)gmail.com>
---
M src/mainboard/asus/p8h61-m_pro/Kconfig
M src/mainboard/asus/p8h61-m_pro/devicetree.cb
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32080/1
diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig
index 4d24187..082d3e4 100644
--- a/src/mainboard/asus/p8h61-m_pro/Kconfig
+++ b/src/mainboard/asus/p8h61-m_pro/Kconfig
@@ -30,6 +30,7 @@
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select DRIVERS_ASMEDIA_ASPM_BLACKLIST
+ select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR
string
diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
index 9407aab..f853452 100644
--- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb
+++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
@@ -109,6 +109,9 @@
irq 0xe5 = 0xff
end
end
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM module
+ end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
--
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Sergey Alirzaev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 )
Change subject: lenovo/x230: introduce FHD variant
......................................................................
Patch Set 7:
> Patch Set 7:
>
> > At the moment the fhd mod board requires 3.3V from a separate cable, which causes elevated power consumption especially when the lid is closed or the machine is sleeping.
> > This is because the tapped source is always on.
> > Though if it was possible to provide power through the VCC3P power rail instead, the board could be supplied with power only when the display is supposed to be on. This would eliminate the extra cable and only requires that J1 jumper is closed on the board. I tried it myself and also measured a the corresponding pad but there seems to be no voltage present from the lvds connector with the current state of this patch.
> >
> > Maybe someone more knowledgeable has an idea on how to implement this?
>
> Did you also measure the voltage when Linux has booted?
> I would assume that it works in Linux. If that is the
> case, all that is left (as mentioned before) is to make
> libgfxinit aware of the panel at the DP connector (needs
> some restructuring, though).
I have some hopefully relevant code:
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -557,6 +557,10 @@ static void gma_pm_init_post_vbios(struct device *dev)
gtt_write(0xc4030, reg32);
}
+ /* Turn the panel power on using eDP VDD Override */
+ gtt_write(PCH_PP_CONTROL, gtt_read(PCH_PP_CONTROL) | PCH_PP_UNLOCK | EDP_FORCE_VDD);
+ udelay(125000); /* And wait until it powers up */
+
/* Setup Panel Power On Delays */
reg32 = gtt_read(0xc7208);
if (!reg32) {
--
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Hello Patrick Rudolph, Aaron Durbin, Felix Held, Vanny E, Julius Werner, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26796
to look at the new patch set (#11).
Change subject: src: include <assert.h> when appropriate
......................................................................
src: include <assert.h> when appropriate
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/arch/arm64/arm_tf.c
M src/arch/x86/acpigen.c
M src/arch/x86/include/arch/acpigen.h
M src/commonlib/storage/pci_sdhci.c
M src/commonlib/storage/sd.c
M src/commonlib/storage/sd_mmc.c
M src/commonlib/storage/sdhci.c
M src/commonlib/storage/sdhci_adma.c
M src/commonlib/storage/storage.c
M src/cpu/intel/hyperthreading/intel_sibling.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/drivers/spi/winbond.c
M src/lib/gpio.c
M src/mainboard/google/dragonegg/romstage_fsp_params.c
M src/mainboard/intel/galileo/vboot.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/security/vboot/vbnv_flash.c
M src/soc/cavium/cn81xx/ecam0.c
M src/soc/cavium/cn81xx/twsi.c
M src/soc/cavium/common/ecam.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/apollolake/gpio_apl.c
M src/soc/intel/apollolake/gpio_glk.c
M src/soc/intel/apollolake/uart.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/cannonlake/uart.c
M src/soc/intel/common/block/sgx/sgx.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/denverton_ns/gpio.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/icelake/uart.c
M src/soc/intel/quark/spi.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/gpio.c
M src/soc/mediatek/common/include/soc/rtc_common.h
M src/soc/mediatek/common/pmic_wrap.c
M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
M src/soc/mediatek/mt8173/emi.c
M src/soc/mediatek/mt8173/pmic_wrap.c
M src/soc/mediatek/mt8183/mt6358.c
M src/soc/qualcomm/ipq40xx/i2c.c
M src/soc/qualcomm/ipq806x/i2c.c
M src/soc/rockchip/common/edp.c
M src/soc/rockchip/common/pwm.c
M src/soc/rockchip/rk3288/hdmi.c
M src/soc/rockchip/rk3288/tsadc.c
M src/soc/rockchip/rk3399/bl31_plat_params.c
M src/soc/rockchip/rk3399/mipi.c
M src/soc/rockchip/rk3399/tsadc.c
M src/soc/samsung/exynos5250/alternate_cbfs.c
M src/soc/samsung/exynos5250/pinmux.c
M src/soc/samsung/exynos5420/alternate_cbfs.c
M src/soc/samsung/exynos5420/pinmux.c
M src/superio/renesas/m3885x/superio.c
M src/superio/smsc/lpc47n227/early_serial.c
56 files changed, 4 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/26796/11
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29301 )
Change subject: src: Use include <reset.h> when appropriate
......................................................................
Patch Set 15: Code-Review+2
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Hello Patrick Rudolph, Aaron Durbin, Julius Werner, Huang Jin, York Yang, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29301
to look at the new patch set (#15).
Change subject: src: Use include <reset.h> when appropriate
......................................................................
src: Use include <reset.h> when appropriate
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/arch/x86/cf9_reset.c
M src/cpu/amd/family_10h-family_15h/init_cpus.h
M src/cpu/intel/fsp_model_406dx/bootblock.c
M src/drivers/intel/fsp2_0/stage_cache.c
M src/ec/google/chromeec/ec.c
M src/lib/hardwaremain.c
M src/mainboard/google/foster/pmic.c
M src/mainboard/google/smaug/pmic.c
M src/mainboard/google/veyron/bootblock.c
M src/mainboard/google/veyron_mickey/bootblock.c
M src/mainboard/google/veyron_rialto/bootblock.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/common.c
M src/soc/cavium/common/bdk-coreboot.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/fsp_baytrail/bootblock/bootblock.c
M src/soc/intel/skylake/romstage/romstage.c
M src/southbridge/amd/agesa/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/sb700/early_setup.c
M src/southbridge/nvidia/ck804/early_setup_car.c
22 files changed, 6 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29301/15
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