coreboot-gerrit March 2019

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Change in ...coreboot[master]: google/kukui: Configure AP_IN_SLEEP_L correctly.
by You-Cheng Syu (Code Review) 09 Apr '19

09 Apr '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32120 Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly. ...................................................................... google/kukui: Configure AP_IN_SLEEP_L correctly. This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM can control it. BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0. Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32120/1 diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335..1193bb3 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -32,8 +32,7 @@ setup_chromeos_gpios(); - /* Declare we are in S0 */ - gpio_output(AP_IN_SLEEP_L, 1); + gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); -- To view, visit https://review.coreboot.org/c/coreboot/+/32120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Gerrit-Change-Number: 32120 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: arch/x86/smbios: Reference type 7
by Patrick Rudolph (Code Review) 09 Apr '19

09 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32132 Change subject: arch/x86/smbios: Reference type 7 ...................................................................... arch/x86/smbios: Reference type 7 Fill in the handle to cache entries of type 7 in the type 4 structure. Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 24 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/32132/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index be024c16..68fca21 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -694,10 +694,12 @@ * @param current Pointer to memory address to write the tables to * @param handle Pointer to the handle for the tables * @param max_struct_size Pointer to maximum struct size + * @param type4 Pointer to SMBIOS type 4 structure */ static int smbios_write_type7_cache_parameters(unsigned long *current, int *handle, - int *max_struct_size) + int *max_struct_size, + struct smbios_type4 *type4) { struct cpuid_result res; unsigned int cnt = 0; @@ -730,6 +732,7 @@ while (1) { enum smbios_cache_associativity associativity; enum smbios_cache_type type; + const int h = (*handle)++; res = cpuid_ext(leaf, cnt++); @@ -766,9 +769,23 @@ else associativity = smbios_cache_associativity(assoc); - update_max(len, *max_struct_size, smbios_write_type7(current, - *handle++, level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, - associativity, type, cache_size, cache_size)); + update_max(len, *max_struct_size, smbios_write_type7(current, h, + level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, associativity, + type, cache_size, cache_size)); + + if (type4) { + switch (level) { + case 1: + type4->l1_cache_handle = h; + break; + case 2: + type4->l2_cache_handle = h; + break; + case 3: + type4->l3_cache_handle = h; + break; + } + } }; return len; @@ -945,10 +962,12 @@ handle++; update_max(len, max_struct_size, smbios_write_type3(&current, handle++)); + + struct smbios_type4 *type4 = (struct smbios_type4 *)current; update_max(len, max_struct_size, smbios_write_type4(&current, handle++)); smbios_write_type7_cache_parameters(&current, &handle, - &max_struct_size); + &max_struct_size, type4); update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); if (CONFIG(ELOG)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Gerrit-Change-Number: 32132 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: arch/x86/smbios: Add type 7
by Patrick Rudolph (Code Review) 09 Apr '19

09 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32131 Change subject: arch/x86/smbios: Add type 7 ...................................................................... arch/x86/smbios: Add type 7 The SMBIOS spec requires type 7 to be present. Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the "Deterministic Cache Parameters" as available on Intel and AMD. As CPUID only provides partial information on caches, some fields are set to unknown. The following fields are supported: * Cache Level * Cache Size * Cache Type * Cache Ways of Associativity Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 256 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32131/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cb59df..be024c16 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -34,6 +34,14 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif +#define update_max(len, max_len, stmt) \ + do { \ + int tmp = stmt; \ + \ + max_len = MAX(max_len, tmp); \ + len += tmp; \ + } while (0) + static u8 smbios_checksum(u8 *p, u32 length) { u8 ret = 0; @@ -580,6 +588,192 @@ return len; } +/* + * Write SMBIOS type 7. + * Fill in some fields with constant values, as gathering the information + * from CPUID is impossible. + */ +static int +smbios_write_type7(unsigned long *current, + const int handle, + const u8 level, + const u8 sram_type, + const enum smbios_cache_associativity associativity, + const enum smbios_cache_type type, + const size_t max_cache_size, + const size_t cache_size) +{ + struct smbios_type7 *t = (struct smbios_type7 *)*current; + int len = sizeof(struct smbios_type7); + static size_t cnt = 0; + char buf[8]; + + memset(t, 0, sizeof(struct smbios_type7)); + t->type = SMBIOS_CACHE_INFORMATION; + t->handle = handle; + t->length = len - 2; + + snprintf(buf, sizeof(buf), "CACHE%x", cnt++); + t->socket_designation = smbios_add_string(t->eos, buf); + + /* Cache level, Internal, Enabled, Mode Varies with Memory Address */ + t->cache_configuration = ((level & 7) << 0) | (1 << 7) | (2 << 8); + + if (max_cache_size < (32 * KiB)) { + t->max_cache_size = max_cache_size; + t->max_cache_size2 = t->max_cache_size; + } else if (max_cache_size < (0x7fff * 64 * KiB)) { + t->max_cache_size = (max_cache_size / (64 * KiB)) | (1 << 15); + t->max_cache_size2 = (max_cache_size / (64 * KiB)) | (1 << 31); + } else { + t->max_cache_size = 0xffff; + t->max_cache_size2 = (max_cache_size / (64 * KiB)) | (1 << 31); + } + + if (cache_size < (32 * KiB)) { + t->installed_size = cache_size; + t->installed_size2 = t->installed_size; + } else if (cache_size < (0x7fff * 64 * KiB)) { + t->installed_size = (cache_size / (64 * KiB)) | (1 << 15); + t->installed_size2 = (cache_size / (64 * KiB)) | (1 << 31); + } else { + t->installed_size = 0xffff; + t->installed_size2 = (cache_size / (64 * KiB)) | (1 << 31); + } + + t->associativity = associativity; + t->supported_sram_type = sram_type; + t->cache_speed = 0; //Unknown + t->error_correction_type = SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; + t->system_cache_type = type; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +/* Convert the associativity as integer to the SMBIOS enum if available */ +static enum smbios_cache_associativity +smbios_cache_associativity(const u8 num) +{ + switch (num) { + case 1: + return SMBIOS_CACHE_ASSOCIATIVITY_DIRECT; + case 2: + return SMBIOS_CACHE_ASSOCIATIVITY_2WAY; + case 4: + return SMBIOS_CACHE_ASSOCIATIVITY_4WAY; + case 8: + return SMBIOS_CACHE_ASSOCIATIVITY_8WAY; + case 12: + return SMBIOS_CACHE_ASSOCIATIVITY_12WAY; + case 16: + return SMBIOS_CACHE_ASSOCIATIVITY_16WAY; + case 20: + return SMBIOS_CACHE_ASSOCIATIVITY_20WAY; + case 24: + return SMBIOS_CACHE_ASSOCIATIVITY_24WAY; + case 32: + return SMBIOS_CACHE_ASSOCIATIVITY_32WAY; + case 48: + return SMBIOS_CACHE_ASSOCIATIVITY_48WAY; + case 64: + return SMBIOS_CACHE_ASSOCIATIVITY_64WAY; + case 0xff: + return SMBIOS_CACHE_ASSOCIATIVITY_FULL; + default: + return SMBIOS_CACHE_ASSOCIATIVITY_UNKNOWN; + }; + +} + +/* + * Parse the "Deterministic Cache Parameters" as provided by Intel in + * leaf 4 or AMD in extended leaf 0x8000001d. + * + * @param current Pointer to memory address to write the tables to + * @param handle Pointer to the handle for the tables + * @param max_struct_size Pointer to maximum struct size + */ +static int smbios_write_type7_cache_parameters(unsigned long *current, + int *handle, + int *max_struct_size) +{ + struct cpuid_result res; + unsigned int cnt = 0; + int len = 0; + u32 leaf; + + if (!cpu_have_cpuid()) + return len; + + if (cpu_is_intel()) { + res = cpuid(0); + if (res.eax < 4) + return len; + leaf = 4; + } else if (cpu_is_amd()) { + res = cpuid(0x80000000); + if (res.eax < 0x80000001) + return len; + + res = cpuid(0x80000001); + if (!(res.ecx & (1 << 22))) + return len; + + leaf = 0x8000001d; + } else { + printk(BIOS_DEBUG, "SMBIOS: Unknown CPU\n"); + return len; + } + + while (1) { + enum smbios_cache_associativity associativity; + enum smbios_cache_type type; + + res = cpuid_ext(leaf, cnt++); + + const size_t cache_type = res.eax & 0x1f; + const size_t level = (res.eax >> 5) & 0x7; + const size_t assoc = ((res.ebx >> 22) & 0x3ff) + 1; + const size_t partitions = ((res.ebx >> 12) & 0x3ff) + 1; + const size_t cache_line_size = ((res.ebx >> 0) & 0xfff) + 1; + const size_t number_of_sets = res.ecx + 1; + const size_t cache_size = assoc * partitions * cache_line_size * + number_of_sets; + + if (!cache_type) + /* No more caches in the system */ + break; + + switch (cache_type) { + case 1: + type = SMBIOS_CACHE_TYPE_DATA; + break; + case 2: + type = SMBIOS_CACHE_TYPE_INSTRUCTION; + break; + case 3: + type = SMBIOS_CACHE_TYPE_UNIFIED; + break; + default: + type = SMBIOS_CACHE_TYPE_UNKNOWN; + break; + } + + if (res.eax & (1 << 9)) + associativity = SMBIOS_CACHE_ASSOCIATIVITY_FULL; + else + associativity = smbios_cache_associativity(assoc); + + update_max(len, *max_struct_size, smbios_write_type7(current, + *handle++, level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, + associativity, type, cache_size, cache_size)); + }; + + return len; +} + static int smbios_write_type11(unsigned long *current, int *handle) { struct smbios_type11 *t = (struct smbios_type11 *)*current; @@ -726,14 +920,6 @@ return len; } -#define update_max(len, max_len, stmt) \ - do { \ - int tmp = stmt; \ - \ - max_len = MAX(max_len, tmp); \ - len += tmp; \ - } while (0) - unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; @@ -761,6 +947,8 @@ handle++)); update_max(len, max_struct_size, smbios_write_type4(&current, handle++)); + smbios_write_type7_cache_parameters(&current, &handle, + &max_struct_size); update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); if (CONFIG(ELOG)) diff --git a/src/include/smbios.h b/src/include/smbios.h index af83bfe..c9deca5 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -393,6 +393,66 @@ u8 eos[2]; } __packed; +#define SMBIOS_CACHE_SRAM_TYPE_OTHER (1 << 0) +#define SMBIOS_CACHE_SRAM_TYPE_UNKNOWN (1 << 1) +#define SMBIOS_CACHE_SRAM_TYPE_NON_BURST (1 << 2) +#define SMBIOS_CACHE_SRAM_TYPE_BURST (1 << 3) +#define SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST (1 << 4) +#define SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS (1 << 5) +#define SMBIOS_CACHE_SRAM_TYPE_ASYNCHRONOUS (1 << 6) + +enum smbios_cache_error_corr { + SMBIOS_CACHE_ERROR_CORRECTION_OTHER = 0, + SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN, + SMBIOS_CACHE_ERROR_CORRECTION_NONE, + SMBIOS_CACHE_ERROR_CORRECTION_PARITY, + SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT, + SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT, +}; + +enum smbios_cache_type { + SMBIOS_CACHE_TYPE_OTHER = 0, + SMBIOS_CACHE_TYPE_UNKNOWN, + SMBIOS_CACHE_TYPE_INSTRUCTION, + SMBIOS_CACHE_TYPE_DATA, + SMBIOS_CACHE_TYPE_UNIFIED, +}; + +enum smbios_cache_associativity { + SMBIOS_CACHE_ASSOCIATIVITY_OTHER = 0, + SMBIOS_CACHE_ASSOCIATIVITY_UNKNOWN, + SMBIOS_CACHE_ASSOCIATIVITY_DIRECT, + SMBIOS_CACHE_ASSOCIATIVITY_2WAY, + SMBIOS_CACHE_ASSOCIATIVITY_4WAY, + SMBIOS_CACHE_ASSOCIATIVITY_FULL, + SMBIOS_CACHE_ASSOCIATIVITY_8WAY, + SMBIOS_CACHE_ASSOCIATIVITY_16WAY, + SMBIOS_CACHE_ASSOCIATIVITY_12WAY, + SMBIOS_CACHE_ASSOCIATIVITY_24WAY, + SMBIOS_CACHE_ASSOCIATIVITY_32WAY, + SMBIOS_CACHE_ASSOCIATIVITY_48WAY, + SMBIOS_CACHE_ASSOCIATIVITY_64WAY, + SMBIOS_CACHE_ASSOCIATIVITY_20WAY, +}; + +struct smbios_type7 { + u8 type; + u8 length; + u16 handle; + u8 socket_designation; + u16 cache_configuration; + u16 max_cache_size; + u16 installed_size; + u16 supported_sram_type; + u8 cache_speed; + u8 error_correction_type; + u8 system_cache_type; + u8 associativity; + u32 max_cache_size2; + u32 installed_size2; + u8 eos[2]; +} __packed; + struct smbios_type11 { u8 type; u8 length; -- To view, visit https://review.coreboot.org/c/coreboot/+/32131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Gerrit-Change-Number: 32131 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 27

Change in ...coreboot[master]: arch/x86/cpu: Add functions to determine CPU vendor
by Patrick Rudolph (Code Review) 09 Apr '19

09 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32130 Change subject: arch/x86/cpu: Add functions to determine CPU vendor ...................................................................... arch/x86/cpu: Add functions to determine CPU vendor Add two functions to determine if CPU is made by a specific vendor. Use Kconfig symbols and CPUID to determine the CPU vendor. Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32130/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 80d4d0d..e82df00 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -196,6 +196,36 @@ } } +bool cpu_is_amd(void) +{ + if (CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI)) + return true; + else if (CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON)) + return false; + else if (cpu_have_cpuid()) { + struct device cpu; + identify_cpu(&cpu); + return cpu.vendor == X86_VENDOR_AMD; + } + + return false; +} + +bool cpu_is_intel(void) +{ + if (CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON)) + return true; + else if (CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI)) + return false; + else if (cpu_have_cpuid()) { + struct device cpu; + identify_cpu(&cpu); + return cpu.vendor == X86_VENDOR_INTEL; + } + + return false; +} + struct cpu_driver *find_cpu_driver(struct device *cpu) { struct cpu_driver *driver; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b40dd1b..ce4ae11 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -217,6 +217,10 @@ ci = cpu_info(); return ci->index; } + +bool cpu_is_amd(void); +bool cpu_is_intel(void); + #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases -- To view, visit https://review.coreboot.org/c/coreboot/+/32130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f Gerrit-Change-Number: 32130 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Qcs405: Add SPI chip select assert/de-assert in claim/release bus
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31177 Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ...................................................................... Qcs405: Add SPI chip select assert/de-assert in claim/release bus Add SPI chip select assert/de-assert in claim/release bus. Configure IO in SPI write function and the keep QUP into run state. Add timeout condition in both SPI write and read functions. Change-Id: Ib8fce5f1890ed3693ee0620cbc0e665d82ce3204 Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/spi.c 3 files changed, 97 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31177/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 41f74be..bccefa7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -63,6 +63,16 @@ }; struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + //.m = 1, + //.n = 2, + //.d_2 = 4, + }, + { .hz = 19200000, .hw_ctl = 0x0, @@ -210,7 +220,7 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); - clock_configure(blsp1_qup4_spi_clk, spi_cfg, 50000000, + clock_configure(blsp1_qup4_spi_clk, spi_cfg, 1000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP1_QUP4_SPI_APPS_CBCR)); clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 211b44e..5c1c429 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -71,6 +71,8 @@ #define OUTPUT_FIFO_FULL (1<<6) #define INPUT_FIFO_NOT_EMPTY (1<<5) #define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) #define INPUT_SERVICE_FLAG (1<<9) #define OUTPUT_SERVICE_FLAG (1<<8) #define QUP_UNPACK_EN (1<<14) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index bd88462..1038881 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -36,6 +36,7 @@ #include <stdlib.h> #include <string.h> #include <spi_flash.h> +#include <timer.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ @@ -320,47 +321,6 @@ return SUCCESS; } -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int ret; - - ret = spi_hw_init(ds); - if (ret) - return -EIO; - switch(slave->bus) { - case 5: - - gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - - break; - case 4: - gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - break; - default: - printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); - break; - } - - - return SUCCESS; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(ds); - ds->initialized = 0; -} - static void write_force_cs(const struct spi_slave *slave, int assert) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -380,6 +340,56 @@ return; } + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 4: + gpio_configure(GPIO(37), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN + gpio_configure(GPIO(38), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out + gpio_configure(GPIO(117), 2, + GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out + gpio_configure(GPIO(118), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out + + break; + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + write_force_cs(slave, 1); + + + return SUCCESS; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; +} + /* * Function to write data to OUTPUT FIFO */ @@ -465,6 +475,7 @@ unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; /* Configure no of bytes to read */ state_config = config_spi_state(ds, QUP_STATE_RESET); @@ -505,6 +516,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_INPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -542,15 +565,18 @@ uint32_t val; unsigned int i; unsigned int write_len = bytes; - unsigned int read_len = 3; //bytes; hack for now + unsigned int read_len = bytes; //hack for now unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; state_config = config_spi_state(ds, QUP_STATE_RESET); if (state_config) return state_config; + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); /* No of bytes to be written in Output FIFO */ write32(ds->regs->qup_mx_output_count, bytes); write32(ds->regs->qup_mx_input_count, bytes); @@ -558,9 +584,6 @@ if (state_config) return state_config; - /* Configure input and output enable */ - enable_io_config(ds, write_len, read_len); - /* * read_len considered to ensure that we read the dummy data for the * write we performed. This is needed to ensure with WR-RD transaction @@ -620,6 +643,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_OUTPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -639,8 +674,10 @@ length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; ret = __blsp_spi_write(ds, cmd_buffer, length); - if (ret != SUCCESS) + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success \n"); return ret; + } cmd_buffer += length; bytes -= length; @@ -670,8 +707,6 @@ if (ret != SUCCESS) return ret; - write_force_cs(slave, 1); - if (dout != NULL) { ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); if (ret != SUCCESS) @@ -685,7 +720,6 @@ } out: - write_force_cs(slave, 0); /* * Put the SPI Core back in the Reset State @@ -750,7 +784,7 @@ .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - //.xfer = spi_ctrlr_xfer, + .xfer = spi_ctrlr_xfer, .xfer_vector = xfer_vectors, .max_xfer_size = MAX_PACKET_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8fce5f1890ed3693ee0620cbc0e665d82ce3204 Gerrit-Change-Number: 31177 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: qcs405: Reduce the reserved memory size
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31176 Change subject: qcs405: Reduce the reserved memory size ...................................................................... qcs405: Reduce the reserved memory size Lets us reserve only for ATF use and give the rest back to Kernel Change-Id: Ibe576b4934e9aa3e5bf1bda71d65c496b42e10f0 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31176/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 46d4673..ace2e70 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -56,7 +56,7 @@ DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + REGION(dram_reserved, 0x86000000, 0x400000, 4096) POSTRAM_CBFS_CACHE(0x9F800000, 384K) RAMSTAGE(0x9F860000, 128K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe576b4934e9aa3e5bf1bda71d65c496b42e10f0 Gerrit-Change-Number: 31176 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: Qcs405: Add SPI chip select assert/de-assert in claim/release bus
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31142 Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ...................................................................... Qcs405: Add SPI chip select assert/de-assert in claim/release bus Add SPI chip select assert/de-assert in claim/release bus. Configure IO in SPI write function and the keep QUP into run state. Add timeout condition in both SPI write and read functions. Change-Id: Iaeb9046f6c4f89c0c1bfa72374b5134eafd1a9dd Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/spi.c 3 files changed, 97 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31142/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 41f74be..bccefa7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -63,6 +63,16 @@ }; struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + //.m = 1, + //.n = 2, + //.d_2 = 4, + }, + { .hz = 19200000, .hw_ctl = 0x0, @@ -210,7 +220,7 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); - clock_configure(blsp1_qup4_spi_clk, spi_cfg, 50000000, + clock_configure(blsp1_qup4_spi_clk, spi_cfg, 1000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP1_QUP4_SPI_APPS_CBCR)); clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 211b44e..5c1c429 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -71,6 +71,8 @@ #define OUTPUT_FIFO_FULL (1<<6) #define INPUT_FIFO_NOT_EMPTY (1<<5) #define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) #define INPUT_SERVICE_FLAG (1<<9) #define OUTPUT_SERVICE_FLAG (1<<8) #define QUP_UNPACK_EN (1<<14) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index bd88462..1038881 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -36,6 +36,7 @@ #include <stdlib.h> #include <string.h> #include <spi_flash.h> +#include <timer.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ @@ -320,47 +321,6 @@ return SUCCESS; } -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int ret; - - ret = spi_hw_init(ds); - if (ret) - return -EIO; - switch(slave->bus) { - case 5: - - gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - - break; - case 4: - gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - break; - default: - printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); - break; - } - - - return SUCCESS; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(ds); - ds->initialized = 0; -} - static void write_force_cs(const struct spi_slave *slave, int assert) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -380,6 +340,56 @@ return; } + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 4: + gpio_configure(GPIO(37), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN + gpio_configure(GPIO(38), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out + gpio_configure(GPIO(117), 2, + GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out + gpio_configure(GPIO(118), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out + + break; + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + write_force_cs(slave, 1); + + + return SUCCESS; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; +} + /* * Function to write data to OUTPUT FIFO */ @@ -465,6 +475,7 @@ unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; /* Configure no of bytes to read */ state_config = config_spi_state(ds, QUP_STATE_RESET); @@ -505,6 +516,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_INPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -542,15 +565,18 @@ uint32_t val; unsigned int i; unsigned int write_len = bytes; - unsigned int read_len = 3; //bytes; hack for now + unsigned int read_len = bytes; //hack for now unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; state_config = config_spi_state(ds, QUP_STATE_RESET); if (state_config) return state_config; + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); /* No of bytes to be written in Output FIFO */ write32(ds->regs->qup_mx_output_count, bytes); write32(ds->regs->qup_mx_input_count, bytes); @@ -558,9 +584,6 @@ if (state_config) return state_config; - /* Configure input and output enable */ - enable_io_config(ds, write_len, read_len); - /* * read_len considered to ensure that we read the dummy data for the * write we performed. This is needed to ensure with WR-RD transaction @@ -620,6 +643,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_OUTPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -639,8 +674,10 @@ length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; ret = __blsp_spi_write(ds, cmd_buffer, length); - if (ret != SUCCESS) + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success \n"); return ret; + } cmd_buffer += length; bytes -= length; @@ -670,8 +707,6 @@ if (ret != SUCCESS) return ret; - write_force_cs(slave, 1); - if (dout != NULL) { ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); if (ret != SUCCESS) @@ -685,7 +720,6 @@ } out: - write_force_cs(slave, 0); /* * Put the SPI Core back in the Reset State @@ -750,7 +784,7 @@ .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - //.xfer = spi_ctrlr_xfer, + .xfer = spi_ctrlr_xfer, .xfer_vector = xfer_vectors, .max_xfer_size = MAX_PACKET_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeb9046f6c4f89c0c1bfa72374b5134eafd1a9dd Gerrit-Change-Number: 31142 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: mistral: qcs405: Updated the layout info as in Gale
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30902 Change subject: mistral: qcs405: Updated the layout info as in Gale ...................................................................... mistral: qcs405: Updated the layout info as in Gale Changed the Mistral's layout as in Gale. Change-Id: I61a82bd8dc6a2f86b72beb8efedaee35897fd66f Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 24 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30902/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index e8b9978..a9bdd7b 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -1,52 +1,33 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2018, The Linux Foundation. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 and -## only version 2 as published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - FLASH@0x0 0x800000 { - WP_RO@0x0 0x300000 { - RO_SECTION@0x0 0x2FE000 { - BOOTBLOCK@0 248K - COREBOOT(CBFS)@0x3E000 0x1E0000 - FMAP@0x21E000 0x1000 - GBB@0x21F000 0xDEF00 - RO_FRID@0x2FDF00 0x100 + WP_RO@0x0 0x400000 { + RO_SECTION@0x0 0x3e0000 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0x2e0000 + FMAP@0x300000 0x1000 + GBB@0x301000 0xdef00 + RO_FRID@0x3dff00 0x100 } - RO_VPD@0x2FE000 0x2000 + RO_VPD@0x3e0000 0x20000 } - - RW_NVRAM@0x300000 0x8000 - RW_ELOG@0x308000 0x8000 - RW_VPD@0x310000 0x8000 - RW_CDT@0x318000 0x8000 - - RW_SECTION_A@0x320000 0x268000 { + RW_SECTION_A@0x400000 0x160000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x1E1F00 - RW_FWID_A@0x1E3F00 0x100 - RW_DDR_TRAINING_A@0x1E4000 0x4000 - RW_XBL_BUFFER_A@0x1E8000 0x4000 + FW_MAIN_A(CBFS)@0x2000 0x14df00 + RW_FWID_A@0x14ff00 0x100 + RW_SHARED@0x150000 0x10000 { + SHARED_DATA@0x0 0x10000 + } } - - RW_SHARED@0x588000 0x10000 { - SHARED_DATA@0x0 0x10000 + RW_GPT@0x560000 0x20000 { + RW_GPT_PRIMARY@0x0 0x10000 + RW_GPT_SECONDARY@0x10000 0x10000 } - - RW_SECTION_B@0x598000 0x268000 { + RW_SECTION_B@0x580000 0x160000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x1E1F00 - RW_FWID_B@0x1E3F00 0x100 - RW_DDR_TRAINING_B@0x1E4000 0x4000 - RW_XBL_BUFFER_B@0x1E8000 0x4000 + FW_MAIN_B(CBFS)@0x2000 0x14df00 + RW_FWID_B@0x14ff00 0x100 } + RW_VPD@0x6e0000 0x8000 + RW_ELOG@0x6e8000 0x8000 + RW_NVRAM@0x6f0000 0x10000 + RW_LEGACY(CBFS)@0x700000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/30902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61a82bd8dc6a2f86b72beb8efedaee35897fd66f Gerrit-Change-Number: 30902 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: nb/intel/pineview: Correct unsigned integer check in msbpos
by Jacob Garber (Code Review) 08 Apr '19

08 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32054 Change subject: nb/intel/pineview: Correct unsigned integer check in msbpos ...................................................................... nb/intel/pineview: Correct unsigned integer check in msbpos The check i >= 0 is always true for an unsigned integer, causing msbpos(0) to hang. We correct it to i != 0. Note this has no material change since the code guards against finding the msb of 0 anyway, but it fixes Coverity CID 1347386. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/32054/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index fa5122a..4f9a0b4 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -336,7 +336,7 @@ static u8 msbpos(u8 val) //Reverse { u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); + for (i = 7; (i != 0) && ((val & (1 << i)) == 0); i--); return i; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb Gerrit-Change-Number: 32054 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: soc/intel/baytrail: Correct array bounds check
by Jacob Garber (Code Review) 08 Apr '19

08 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32125 Change subject: soc/intel/baytrail: Correct array bounds check ...................................................................... soc/intel/baytrail: Correct array bounds check If `gms == ARRAY_SIZE(gms_size_map)`, then we will have an out of bounds read. Fix the check to exclude this case. This was partially fixed in 04f68c1 (baytrail: fix range check). Found-by: Coverity Scan, CID 1229677 (OVERRUN) Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I8c8cd59df49beea066b46cde3cf00237816aff33 --- M src/soc/intel/baytrail/gfx.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32125/1 diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 73c0d15..eaec46b 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -50,7 +50,7 @@ gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK; gms >>= 3; - if (gms > ARRAY_SIZE(gms_size_map)) + if (gms >= ARRAY_SIZE(gms_size_map)) return; gmsize = gms_size_map[gms]; -- To view, visit https://review.coreboot.org/c/coreboot/+/32125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c8cd59df49beea066b46cde3cf00237816aff33 Gerrit-Change-Number: 32125 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019