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Change in ...coreboot[master]: sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 16 Apr '19

16 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32037 Change subject: sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc D src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/bd82x6x/pch.h 5 files changed, 3 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32037/1 diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 6112c76..8ddc156 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,6 +28,7 @@ #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmclib.h> static void early_pch_reset_pmcon(void) { diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1396a63..dae3c32 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -29,6 +29,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 24d7e2d..7ce3da7 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,7 +38,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c early_pch_common.c +romstage-y += early_spi.c romstage-y += early_rcba.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -47,6 +47,4 @@ romstage-y += early_me_mrc.c early_usb_mrc.c endif -ramstage-y += early_pch_common.c - endif diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c deleted file mode 100644 index 2e9ad7f..0000000 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include "pch.h" -#include <arch/acpi.h> -#include <console/console.h> - -#if ENV_ROMSTAGE -int southbridge_detect_s3_resume(void) -{ - u32 pm1_cnt; - u16 pm1_sts; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - return 1; - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } - - return 0; -} -#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 0097e15..21b6031 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,7 +76,6 @@ void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); -int southbridge_detect_s3_resume(void); void early_pch_init(void); struct southbridge_usb_port -- To view, visit https://review.coreboot.org/c/coreboot/+/32037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb Gerrit-Change-Number: 32037 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 13 Apr '19

13 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32041 Change subject: sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/Makefile.inc D src/southbridge/intel/i82801gx/early_lpc.c M src/southbridge/intel/i82801gx/i82801gx.h 21 files changed, 19 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32041/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 479ab59..c524446 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> static void ich7_enable_lpc(void) { diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 8cf3487..de73d01 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -23,6 +23,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index ffb3bf9..ae19526 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -32,6 +32,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <arch/cpu.h> diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 6295a53..8ce5979 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -27,6 +27,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 47a7d40..01c6edd 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -22,6 +22,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8720f/it8720f.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 423b4e8..cef208a 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -28,6 +28,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include "option_table.h" static void setup_special_ich7_gpios(void) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index b2d4bb4..fe3a269 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -28,6 +28,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 7c03399..e20fb7a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 1257fa5..eb62548 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -31,6 +31,7 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> +#include <southbridge/intel/common/pmclib.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 18a7721..ba9a812 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -26,6 +26,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 345e4b7..2d6e916 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -23,6 +23,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 52432a0..a419881 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index f377c89..e410351 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 39e0ed5..8391343 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -33,6 +33,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include "dock.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 45cd9ec..30edfa3 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -33,6 +33,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include "dock.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index dbc4b6c..819c666 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include "option_table.h" static void ich7_enable_lpc(void) diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index cf1da63..7f4473c 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -27,6 +27,7 @@ #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <cpu/intel/romstage.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index d4615fa..a7d65c5 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -25,6 +25,7 @@ select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 290794b..b72ca23 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -34,6 +34,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-y += early_smbus.c early_lpc.c +romstage-y += early_smbus.c endif diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c deleted file mode 100644 index a52fb85..0000000 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <arch/acpi.h> -#include "i82801gx.h" - -int southbridge_detect_s3_resume(void) -{ - u32 reg32; - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - return 1; - } - } - - return 0; -} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1e7dfdb..3db5d49 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -48,7 +48,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -int southbridge_detect_s3_resume(void); #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70 Gerrit-Change-Number: 32041 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: sb/intel/common: Add common detect_s3_resume
by Patrick Rudolph (Code Review) 13 Apr '19

13 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32036 Change subject: sb/intel/common: Add common detect_s3_resume ...................................................................... sb/intel/common: Add common detect_s3_resume Add a common detect_s3_resume function. Will be used by other southbridge code. TODO: Merge with soc/intel/common/*/pmclib Change-Id: I88023af522afac8164f068b0fbe0eac601aef702 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/pmclib.c A src/southbridge/intel/common/pmclib.h 4 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32036/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 6a96277..308c4f4 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -6,6 +6,9 @@ bool select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_PMCLIB + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3ad7924..ac339a2 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -25,6 +25,8 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c new file mode 100644 index 0000000..198562b --- /dev/null +++ b/src/southbridge/intel/common/pmclib.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/acpi.h> +#include <console/console.h> + +#include "pmclib.h" +#include "pmbase.h" +#include "pmutil.h" + +int southbridge_detect_s3_resume(void) +{ + u32 pm1_cnt; + u16 pm1_sts; + int is_s3 = 0; + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = read_pmbase16(PM1_STS); + if (pm1_sts & WAK_STS) { + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = read_pmbase32(PM1_CNT); + if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { + /* Clear SLP_TYPE. */ + write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); + is_s3 = 1; + } + } + if (is_s3) { + if (!acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n"); + return 0; + } + + printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n"); + } + + return is_s3; +} diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h new file mode 100644 index 0000000..7de5f97 --- /dev/null +++ b/src/southbridge/intel/common/pmclib.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INTEL_COMMON_PMCLIB_H +#define INTEL_COMMON_PMCLIB_H + +/* + * Returns 1 if platform was in ACPI S3 power state and CONFIG(ACPI_RESUME) + * is enabled else returns 0. + */ +int southbridge_detect_s3_resume(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88023af522afac8164f068b0fbe0eac601aef702 Gerrit-Change-Number: 32036 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Update SRAT revision number
by HAOUAS Elyes (Code Review) 13 Apr '19

13 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31565 Change subject: src/arch/x86/acpi.c: Update SRAT revision number ...................................................................... src/arch/x86/acpi.c: Update SRAT revision number We currently use ACPI v3.0, so the SRAT revision number is "2". Change-Id: I14311029c887a2260c3a93d0b7fca6e8d546edd0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31565/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6396877..fc9dfe1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1383,8 +1383,8 @@ return 4; case SSDT: /* ACPI 3.0 upto 6.3: 2 */ return 2; - case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ - return 1; /* TODO Should probably be upgraded to 2 */ + case SRAT: /* ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ + return 2; case DMAR: return 1; case SLIT: /* ACPI 2.0 upto 6.3: 1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14311029c887a2260c3a93d0b7fca6e8d546edd0 Gerrit-Change-Number: 31565 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/intelmetool: Add support for Apollolake
by Felix Singer (Code Review) 12 Apr '19

12 Apr '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31791 Change subject: util/intelmetool: Add support for Apollolake ...................................................................... util/intelmetool: Add support for Apollolake Change-Id: I4f8ef88d2fcc4bff4e7f56fbe5199fb534ae66d1 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M util/intelmetool/intelmetool.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31791/1 diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index 4c4dfcd..4d1103f 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -305,7 +305,8 @@ ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_2) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2) || \ - ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP)) + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP) || \ + ((x) == PCI_DEVICE_ID_INTEL_APL)) #define BOOTGUARD_DISABLED 0x400000000 #define BOOTGUARD_ENABLED_VERIFIED_MODE 0x100000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/31791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f8ef88d2fcc4bff4e7f56fbe5199fb534ae66d1 Gerrit-Change-Number: 31791 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/genbuild_h: don't expect `git log` not printing the signature cruft
by Sergey Alirzaev (Code Review) 12 Apr '19

12 Apr '19

Sergey Alirzaev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32129 Change subject: util/genbuild_h: don't expect `git log` not printing the signature cruft ...................................................................... util/genbuild_h: don't expect `git log` not printing the signature cruft Explicitly ask it not to. Signed-off-by: Sergey Alirzaev <zl29ah(a)gmail.com> Change-Id: I102ecc79bb649a67661c3d22988453dc7741acda --- M util/genbuild_h/genbuild_h.sh 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/32129/1 diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index 340de35..5c45b2b 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -27,9 +27,9 @@ TIMESOURCE="fixed" DATE=0 elif [ "$(git rev-parse --is-inside-work-tree 2>/dev/null)" = "true" ]; then - GITREV=$(LANG= git log -1 --format=format:%h) + GITREV=$(LANG= git log --no-show-signature -1 --format=format:%h) TIMESOURCE=git - DATE=$(git log --pretty=format:%ct -1) + DATE=$(git log --no-show-signature --pretty=format:%ct -1) else GITREV=Unknown TIMESOURCE="date" -- To view, visit https://review.coreboot.org/c/coreboot/+/32129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I102ecc79bb649a67661c3d22988453dc7741acda Gerrit-Change-Number: 32129 Gerrit-PatchSet: 1 Gerrit-Owner: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: option table: Don't pad string entries with garbage
by Thomas Heijligen (Code Review) 11 Apr '19

11 Apr '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31348 to review the following change. Change subject: option table: Don't pad string entries with garbage ...................................................................... option table: Don't pad string entries with garbage set_option_with() expects a buffer of the exact size of the option. Change-Id: I21332394f88cf2daa4f733a544627d6d3c6ef26c Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/drivers/options.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31348/1 diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 70c2b17..2b0a42e 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -357,7 +357,11 @@ *(u64*)raw = strtoull(value, NULL, 0); break; case 's': - raw = strdup(value); + raw = malloc(cmos_entry->length); + if (!raw) + return 1; + memset(raw, 0x00, cmos_entry->length); + strncpy(raw, value, cmos_entry->length); break; case 'e': cmos_enum = lookup_cmos_enum_by_label(option_table, cmos_entry->config_id, value); -- To view, visit https://review.coreboot.org/c/coreboot/+/31348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21332394f88cf2daa4f733a544627d6d3c6ef26c Gerrit-Change-Number: 31348 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: libpayload/storage: Add Apollo Lake AHCI ID
by Thomas Heijligen (Code Review) 11 Apr '19

11 Apr '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31347 to review the following change. Change subject: libpayload/storage: Add Apollo Lake AHCI ID ...................................................................... libpayload/storage: Add Apollo Lake AHCI ID Change-Id: Iee244d0cd7d64934fbfc34778a45e21e97646628 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/drivers/storage/ahci.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31347/1 diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index bb0d37e..6cc3866 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -224,6 +224,7 @@ 0x8086 | 0x1c03 << 16, /* Mobile Cougar Point PCH */ 0x8086 | 0x1e03 << 16, /* Mobile Panther Point PCH */ 0x8086 | 0xa102 << 16, /* Desktop / Mobile-Wks Sunrise Point PCH */ + 0x8086 | 0x5ae3 << 16, /* Apollo Lake */ }; #endif static void ahci_init_pci(pcidev_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee244d0cd7d64934fbfc34778a45e21e97646628 Gerrit-Change-Number: 31347 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/spi: Move M25Pxx commands to spi_winbond.h
by Frans Hendriks (Code Review) 11 Apr '19

11 Apr '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31710 Change subject: drivers/spi: Move M25Pxx commands to spi_winbond.h ...................................................................... drivers/spi: Move M25Pxx commands to spi_winbond.h Move Wnbond M25PXX command values to spi_winbond.h Now the commands value can be used for programming SPI contoller of Intel Braswell, by using including file. Update winbond.c file with coreboot header. BUG=N/A TEST=Facebook FBG-1701 with flashrom Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A src/drivers/spi/spi_winbond.h M src/drivers/spi/winbond.c 2 files changed, 49 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31710/1 diff --git a/src/drivers/spi/spi_winbond.h b/src/drivers/spi/spi_winbond.h new file mode 100644 index 0000000..e21571c --- /dev/null +++ b/src/drivers/spi/spi_winbond.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Winbond specific function */ +/* M25Pxx-specific commands */ +#define CMD_W25_WREN 0x06 /* Write Enable */ +#define CMD_W25_WRDI 0x04 /* Write Disable */ +#define CMD_W25_RDSR 0x05 /* Read Status Register */ +#define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */ +#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */ +#define CMD_W25_READ 0x03 /* Read Data Bytes */ +#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_W25_PP 0x02 /* Page Program */ +#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_W25_RDID 0x9f /* Read ID */ +#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_W25_CE 0xc7 /* Chip Erase */ +#define CMD_W25_DP 0xb9 /* Deep Power-down */ +#define CMD_W25_RES 0xab /* Release from DP and Read Signature */ +#define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile SREG */ + +/* tw: Maximum time to write a flash cell in milliseconds */ +#define WINBOND_FLASH_TIMEOUT 30 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 8bf8fcd..7276ec1 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -1,7 +1,16 @@ /* * Copyright 2008, Network Appliance Inc. - * Author: Jason McMullan <mcmullan <at> netapp.com> - * Licensed under the GPL-2 or later. + * Jason McMullan <mcmullan(a)netapp.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include <console/console.h> @@ -14,26 +23,7 @@ #include <lib.h> #include "spi_flash_internal.h" - -/* M25Pxx-specific commands */ -#define CMD_W25_WREN 0x06 /* Write Enable */ -#define CMD_W25_WRDI 0x04 /* Write Disable */ -#define CMD_W25_RDSR 0x05 /* Read Status Register */ -#define CMD_W25_WRSR 0x01 /* Write Status Register */ -#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */ -#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */ -#define CMD_W25_READ 0x03 /* Read Data Bytes */ -#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_W25_PP 0x02 /* Page Program */ -#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_W25_CE 0xc7 /* Chip Erase */ -#define CMD_W25_DP 0xb9 /* Deep Power-down */ -#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ -#define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile SREG */ - -/* tw: Maximum time to write a flash cell in milliseconds */ -#define WINBOND_FLASH_TIMEOUT 30 +#include "spi_winbond.h" struct winbond_spi_flash_params { uint16_t id; -- To view, visit https://review.coreboot.org/c/coreboot/+/31710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495 Gerrit-Change-Number: 31710 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 11 Apr '19

11 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30993 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Aslo add comments on Read/Write-Once bits. ULBA register is 64bits, so maybe there is a typo on RCBA(0x114) and it should be 0x11b insted. Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M 3rdparty/blobs M src/northbridge/intel/i945/early_init.c 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 16058e5..998982d 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 16058e552279b4884b1f671e7a78752d28abd1cc +Subproject commit 998982d714a08481bb4944f456929be06b5e696f diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 6bfa1c7..70b8152 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -883,10 +883,13 @@ static void ich7_setup_root_complex_topology(void) { - RCBA32(0x104) = 0x00000802; - RCBA32(0x110) = 0x00000001; - RCBA32(0x114) = 0x00000000; - RCBA32(0x118) = 0x00000000; + /* FIXME: ESD [23:16] is R/WO */ + RCBA32(ESD) = 0x00000802; + /* FIXME: ULD [31:16] is R/WO */ + RCBA32(ULD) = 0x00000001; + /* FIXME: ULBA [63:0] is R/WO */ + RCBA32(0x114) = 0x00000000; // RCBA32(0x11b) ? + RCBA32(ULBA) = 0x00000000; } static void ich7_setup_pci_express(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/30993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Gerrit-Change-Number: 30993 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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