coreboot-gerrit March 2019

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Set basename for FSP binaries
by Felix Singer (Code Review) 21 Apr '19

21 Apr '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30930 Change subject: drivers/intel/fsp2_0: Set basename for FSP binaries ...................................................................... drivers/intel/fsp2_0: Set basename for FSP binaries Since there is no standardized naming scheme for the FSP binaries, the option USE_FSP_REPO can't be used on some platforms, because the output filenames differ and the build process awaits "Fsp_*.fd" as filename. As a workaround, add the option -n to SplitFspBin.py, which defines the basename. Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/30930/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8..1d1bae7 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -69,7 +69,7 @@ ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) - python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true -- To view, visit https://review.coreboot.org/c/coreboot/+/30930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Gerrit-Change-Number: 30930 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mb/Kconfig: Fix PCI subsystem IDs
by Kyösti Mälkki (Code Review) 20 Apr '19

20 Apr '19

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32107 to review the following change. Change subject: src/mb/Kconfig: Fix PCI subsystem IDs ...................................................................... src/mb/Kconfig: Fix PCI subsystem IDs Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M util/autoport/bd82x6x.go 4 files changed, 0 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32107/1 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 5fba47a..5e46365 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -40,14 +40,6 @@ string default "GA-H61M-S2PV" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x5001 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1458 - config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c414083..06f296b 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -65,14 +65,6 @@ string default "pci8086,0126.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21cf - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 14f9fb2..b36460d 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -62,14 +62,6 @@ default "pci8086,0106.rom" if BOARD_LENOVO_T530 default "pci8086,0166.rom" if BOARD_LENOVO_W530 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 265cb6f..a97ff1d 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -181,12 +181,6 @@ } KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" - /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. - But most systems don't have any of those. But the config needs to be set - nevertheless. So set it to southbridge subsys/subvendor. */ - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) - ich9GetFlashSize(ctx) DSDTDefines = append(DSDTDefines, -- To view, visit https://review.coreboot.org/c/coreboot/+/32107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Gerrit-Change-Number: 32107 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801ix/sata.c: Add brackets around left shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31410 Change subject: sb/intel/i82801ix/sata.c: Add brackets around left shift ...................................................................... sb/intel/i82801ix/sata.c: Add brackets around left shift Change-Id: I8068d922d12acb4dbff22c231a065151b43f4c2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/sata.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31410/1 diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index e3b7e14..1968694 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -43,7 +43,7 @@ /* Set AHCI access mode. No other ABAR registers should be accessed before this. */ reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; + reg32 |= (1 << 31); write32(abar + 0x04, reg32); /* CAP (HBA Capabilities) : enable power management */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8068d922d12acb4dbff22c231a065151b43f4c2f Gerrit-Change-Number: 31410 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/ibase/mb899/superio_hwm.c: Fix coding style
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31156 Change subject: mb/ibase/mb899/superio_hwm.c: Fix coding style ...................................................................... mb/ibase/mb899/superio_hwm.c: Fix coding style Change-Id: I6ce74a006a5bf461a1f33203a9e5ea37a1bc7d7b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/superio_hwm.c 1 file changed, 62 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31156/1 diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7fb45f9..5e3d5c5 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -29,7 +29,7 @@ #define FAN_CRUISE_CONTROL_THERMAL 2 #define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 +#define FAN_TEMPERATURE_30DEGC 0 #define HWM_BASE 0x290 @@ -52,10 +52,10 @@ // FANIN Target Speed Register // FANIN = 337500 / RPM struct fan_speed fan_speeds[] = { - { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, - { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, - { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, - { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } + {0x3c, 5625}, {0x41, 5192}, {0x47, 4753}, {0x4e, 4326}, + {0x56, 3924}, {0x5f, 3552}, {0x69, 3214}, {0x74, 2909}, + {0x80, 2636}, {0x8d, 2393}, {0x9b, 2177}, {0xaa, 1985}, + {0xba, 1814}, {0xcb, 1662}, {0xdd, 1527}, {0xf0, 1406} }; struct temperature { @@ -64,94 +64,109 @@ }; struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, - { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, - { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, - { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } + {30, 86}, {33, 91}, {36, 96}, {39, 102}, + {42, 107}, {45, 113}, {48, 118}, {51, 123}, + {54, 129}, {57, 134}, {60, 140}, {63, 145}, + {66, 150}, {69, 156}, {72, 161}, {75, 167} }; void hwm_setup(void) { - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; + int cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + int cpufan_speed = FAN_SPEED_5625; + int cpufan_temperature = FAN_TEMPERATURE_30DEGC; + int sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + int sysfan_speed = FAN_SPEED_5625; + int sysfan_temperature = FAN_TEMPERATURE_30DEGC; - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&cpufan_control, "cpufan_cruise_control"); - cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; //get_option(&cpufan_temperature, "cpufan_temperature"); - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); - sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; //get_option(&sysfan_temperature, "sysfan_temperature"); // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset - hwm_bank(0x80); // Default + hwm_bank(0x80); // Default u8 fan_config = 0; // 00 FANOUT is Manual Mode // 01 FANOUT is Thermal Cruise Mode // 10 FANOUT is Fan Speed Cruise Mode switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 4); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 4); + break; } switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 2); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 2); + break; } // This register must be written first hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", - fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + // CPUFANIN target speed + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", - temperatures[cpufan_temperature].deg_celsius, - temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to activation " + "at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + // CPUFANIN target temperature + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); break; } switch (sysfan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", - fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + // SYSFANIN target speed + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", - temperatures[sysfan_temperature].deg_celsius, - temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to activation " + "at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + // SYSFANIN target temperature + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); break; } - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor - hwm_write(0x40, 0x01); // Init, but no SMI# + hwm_write(0x40, 0x01); // Init, but no SMI# } -- To view, visit https://review.coreboot.org/c/coreboot/+/31156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ce74a006a5bf461a1f33203a9e5ea37a1bc7d7b Gerrit-Change-Number: 31156 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/kontron/986lcd-m/mainboard.c: Fix coding style
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31155 Change subject: mb/kontron/986lcd-m/mainboard.c: Fix coding style ...................................................................... mb/kontron/986lcd-m/mainboard.c: Fix coding style Change-Id: I96a1d480c8b618a184c2b5ae08380f45fbd628ec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/986lcd-m/mainboard.c 1 file changed, 66 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31155/1 diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 73d5997..2c796b7 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -44,7 +44,6 @@ #define FAN_SPEED_5625 0 - struct fan_speed { u8 fan_in; u16 fan_speed; @@ -53,10 +52,10 @@ /* FANIN Target Speed Register */ /* FANIN = 337500 / RPM */ struct fan_speed fan_speeds[] = { - { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, - { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, - { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, - { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } + {0x3c, 5625}, {0x41, 5192}, {0x47, 4753}, {0x4e, 4326}, + {0x56, 3924}, {0x5f, 3552}, {0x69, 3214}, {0x74, 2909}, + {0x80, 2636}, {0x8d, 2393}, {0x9b, 2177}, {0xaa, 1985}, + {0xba, 1814}, {0xcb, 1662}, {0xdd, 1527}, {0xf0, 1406} }; struct temperature { @@ -65,89 +64,108 @@ }; struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, - { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, - { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, - { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } + {30, 86}, {33, 91}, {36, 96}, {39, 102}, + {42, 107}, {45, 113}, {48, 118}, {51, 123}, + {54, 129}, {57, 134}, {60, 140}, {63, 145}, + {66, 150}, {69, 156}, {72, 161}, {75, 167} }; static void hwm_setup(void) { - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; + int cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + int cpufan_speed = FAN_SPEED_5625; + int cpufan_temperature = 0; + int cpufan_temperature = 0; - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + int sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + int sysfan_speed = FAN_SPEED_5625; + int sysfan_temperature = 0; + get_option(&cpufan_control, "cpufan_cruise_control"); - cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); - sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); hwm_bank(0); - hwm_write(0x59, 0x20); /* Diode Selection */ - hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ + hwm_write(0x59, 0x20); /* Diode Selection */ + hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ hwm_bank(4); - hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ - hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ - hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ + hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ + hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ + hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ - hwm_bank(0x80); /* Default */ + hwm_bank(0x80); /* Default */ u8 fan_config = 0; /* 00 FANOUT is Manual Mode */ /* 01 FANOUT is Thermal Cruise Mode */ /* 10 FANOUT is Fan Speed Cruise Mode */ switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 4); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 4); + break; } switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 2); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 2); + break; } /* This register must be written first */ hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", - fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + /* CPUFANIN target speed */ + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", - temperatures[cpufan_temperature].deg_celsius, - temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to activation " + "at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + /* CPUFANIN target temperature */ + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); break; } switch (sysfan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", - fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + /* SYSFANIN target speed */ + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", - temperatures[sysfan_temperature].deg_celsius, - temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to activation " + "at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + /* SYSFANIN target temperature */ + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); break; } - hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ - hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ + hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ + hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ - hwm_write(0x47, 0xaf); /* FAN divisor register */ - hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ + hwm_write(0x47, 0xaf); /* FAN divisor register */ + hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ - hwm_write(0x40, 0x01); /* Init, but no SMI# */ + hwm_write(0x40, 0x01); /* Init, but no SMI# */ } /* mainboard_enable is executed as first thing after */ @@ -155,7 +173,9 @@ static void mainboard_enable(struct device *dev) { - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a1d480c8b618a184c2b5ae08380f45fbd628ec Gerrit-Change-Number: 31155 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/block/pcr: Remove unneeded white space before '\t'
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30818 Change subject: soc/intel/common/block/pcr: Remove unneeded white space before '\t' ...................................................................... soc/intel/common/block/pcr: Remove unneeded white space before '\t' Change-Id: If39d9d23acbb37068584caebe93756f7a9ffeaaa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30818/1 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 804ccff..17d7d20 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -269,7 +269,7 @@ if (!msg || !data || !response) { printk(BIOS_ERR, "Pointer checked for NULL Fail! " - "msg = %p \t data = %p \t response = %p\n", + "msg = %p\t data = %p\t response = %p\n", msg, data, response); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39d9d23acbb37068584caebe93756f7a9ffeaaa Gerrit-Change-Number: 30818 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/ibase/mb899: Set HD Audio to off
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30892 Change subject: mb/ibase/mb899: Set HD Audio to off ...................................................................... mb/ibase/mb899: Set HD Audio to off As AC'97 audio is ON in devicetree, HD audio should be OFF Change-Id: I22af68ab92f76bf3ddcea10faa40a3c6fd934c04 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/30892/1 diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 3544c96..05f48d8 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -41,7 +41,7 @@ register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - #device pci 1b.0 on end # High Definition Audio + device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe device pci 1c.1 on end # PCIe device pci 1c.2 on end # PCIe -- To view, visit https://review.coreboot.org/c/coreboot/+/30892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22af68ab92f76bf3ddcea10faa40a3c6fd934c04 Gerrit-Change-Number: 30892 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove 'assert' function name and open parenthesis
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32121 Change subject: src: Remove 'assert' function name and open parenthesis ...................................................................... src: Remove 'assert' function name and open parenthesis Change-Id: If3dbb1422915f2bfc8ff42c5d9eeeece9e4e9f80 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/spi/spi-generic.c M src/drivers/spi/tpm/tpm.c M src/mainboard/google/poppy/romstage.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/nvidia/tegra210/cpu.c 6 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32121/1 diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 84a42d1..f2e4311 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -103,7 +103,7 @@ deduct_opcode_len = !!(ctrlr->flags & SPI_CNTRLR_DEDUCT_OPCODE_LEN); ctrlr_max = ctrlr->max_xfer_size; - assert (ctrlr_max != 0); + assert(ctrlr_max != 0); /* Assume opcode is always one byte and deduct it from the cmd_len as the hardware has a separate register for the opcode. */ diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index aad7610..740f7be 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -360,7 +360,7 @@ static void tpm2_write_access_reg(uint8_t cmd) { /* Writes to access register can set only 1 bit at a time. */ - assert (!(cmd & (cmd - 1))); + assert(!(cmd & (cmd - 1))); tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); } diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 9de1602..197081e 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -81,7 +81,7 @@ char spd_name[SPD_PART_LEN+1] = { 0 }; const struct dram_info *info = &spd_info[type]; - assert (info->type_code == spd[SPD_DRAM_TYPE_OFF]); + assert(info->type_code == spd[SPD_DRAM_TYPE_OFF]); /* Module type */ printk(BIOS_INFO, "SPD: module type is %s\n", info->str); diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index 066155e..9da1c7d 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -52,8 +52,8 @@ struct i2c_msg seg[2]; u32 buf; - assert (num_bytes < 5); - assert (ia_width_bytes < 3); + assert(num_bytes < 5); + assert(ia_width_bytes < 3); seg[0].flags = 0; seg[0].slave = dev_addr; @@ -94,8 +94,8 @@ struct i2c_msg seg; u8 buf[10]; - assert (num_bytes <= 8); - assert (ia_width_bytes < 3); + assert(num_bytes <= 8); + assert(ia_width_bytes < 3); memcpy(buf, &internal_addr, ia_width_bytes); memcpy(&buf[ia_width_bytes], &data, num_bytes); diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 0065a6c..00afa44 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -513,7 +513,7 @@ int i; routes = soc_pmc_gpio_routes(&num_routes); - assert (routes != NULL); + assert(routes != NULL); for (i = 0; i < num_routes; i++, routes++) { if (pmc_gpe_num == routes->pmc) return routes->gpio; diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index 8d74bd3..11b7082 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -34,7 +34,7 @@ CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX3, }; - assert (cpu < CONFIG_MAX_CPUS); + assert(cpu < CONFIG_MAX_CPUS); /* Clear reset of CPU components. */ write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu_clocks[cpu]); -- To view, visit https://review.coreboot.org/c/coreboot/+/32121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3dbb1422915f2bfc8ff42c5d9eeeece9e4e9f80 Gerrit-Change-Number: 32121 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31409 Change subject: sb/intel/common: Use big enough type for left-shift ...................................................................... sb/intel/common: Use big enough type for left-shift Change-Id: I662b66513db48ff1742255beef524762cdaf4dc8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/spi.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31409/1 diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 7f07a72..7a1070c 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -33,7 +33,7 @@ #define D31F0_ETR3 0xac #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) -#define ETR3_CF9LOCK (1 << 31) +#define ETR3_CF9LOCK (1UL << 31) #define D31F0_GPIO_ROUT 0xb8 #define GPI_DISABLE 0x00 #define GPI_IS_SMI 0x01 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 60c0b8d..4e8e80f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -984,7 +984,7 @@ #define ICH7_SPI_FPR_LIMIT_SHIFT 12 #define ICH9_SPI_FPR_LIMIT_SHIFT 16 #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ -#define SPI_FPR_WPE (1 << 31) /* Write Protect */ +#define SPI_FPR_WPE (1UL << 31) /* Write Protect */ static u32 spi_fpr(u32 base, u32 limit) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662b66513db48ff1742255beef524762cdaf4dc8 Gerrit-Change-Number: 31409 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31408 Change subject: nb/intel/i945: Use big enough type for left-shift ...................................................................... nb/intel/i945: Use big enough type for left-shift Change-Id: I7eb5850e4af3d5a41973a73737751b0f29c9d507 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c 4 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31408/1 diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 053815b..3fc1483 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -41,15 +41,15 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); max_buses = 256; break; case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); max_buses = 128; break; case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); max_buses = 64; break; default: // RSVD diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b82812e..fb504af 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -316,7 +316,7 @@ printk(BIOS_DEBUG, "ok\n"); /* Now enable VC1 */ - EPBAR32(EPVC1RCTL) |= (1 << 31); + EPBAR32(EPVC1RCTL) |= (1U << 31); printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ @@ -359,7 +359,7 @@ reg32 = RCBA32(V1CTL); reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24)); - reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); + reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1U << 31); RCBA32(V1CTL) = reg32; RCBA32(ESD) |= (2 << 16); @@ -408,7 +408,7 @@ DMIBAR32(DMIVC1RCTL) = reg32; /* Now enable VC1 */ - DMIBAR32(DMIVC1RCTL) |= (1 << 31); + DMIBAR32(DMIVC1RCTL) |= (1U << 31); printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ @@ -485,8 +485,8 @@ reg32 |= (0x02 << 26); DMIBAR32(0x200) = reg32; - DMIBAR32(DMIDRCCFG) &= ~(1 << 31); - DMIBAR32(DMICTL2) |= (1 << 31); + DMIBAR32(DMIDRCCFG) &= ~(1U << 31); + DMIBAR32(DMICTL2) |= (1U << 31); if (i945_silicon_revision() >= 3) { reg32 = DMIBAR32(0xec0); @@ -762,11 +762,11 @@ pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); - reg32 &= ~(1 << 31); + reg32 &= ~(1U << 31); pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); - reg32 |= (1 << 31); + reg32 |= (1U << 31); pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); if (i945_silicon_revision() >= 3) { diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 7c209dc..3973f80 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -45,13 +45,13 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); return 256; case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); return 128; case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); return 64; } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dece9bf..c86628b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1156,7 +1156,7 @@ sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) reg32 |= (1 << 7) | (1 << 5); else - reg32 |= (1 << 31); + reg32 |= (1U << 31); /* Is channel 1 populated? */ if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || @@ -2006,7 +2006,7 @@ reg32 = MCHBAR32(WCC); reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + reg32 |= (4U << 29) | (3 << 25) | (1 << 10); MCHBAR32(WCC) = reg32; MCHBAR32(SMVREFC) |= (1 << 6); -- To view, visit https://review.coreboot.org/c/coreboot/+/31408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb5850e4af3d5a41973a73737751b0f29c9d507 Gerrit-Change-Number: 31408 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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