coreboot-gerrit March 2019

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Change in ...coreboot[master]: google/kukui: Add panel config data for display
by jitao shi (Code Review) 08 May '19

08 May '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31590 Change subject: google/kukui: Add panel config data for display ...................................................................... google/kukui: Add panel config data for display BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31590/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 950dca4..bf9bd02 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -15,9 +15,12 @@ #include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <edid.h> +#include <gpio.h> #include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> @@ -42,13 +45,66 @@ setup_usb_host(); } +/* Setup backlight control pins as output pin and power-off by default */ +static void configure_backlight(void) +{ + /* Configure PANEL_LCD_POWER_EN */ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ +} + +static void configure_display(void) +{ + /* board from p0 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); +} + +static const struct edid kukui_innolux_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "768x1024@60Hz", + .pixel_clock = 56900, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0, + .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 120, .y_mm = 160, + }, +}; + +struct lcm_init_table lcm_init_cmd[] = { + {INIT_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON}}, + {DELAY_CMD, 120, {}}, +}; + + static void display_startup(void) { + int ret = 0; + u32 mipi_dsi_flags; struct edid edid; + edid = kukui_innolux_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM; + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } mtk_ddp_mode_set(&edid); @@ -62,6 +118,8 @@ mtcmos_display_power_on(); mtcmos_protect_display_bus(); + configure_backlight(); + configure_display(); display_startup(); } else { printk(BIOS_INFO, "Skipping display init.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Gerrit-Change-Number: 31590 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: WIP: mediaek/mt8183: add panel driver for kukui p2
by jitao shi (Code Review) 08 May '19

08 May '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32097 Change subject: WIP: mediaek/mt8183: add panel driver for kukui p2 ...................................................................... WIP: mediaek/mt8183: add panel driver for kukui p2 BUG=b:80501386,b:117254947 BRANCH=none TEST=build pass Change-Id: I878c9e0454acdbc0cd2cd310b8519efb845bb6ee Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/dsi.c 2 files changed, 222 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32097/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index bf9bd02..541485a 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boardid.h> #include <bootmode.h> #include <console/console.h> #include <delay.h> @@ -55,11 +56,72 @@ static void configure_display(void) { - /* board from p0 */ - gpio_output(GPIO(LCM_RST), 0); - udelay(100); - gpio_output(GPIO(LCM_RST), 1); - mdelay(20); + + printk(BIOS_ERR, "board_id() = %d\n", board_id()); + + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + printk(BIOS_ERR, "board from p2\n"); + + gpio_output(GPIO(LCM_RST), 0); + gpio_output(GPIO(BPI_BUS3), 0); + gpio_output(GPIO(MISC_BSI_CK_3), 0); + gpio_output(GPIO(PERIPHERAL_EN9), 0); + gpio_output(GPIO(SIM2_SRST), 0); + gpio_output(GPIO(SIM2_SIO), 0); + gpio_output(GPIO(BPI_OLAT1), 0); + gpio_output(GPIO(SIM2_SCLK), 0); + gpio_set_pull(GPIO(LCM_RST), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(BPI_BUS3), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(MISC_BSI_CK_3), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(PERIPHERAL_EN9), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SRST), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SIO), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(BPI_OLAT1), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SCLK), GPIO_PULL_ENABLE, GPIO_PULL_UP); + + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + + gpio_output(GPIO(MISC_BSI_CK_3), 1); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(SIM2_SRST), 1); + gpio_output(GPIO(SIM2_SIO), 1); + gpio_output(GPIO(BPI_OLAT1), 1); + gpio_output(GPIO(SIM2_SCLK), 1); + + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + gpio_output(GPIO(BPI_BUS3), 1); + mdelay(20); + mdelay(20); + + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox350] = 0x%x\n", read32((void *)GPIO_BASE + 0x350)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox10] = 0x%x\n", read32((void *)GPIO_BASE + 0x10)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox110] = 0x%x\n", read32((void *)GPIO_BASE + 0x110)); + + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox390] = 0x%x\n", read32((void *)GPIO_BASE + 0x390)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox20] = 0x%x\n", read32((void *)GPIO_BASE + 0x20)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox120] = 0x%x\n", read32((void *)GPIO_BASE + 0x120)); + } } static const struct edid kukui_innolux_edid = { @@ -84,6 +146,76 @@ {DELAY_CMD, 120, {}}, }; +static const struct edid kukui_p097pfg_ssd2858_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1536x2048@60Hz", + .pixel_clock = 229000, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1536, .hbl = 160, .hso = 80, .hspw = 26, .hborder = 0, + .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 196, + }, +}; + +struct lcm_init_table lcm_p097pfg_ssd2858_init_cmd[] = { + /* SSD2858 config */ + {INIT_CMD, 2, {0xff, 0x00}}, + /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2}}, MULT=0x49 + * 27 Mhz => 985.5 Mhz */ + {INIT_CMD, 6, {0x00, 0x08, 0x01, 0xf4, 0x01, 0x49}}, + /* MTXDIV=1, SYSDIV=3 (=> 4) */ + {INIT_CMD, 6, {0x00, 0x0c, 0x00, 0x00, 0x00, 0x03}}, + /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1 + * MRXEE=1 */ + {INIT_CMD, 6, {0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f}}, + {INIT_CMD, 6, {0x00, 0x20, 0x15, 0x92, 0x56, 0x7d}}, + {INIT_CMD, 6, {0x00, 0x24, 0x00, 0x00, 0x30, 0x00}}, + +// {INIT_CMD, 1, {0x11}}, +// {DELAY_CMD, 120, {}}, + + {INIT_CMD, 6, {0x10, 0x08, 0x01, 0x20, 0x04, 0x45}}, + {INIT_CMD, 6, {0x10, 0x1c, 0x00, 0x00, 0x00, 0x00}}, + {INIT_CMD, 6, {0x20, 0x0c, 0x00, 0x00, 0x00, 0x04}}, + /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */ + {INIT_CMD, 6, {0x20, 0x10, 0x00, 0x4b, 0x00, 0x49}}, + {INIT_CMD, 6, {0x20, 0xa0, 0x00, 0x00, 0x00, 0x00}}, + /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */ + {INIT_CMD, 6, {0x60, 0x08, 0x00, 0xd9, 0x00, 0x08}}, + {INIT_CMD, 6, {0x60, 0x14, 0x01, 0x00, 0x01, 0x06}}, + /* DSI0 enable (default: probably not needed) */ + {INIT_CMD, 6, {0x60, 0x80, 0x00, 0x00, 0x00, 0x0f}}, + /* DSI1 enable */ + {INIT_CMD, 6, {0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f}}, + + /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */ + {INIT_CMD, 6, {0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18}}, + /* VACT= 0x800 (2048}}, VFP= 0x14, HFP=0x50 */ + {INIT_CMD, 6, {0x60, 0x10, 0x08, 0x00, 0x14, 0x50}}, + /* HACT=0x300 (768) */ + {INIT_CMD, 6, {0x60, 0x84, 0x00, 0x00, 0x03, 0x00}}, + {INIT_CMD, 6, {0x60, 0xa4, 0x00, 0x00, 0x03, 0x00}}, + + /* Take panel out of sleep. */ + {INIT_CMD, 2, {0xff, 0x01}}, + {INIT_CMD, 1, {0x11}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x29}}, + {DELAY_CMD, 20, {}}, + {INIT_CMD, 2, {0xff, 0x00}}, + + //{INIT_CMD, 6, {0x60, 0x14, 0x41, 0x00, 0x81, 0x02}}, + //{INIT_CMD, 6, {0x60, 0x14, 0xc1, 0x00, 0x81, 0x0A}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x11}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x29}}, + {DELAY_CMD, 20, {}}, +}; static void display_startup(void) { @@ -91,16 +223,30 @@ u32 mipi_dsi_flags; struct edid edid; - edid = kukui_innolux_edid; - mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM; + if (board_id() < 2) { + edid = kukui_innolux_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM; + } else { + edid = kukui_p097pfg_ssd2858_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + } edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); - ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, - false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + if (board_id() < 2) + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + else { + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_p097pfg_ssd2858_init_cmd, sizeof(lcm_p097pfg_ssd2858_init_cmd) / sizeof(struct lcm_init_table)); + printk(BIOS_ERR, "mtk_dsi_init from p2\n"); + } + if (ret < 0) { printk(BIOS_ERR, "dsi init fail\n"); return; diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index f96d847..316d92d 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <boardid.h> #include <console/console.h> #include <delay.h> #include <soc/addressmap.h> @@ -97,6 +98,11 @@ printk(BIOS_ERR, "data_rate: %u bps\n", data_rate); + if (board_id() == 2) + data_rate = 1420000000; + + printk(BIOS_ERR, "board_id() == 2 data_rate: %u bps\n", data_rate); + if (data_rate >= 2000000000) { txdiv = 1; txdiv0 = 0; @@ -169,26 +175,28 @@ timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | phy_timing->clk_hs_exit << 16; - dsi_write32(&dsi->dsi_phy_timecon0, timcon0); - dsi_write32(&dsi->dsi_phy_timecon1, timcon1); - dsi_write32(&dsi->dsi_phy_timecon2, timcon2); - dsi_write32(&dsi->dsi_phy_timecon3, timcon3); + if (board_id() < 2) { + dsi_write32(&dsi->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi->dsi_phy_timecon3, timcon3); + } else { + dsi_write32(&dsi->dsi_phy_timecon0, 0x0e1c070d); + dsi_write32(&dsi->dsi_phy_timecon1, 0x1a411334); + dsi_write32(&dsi->dsi_phy_timecon2, 0x11420100); + dsi_write32(&dsi->dsi_phy_timecon3, 0x001a180a); + } } static void mtk_dsi_reset(void) { - dsi_setbits_le32(&dsi->dsi_con_ctrl, 3); - dsi_clrbits_le32(&dsi->dsi_con_ctrl, 1); + dsi_write32(&dsi->dsi_con_ctrl, 1); + dsi_write32(&dsi->dsi_con_ctrl, 0); } static void mtk_dsi_clk_hs_mode_enable(void) { - dsi_setbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_clk_hs_mode_disable(void) -{ - dsi_clrbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); + dsi_setbits_le32(&dsi->dsi_phy_lccon, 1); } static void mtk_dsi_set_mode(u32 mode_flags) @@ -312,7 +320,7 @@ edid->mode.hborder) * bpp - 10; else hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bpp - 10; + edid->mode.hborder) * bpp - 8; hsync_active_byte = edid->mode.hspw * bpp - 10; hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; @@ -348,8 +356,8 @@ static void mtk_dsi_start(void) { - dsi_write32(&dsi->dsi_start, 0); - dsi_write32(&dsi->dsi_start, 1); + dsi_clrbits_le32(&dsi->dsi_start, 1); + dsi_setbits_le32(&dsi->dsi_start, 1); } static void mtk_dsi_cmdq(u8 *data, u8 len) @@ -359,6 +367,15 @@ u8 cmdq_size; u32 reg_val, cmdq_mask, i, config, cmdq_off, type, intsta_0; + + while(read32(&dsi->dsi_intsta) & (1 << 31)) { + printk(BIOS_ERR, "mtk_dsi_cmdq wait dsi no busy\n"); + mdelay(20); + } + + printk(BIOS_ERR, "mtk_dsi_cmdq dsi no busy\n"); + dsi_write32(&dsi->dsi_intsta, 0); + switch (len) { case 0: return; @@ -393,14 +410,17 @@ reg_val = (type << 8) | config; } - for (i = 0; i < len; i++) - dsi_clrsetbits_le32(&dsi->dsi_cmdq0 + ((cmdq_off + i) & (~0x3)), + for (i = 0; i < 0x20; i = i + 4) + dsi_write32((void *)DSI_BASE + 0x200 + i, 0); + + for (i = 0; i < len; i++) { + dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + ((cmdq_off + i) & (0xfffffffc)), (0xff << (((i + cmdq_off) & 3) * 8)), tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + } dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); - dsi_write32(&dsi->dsi_intsta, 0); mtk_dsi_start(); stopwatch_init_usecs_expire(&sw, 400); @@ -414,7 +434,12 @@ if (!(intsta_0 & CMD_DONE_INT_FLAG)) printk(BIOS_ERR, "dsi DONE INT Timeout\n"); - dsi_write32(&dsi->dsi_start, 0); + for (i = 0x200; i < 0x210; i = i + 4) + printk(BIOS_ERR, "dump_dsi_reg : reg[0x%x] = 0x%x\n", i, read32((void *)DSI_BASE + i)); + + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x60] = 0x%x\n", read32((void *)DSI_BASE + 0x60)); + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x00] = 0x%x\n", read32((void *)DSI_BASE)); + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x14] = 0x%x\n", read32((void *)DSI_BASE + 0x14)); } static void push_table(struct lcm_init_table *init_cmd, u32 count) @@ -426,7 +451,17 @@ switch (cmd) { case DELAY_CMD: - mdelay(init_cmd[i].cmd); + if (init_cmd[i].cmd > 20) { + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + } else { + mdelay(20); + } + printk(BIOS_ERR, "delay : init_cmd[%d].len = 0x%x\n", i, init_cmd[i].len); break; case END_OF_TABLE: @@ -434,6 +469,7 @@ case INIT_CMD: default: + printk(BIOS_ERR, "init_cmd : init_cmd[%d].data[0] = 0x%x\n", i, init_cmd[i].data[0]); mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len); break; } @@ -443,7 +479,7 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, const struct edid *edid, struct lcm_init_table *init_cmd, u32 count) { - int data_rate; + int data_rate, i; struct mtk_phy_timing phy_timing; mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); @@ -453,18 +489,23 @@ if (data_rate < 0) return -1; - mtk_dsi_reset(); dsi_write32(&dsi->dsi_force_commit, 3); + mtk_dsi_reset(); mtk_dsi_phy_timconfig(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, edid); mtk_dsi_clk_hs_mode_enable(); - mtk_dsi_set_mode(0); push_table(init_cmd, count); mtk_dsi_set_mode(mode_flags); mtk_dsi_start(); + dsi_write32((void *)DSI_BASE + 0x178, 0x00ff0000); + dsi_write32((void *)DSI_BASE + 0x17c, 0x00200040); + + for (i = 0; i < 0x208; i = i + 4) { + printk(BIOS_ERR, "dump_dsi_reg : reg[ox%x] = 0x%x\n", i, read32((void *)DSI_BASE + i)); + } + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I878c9e0454acdbc0cd2cd310b8519efb845bb6ee Gerrit-Change-Number: 32097 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

8 21

Change in ...coreboot[master]: util/inteltool: Add Sunrise Point LP (Skylake) IDs
by Felix Singer (Code Review) 06 May '19

06 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31506 Change subject: util/inteltool: Add Sunrise Point LP (Skylake) IDs ...................................................................... util/inteltool: Add Sunrise Point LP (Skylake) IDs Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/31506/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 93a7ffe..bdcee02 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -224,11 +224,19 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, "Sunrise Point Desktop Engineering Sample" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE, + "Sunrise Point Mobile Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1, "Sunrise Point-LP U Base" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2, + "Sunrise Point-LP U Base" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1, "Sunrise Point-LP U Premium" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2, + "Sunrise Point-LP U Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1, + "Sunrise Point-LP Y Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2, "Sunrise Point-LP Y Premium" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE, "Sunrise Point-LP U iHDCP 2.2 Base" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fb64811..9fbe9b5 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -144,10 +144,14 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE 0x9d53 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM 0x9d58 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1 0x9d43 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2 0x9d53 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1 0x9d48 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2 0x9d58 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1 0x9d46 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2 0x9d56 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b -- To view, visit https://review.coreboot.org/c/coreboot/+/31506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Gerrit-Change-Number: 31506 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x: Use common/rcba.h
by Patrick Rudolph (Code Review) 06 May '19

06 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32066 Change subject: sb/intel/bd82x6x: Use common/rcba.h ...................................................................... sb/intel/bd82x6x: Use common/rcba.h Make use of: * southbridge/intel/common/rcba.h * southbridge/intel/common/pmbase.c * defines in pch.h Get rid of dependency to DEFAULT_RCBA. Untested. Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 14 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32066/1 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 17919af..955737e 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -19,6 +19,9 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/pmbase.h> + #include "pch.h" void early_usb_init(const struct southbridge_usb_port *portmap) @@ -32,46 +35,39 @@ 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, 0x20000353 }; int i; - /* Activate PMBAR. */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Unlock registers. */ - outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, - DEFAULT_PMBASE | UPRWC); + write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) - write32(DEFAULT_RCBABASE + (0x3500 + 4 * i), - currents[portmap[i].current]); + RCBA32(0x3500 + 4 * i) = currents[portmap[i].current]; for (i = 0; i < 10; i++) - write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); + RCBA32(0x3538 + 4 * i) = 0; for (i = 0; i < 8; i++) - write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); + RCBA32(0x3560 + 4 * i) = rcba_dump[i]; for (i = 0; i < 8; i++) - write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); + RCBA32(0x3580 + 4 * i) = 0; reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32(DEFAULT_RCBABASE + USBPDO, reg32); + RCBA32(USBPDO) = reg32; reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32(DEFAULT_RCBABASE + USBOCM1, reg32); + RCBA32(USBOCM1) = reg32; reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32(DEFAULT_RCBABASE + USBOCM2, reg32); + RCBA32(USBOCM2) = reg32; for (i = 0; i < 22; i++) - write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); + RCBA32(0x35a8 + 4 * i) = 0; - pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32(PCH_XHCI_DEV, 0xe4, 0x00000000); /* Relock registers. */ - outw(0, DEFAULT_PMBASE | UPRWC); + write_pmbase16(UPRWC, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0 Gerrit-Change-Number: 32066 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: soc/amd/common: Introduce module_dispatch()
by Kyösti Mälkki (Code Review) 06 May '19

06 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31485 Change subject: soc/amd/common: Introduce module_dispatch() ...................................................................... soc/amd/common: Introduce module_dispatch() This change removes all the separate entrypoint dispatch functions as they all share the same pattern. Furthermore, none of the function definitions under vendorcode binaryPI/AGESA.c file have proper declarations, the ones compiler picks up from AGESA.h are for the internal implementations and with sanely organized headerfiles would not be exposed outside the build of AGESA at all. Change-Id: I0b72badc007565740c93b58743cfd048e8b42775 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c 2 files changed, 39 insertions(+), 170 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31485/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index fb33f4d..f09fc5d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -42,8 +42,34 @@ static void *AcpiIvrs; static void *AcpiCrat; +static AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func, + AMD_CONFIG_PARAMS *StdHeader) +{ + MODULE_ENTRY dispatcher = agesa_get_dispatcher(); + + if (!dispatcher) + return AGESA_UNSUPPORTED; + + StdHeader->Func = func; + return dispatcher(StdHeader); +} + +static AGESA_STATUS amd_dispatch(void *Params) +{ + AMD_CONFIG_PARAMS *StdHeader = Params; + return module_dispatch(StdHeader->Func, StdHeader); +} + +AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) +{ + AMD_CONFIG_PARAMS *StdHeader = (void *)ApExeParams; + return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); +} + static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) { + AMD_CONFIG_PARAMS *StdHeader; + /* Should clone entire StdHeader here. */ interface_struct->StdHeader.CalloutPtr = &GetBiosCallout; @@ -58,7 +84,9 @@ if (!interface_struct->NewStructPtr) /* Avoid NULL pointer usage */ die("No AGESA structure created"); - return interface_struct->NewStructPtr; + StdHeader = interface_struct->NewStructPtr; + StdHeader->Func = interface_struct->AgesaFunctionName; + return StdHeader; } static AGESA_STATUS amd_init_reset(void) @@ -77,7 +105,7 @@ SetFchResetParams(&ResetParams->FchInterface); timestamp_add_now(TS_AGESA_INIT_RESET_START); - status = AmdInitReset(ResetParams); + status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -98,7 +126,7 @@ OemCustomizeInitEarly(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_START); - status = AmdInitEarly(EarlyParams); + status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -163,7 +191,7 @@ ); timestamp_add_now(TS_AGESA_INIT_POST_START); - status = AmdInitPost(PostParams); + status = amd_dispatch(PostParams); timestamp_add_now(TS_AGESA_INIT_POST_DONE); /* @@ -206,7 +234,7 @@ SetNbEnvParams(&EnvParams->GnbEnvConfiguration); timestamp_add_now(TS_AGESA_INIT_ENV_START); - status = AmdInitEnv(EnvParams); + status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -257,7 +285,7 @@ SetNbMidParams(&MidParams->GnbMidConfiguration); timestamp_add_now(TS_AGESA_INIT_MID_START); - status = AmdInitMid(MidParams); + status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -287,7 +315,7 @@ } timestamp_add_now(TS_AGESA_INIT_LATE_START); - Status = AmdInitLate(LateParams); + Status = amd_dispatch(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); DmiTable = LateParams->DmiTable; @@ -310,11 +338,6 @@ return Status; } -AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) -{ - return AmdLateRunApTask(ApExeParams); -} - static AGESA_STATUS amd_init_rtb(void) { AGESA_STATUS Status; @@ -326,7 +349,7 @@ AMD_RTB_PARAMS *RtbParams = create_struct(&AmdParamStruct); timestamp_add_now(TS_AGESA_INIT_RTB_START); - Status = AmdInitRtb(RtbParams); + Status = amd_dispatch(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); if (save_s3_info(RtbParams->S3DataBlock.NvStorage, @@ -355,7 +378,7 @@ InitResumeParams->S3DataBlock.NvStorageSize = nv_size; timestamp_add_now(TS_AGESA_INIT_RESUME_START); - status = AmdInitResume(InitResumeParams); + status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -383,7 +406,7 @@ S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_LATE_START); - Status = AmdS3LateRestore(S3LateParams); + Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -409,7 +432,7 @@ S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_FINAL_START); - Status = AmdS3FinalRestore(S3FinalParams); + Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); AmdReleaseStruct(&AmdParamStruct); diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index 2efee4e..e17cedc 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -72,157 +72,3 @@ if (!Dispatcher) return AGESA_UNSUPPORTED; return Dispatcher(InterfaceParams); } - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResetParams->StdHeader.Func = AMD_INIT_RESET; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResetParams); -} - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EarlyParams->StdHeader.Func = AMD_INIT_EARLY; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EarlyParams); -} - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - PostParams->StdHeader.Func = AMD_INIT_POST; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(PostParams); -} - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EnvParams->StdHeader.Func = AMD_INIT_ENV; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EnvParams); -} - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - MidParams->StdHeader.Func = AMD_INIT_MID; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(MidParams); -} - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - LateParams->StdHeader.Func = AMD_INIT_LATE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(LateParams); -} - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResumeParams->StdHeader.Func = AMD_INIT_RESUME; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResumeParams); -} - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3LateParams); -} - -/********************************************************************** - * Interface call: AmdS3FinalRestore - **********************************************************************/ -AGESA_STATUS -AmdS3FinalRestore ( - IN OUT AMD_S3FINAL_PARAMS *S3FinalParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3FinalParams->StdHeader.Func = AMD_S3FINAL_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3FinalParams); -} - -/********************************************************************** - * Interface call: AmdInitRtb - **********************************************************************/ -AGESA_STATUS -AmdInitRtb ( - IN OUT AMD_RTB_PARAMS *AmdInitRtbParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdInitRtbParams->StdHeader.Func = AMD_INIT_RTB; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdInitRtbParams); -} - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdApExeParams); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b72badc007565740c93b58743cfd048e8b42775 Gerrit-Change-Number: 31485 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: inteltool: Skylake GPIOs #2
by Felix Singer (Code Review) 05 May '19

05 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31660 Change subject: inteltool: Skylake GPIOs #2 ...................................................................... inteltool: Skylake GPIOs #2 Used Intel documents: - 332995-001EN - 332996-002EN Change-Id: Ic006d9c094f9fe1ad419cb0168ada45b7dd81732 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31660/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index a87ae35..52eae09 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1027,6 +1027,9 @@ case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_DNV_LPC: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index d61438b..5abb570 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -908,6 +908,9 @@ communities = sunrise_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2: -- To view, visit https://review.coreboot.org/c/coreboot/+/31660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic006d9c094f9fe1ad419cb0168ada45b7dd81732 Gerrit-Change-Number: 31660 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variant/atlas: enable USB acpi
by Gaggery Tsai (Code Review) 03 May '19

03 May '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30754 Change subject: mb/google/poppy/variant/atlas: enable USB acpi ...................................................................... mb/google/poppy/variant/atlas: enable USB acpi Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:122540489 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage $cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat & retrieve ssdt.dat from DUT & $iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio" under _DSD object Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30754/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 59abe72..197986d 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -150,6 +150,7 @@ select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 select VARIANT_HAS_CAMERA_ACPI diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index f8a6e6d..97c10b0 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -268,7 +268,30 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + end + end + end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/30754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Gerrit-Change-Number: 30754 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: fleex: Add VPD entry for deciding which touchscreen ACPI nodes to gen...
by Tim Wawrzynczak (Code Review) 29 Apr '19

29 Apr '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32006 Change subject: fleex: Add VPD entry for deciding which touchscreen ACPI nodes to generate. ...................................................................... fleex: Add VPD entry for deciding which touchscreen ACPI nodes to generate. Fleex has the option of two different touchscreens, WDT or Elan. A new VPD entry will go along with this (key="touchscreen", value="wdt" or "elan"). If the VPD entry exists, only one ACPI node will be generated for that I2C bus. If no entry exists, or no tag is specified in the device tree, then both nodes will be generated and it will be up to the kernel to probe for them. Change-Id: I0e0a9f96f3d3de9be36b218600268711b80c18b9 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/i2c/generic/chip.h M src/drivers/i2c/generic/generic.c M src/mainboard/google/octopus/variants/fleex/overridetree.cb M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/vpd_ssdt.c A src/vendorcode/google/chromeos/vpd_ssdt.h 6 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/32006/1 diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 9e2abb9..7cf04cd 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -75,6 +75,8 @@ /* Generic properties for exporting device-specific data to the OS */ struct acpi_dp property_list[MAX_GENERIC_PROPERTY_LIST]; int property_count; + const char *vpd_string_tag; + const char *vpd_string_value; }; /* diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 598f211..75a365f 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -22,6 +22,8 @@ #include <gpio.h> #include <stdint.h> #include <string.h> +#include <vendorcode/google/chromeos/vpd_ssdt.h> + #include "chip.h" #if CONFIG(HAVE_ACPI_TABLES) @@ -79,6 +81,11 @@ return; } + if (config->vpd_string_tag && config->vpd_string_value && + !vpd_should_generate_ssdt(config->vpd_string_tag, + config->vpd_string_value)) + return; + /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 19246e0..a368598 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -122,6 +122,8 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" + register "vpd_string_tag" = ""touchscreen"" + register "vpd_string_value" = ""elan"" device i2c 10 on end end chip drivers/i2c/hid @@ -136,6 +138,8 @@ register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x20" + register "generic.vpd_string_tag" = ""touchscreen"" + register "generic.vpd_string_value" = ""wdt"" device i2c 2c on end end end # - I2C 7 diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..6776c5f 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -18,6 +18,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += vpd_ssdt.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c diff --git a/src/vendorcode/google/chromeos/vpd_ssdt.c b/src/vendorcode/google/chromeos/vpd_ssdt.c new file mode 100644 index 0000000..7ed0199 --- /dev/null +++ b/src/vendorcode/google/chromeos/vpd_ssdt.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> +#include <drivers/vpd/vpd.h> + +#include <string.h> + +#include "vpd_ssdt.h" + +/* + * For multi-sourced components, we may decide to store the presence + * of one or the other in the VPD area. If that's the case, we can + * decide to only populate the ACPI SSDT table with the one that's + * actually in the device in question. In that case, we'll search + * the VPD tables to find a matching entry; if there is an entry + * with the appropriate tag, return true if the value matches, false + * otherwise. If there is no entry, then return true as well, meaning + * we don't know which component is being used, so the entry should be + * available in the SSDT and the kernel can probe for both. + */ +int vpd_should_generate_ssdt(const char *key, const char *value) +{ + const void *vpd_entry; + int size; + int keys_cmp; + + vpd_entry = vpd_find(key, &size, VPD_RO); + + /* If no entry was found, then generate an SSDT node */ + if (!vpd_entry) + return 1; + + /* If an entry was found, then compare values */ + keys_cmp = strncmp((char *)vpd_entry, value, size); + + if (keys_cmp == 0) + return 1; + else + return 0; +} diff --git a/src/vendorcode/google/chromeos/vpd_ssdt.h b/src/vendorcode/google/chromeos/vpd_ssdt.h new file mode 100644 index 0000000..37e887e --- /dev/null +++ b/src/vendorcode/google/chromeos/vpd_ssdt.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VPD_ACPI_H +#define VPD_ACPI_H + +int vpd_should_generate_ssdt(const char *key, const char *value); + +#endif /* VPD_ACPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0a9f96f3d3de9be36b218600268711b80c18b9 Gerrit-Change-Number: 32006 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: soc/{amd,intel}/chip: Use local include for chip.h
by HAOUAS Elyes (Code Review) 26 Apr '19

26 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32014 Change subject: soc/{amd,intel}/chip: Use local include for chip.h ...................................................................... soc/{amd,intel}/chip: Use local include for chip.h Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/fsp_broadwell_de/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/skylake/chip.c 6 files changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32014/1 diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 1bd8cbf..5c2a58b 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <bootstate.h> #include <console/console.h> #include <cpu/amd/mtrr.h> @@ -30,6 +29,8 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include "chip.h" + /* Supplied by i2c.c */ extern struct device_operations stoneyridge_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e8fd9d1..dbf697d 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -23,6 +22,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + static void pci_domain_set_resources(struct device *dev) { printk(BIOS_SPEW, "%s/%s (%s)\n", diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index d50c689..8df0aa7 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -28,6 +27,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index 6b14845..1711e3a 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -22,7 +22,8 @@ #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <chip.h> + +#include "chip.h" static void pci_domain_set_resources(struct device *dev) { diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 0e4388e..e275fd2 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +28,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 98e5baf..fa2e0fb 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -15,7 +15,6 @@ */ #include <arch/acpi.h> -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -33,6 +32,8 @@ #include <soc/ramstage.h> #include <string.h> +#include "chip.h" + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a -- To view, visit https://review.coreboot.org/c/coreboot/+/32014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Gerrit-Change-Number: 32014 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 17

Change in ...coreboot[master]: mb/ocp/monolake: add TPM and IPMI support
by Łukasz Siudut (Code Review) 24 Apr '19

24 Apr '19

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31525 Change subject: mb/ocp/monolake: add TPM and IPMI support ...................................................................... mb/ocp/monolake: add TPM and IPMI support Changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable by ipmi_si driver Signed-off-by: Lukasz Siudut <lsiudut(a)fb.com> Change-Id: I8f9fb17b9f1349272080e032991fe45a443a9d84 --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 5 files changed, 153 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31525/1 diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 76ecb48..2315ec6 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -11,6 +11,11 @@ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + +config INTEGRATED_UART + def_bool n config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 30d99c2..2d91b73 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -7,7 +7,14 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip drivers/generic/generic # BMC KCS + device pnp ca2.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller device pci 1f.5 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703..72b1c3c 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,6 +27,9 @@ { #include "acpi/platform.asl" + Name (IDTP, 0x0CA2) + Name (ICDP, 0x0CA6) + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -290,5 +293,97 @@ } } + Scope (_SB.PCI0.LPC0) + { + Device (SPMI) + { + Name (_HID, EisaId ("IPI0001")) + Name (_STR, Unicode ("IPMI_KCS")) + Name (_UID, 0x00) + OperationRegion (IPST, SystemIO, ICDP, 0x01) + Field (IPST, ByteAcc, NoLock, Preserve) + { + STAS, 8 + } + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } + Name (ICRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y01) + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y02) + + }) + Method (_CRS, 0, NotSerialized) + { + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) + + IPDB = IDTP + IPDH = IDTP + IPDL = 0x01 + + IPCB = ICDP + IPCH = ICDP + IPCL = 0x01 + + Return (ICRS) + } + Method (_IFT, 0, NotSerialized) { + Return (0x01) + } + Method(_SRV, 0, NotSerialized) { + Return (0x0200) + } + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, + 0x0CA2, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA6, + 0x0CA6, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA8, + 0x0CA8, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CAC, + 0x0CAC, + 0x01, + 0x01, + ) + }) + } + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index f1a3a20..934b757 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -15,17 +15,52 @@ */ #include <device/device.h> +#include <smbios.h> + #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif +#define BMC_KCS_BASE 0xca2 +#define INTERFACE_IS_IO 0x1 + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address + 0x40, + 0); // no IRQ + + return len; +} +#endif + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif + /* Enable access to the BMC IPMI via KCS */ + struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); + struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + res->base = BMC_KCS_BASE; + res->size = 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index cf52c01..58b2d17 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,8 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +26,14 @@ */ void early_mainboard_romstage_entry(void) { - + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, + 0x0c0681); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + 0x0c0ca1); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN3_DEC, + 0xfc0201); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN4_DEC, + 0xfc0601); } /** @@ -33,7 +42,6 @@ */ void late_mainboard_romstage_entry(void) { - } /** @@ -41,5 +49,4 @@ */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - } -- To view, visit https://review.coreboot.org/c/coreboot/+/31525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f9fb17b9f1349272080e032991fe45a443a9d84 Gerrit-Change-Number: 31525 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

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