coreboot-gerrit March 2019

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Change in ...coreboot[master]: src/superio/ite/common: Prepare for new SuperIO
by Michał Żygowski (Code Review) 15 May '19

15 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30553 Change subject: src/superio/ite/common: Prepare for new SuperIO ...................................................................... src/superio/ite/common: Prepare for new SuperIO Introduce 7bit Slope PWM registers. New ITE SuperIO may have contiguous 7bit values for PWM slope. Add option to enable External Sensor SMBus Host. Allow early SuperIO serial init in bootblock for platforms supporting C_ENVIRONMENT_BOOTBLOCK. Update/add registers macros for IT8786E-F which are not backwards compatible. Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/superio/ite/Makefile.inc M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 5 files changed, 53 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30553/1 diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 382dbd7..a54db6f 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -14,7 +14,11 @@ ## ## include generic ite pre-ram stage driver -romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c + +ifeq ($(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += common/early_serial.c +romstage-y += common/early_serial.c +endif ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 162b7f1..fd6a699 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -41,4 +41,10 @@ help The second FAN controller has a separate frequency setting. +config SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + bool + help + Slope PWM registers have no separate BIT6 and are set directly by + 7-bit values instead. + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1dc5bb6..fb347de 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -164,9 +165,14 @@ pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin); pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); - pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); - pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { + pwm_auto = conf->slope & 0x7f; + } else { + pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } + if (conf->smoothing) pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; @@ -213,7 +219,7 @@ ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); } - if (IS_ENABLED(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); @@ -271,6 +277,13 @@ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]); + /* Enable External Sensor SMBus Host if configured */ + if (conf->smbus_en) { + ite_ec_write(base, ITE_EC_INTERFACE_SELECT, + ite_ec_read(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_SMB_ENABLE); + } + /* Enable reading of voltage pins */ ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 11316db..06a41a5 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,13 +49,34 @@ #define ITE_EC_FAN_PWM_SMOOTHING_1KHZ (0 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_256HZ (1 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_64HZ (2 << 6) +#if IS_ENABLED(CONFIG_SUPERIO_ITE_IT8786E) +#define ITE_EC_FAN_PWM_SMOOTHING_16HZ (1 << 6) +#else #define ITE_EC_FAN_PWM_SMOOTHING_16HZ (3 << 6) +#endif +/* SUPERIO_ITE_IT8786E PWM_SMOOTHING_FREQ contents */ +#define ITE_EC_FAN_PWM_SMOOTHING_1HZ (0 << 6) +#define ITE_EC_FAN_PWM_SMOOTHING_8HZ (2 << 6) +#define ITE_EC_FAN_PWM_SMOOTHING_4HZ (3 << 6) +#define ITE_EC_FAN_CTL5_SEL(x) ((((x)-1) & 3) << 2) +#define ITE_EC_FAN_CTL5_SEL_NONE (3 << 2) +#define ITE_EC_FAN_CTL4_SEL(x) (((x)-1) & 3) +#define ITE_EC_FAN_CTL4_SEL_NONE (3 << 0) #define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c #define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1)) #define ITE_EC_FAN_TAC_LIMIT(x) (0x10 + ((x)-1)) #define ITE_EC_FAN_TAC_EXT_LIMIT(x) (0x1b + ((x)-1)) +/* SUPERIO_ITE_IT8786E FAN_TAC_CNTRL register content */ +#define ITE_EC_FAN_TAC_CNTRL 0x0c +#define ITE_EC_TMPIN3_ENHANCED_INT_MODE (1 << 7) +#define ITE_EC_TMPIN2_ENHANCED_INT_MODE (1 << 6) +#define ITE_EC_FAN_TAC5_EN (1 << 5) +#define ITE_EC_FAN_TAC4_EN (1 << 4) +#define ITE_EC_TMPIN1_ENHANCED_INT_MODE (1 << 3) +#define ITE_EC_AMDTSI_ERR_EN (1 << 0) + #define ITE_EC_FAN_MAIN_CTL 0x13 #define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) #define ITE_EC_FAN_MAIN_CTL_COLL_FULL_SPEED (1 << 3) @@ -130,6 +152,8 @@ #define ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(s) ((s) & 0x3f) #define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) +#define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f #define ITE_EC_EXTEMP_STATUS 0x88 #define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index f8f2e1e..4df9b01 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,6 +96,7 @@ bool tmpin_beep; bool fan_beep; bool vin_beep; + bool smbus_en; }; /* Some shorthands for device trees */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Gerrit-Change-Number: 30553 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Update chromeec submodule to upstream master
by Patrick Georgi (Code Review) 13 May '19

13 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30915 Change subject: Update chromeec submodule to upstream master ...................................................................... Update chromeec submodule to upstream master Updating from commit id 11bd4c0f4: 2018-05-22 21:57:16 -0700 - (bip: enabled PPC interrupts) to commit id 860fe2962: 2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.) This brings in 1420 new commits. Change-Id: Ib7fef556696d6ea6547ec680124e0e13b4c3bfb8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30915/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..860fe29 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d -- To view, visit https://review.coreboot.org/c/coreboot/+/30915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7fef556696d6ea6547ec680124e0e13b4c3bfb8 Gerrit-Change-Number: 30915 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Patrick Georgi (Code Review) 13 May '19

13 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30916 Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 693e278e: 2018-02-01 18:15:53 +0000 - (Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch) to commit id c8765826: 2018-12-19 15:08:23 +0100 - (Merge pull request #1730 from antonio-nino-diaz-arm/an/spdx) This brings in 1583 new commits. Change-Id: Ief895b0bbaf80d0825e38975ba44f77c05d1dded Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30916/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 693e278..c876582 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 693e278e308441d716f7f5116c43aa150955da31 +Subproject commit c8765826f4c2d10db0b660defccc84f7bce11af0 -- To view, visit https://review.coreboot.org/c/coreboot/+/30916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief895b0bbaf80d0825e38975ba44f77c05d1dded Gerrit-Change-Number: 30916 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: nb/intel/sandybridge: Move boot_count_increment()
by Patrick Rudolph (Code Review) 13 May '19

13 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32067 Change subject: nb/intel/sandybridge: Move boot_count_increment() ...................................................................... nb/intel/sandybridge: Move boot_count_increment() Move boot_count_increment() to romstage.c, drop preprocessor code and only increase counter once on regular boot. Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/romstage.c 2 files changed, 5 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32067/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b923065..34aec38 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <elog.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include "sandybridge.h" @@ -45,22 +44,7 @@ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif + printk(BIOS_DEBUG, " done\n"); } static void sandybridge_setup_graphics(void) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 8ddc156..96d98ea 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <elog.h> static void early_pch_reset_pmcon(void) { @@ -80,6 +81,9 @@ s3resume = southbridge_detect_s3_resume(); + if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) + boot_count_increment(); + post_code(0x38); mainboard_early_init(s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/32067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Gerrit-Change-Number: 32067 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/gma: Choose better default settings for HSW
by Nico Huber (Code Review) 12 May '19

12 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31465 Change subject: drivers/intel/gma: Choose better default settings for HSW ...................................................................... drivers/intel/gma: Choose better default settings for HSW When libgfxinit was added, there were no Haswell boards in the tree with discrete CPU/PCH. There are now, and we have a Kconfig to distingush them. So use that instead of mainboard overrides. TEST=Built config for asrock/h81m-hds and checked that GFX_GMA_CPU_VARIANT is still set to `Normal`. Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/gma/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig 2 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31465/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 2dbed01..fd2422d 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -105,7 +105,7 @@ default "ULT" if ((SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEY_LAKE) \ && !SOC_INTEL_CANNONLAKE_PCH_H) \ || ((SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE) && !SKYLAKE_SOC_PCH_H) \ - || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL + || SOC_INTEL_BROADWELL || (NORTHBRIDGE_INTEL_HASWELL && INTEL_LYNXPOINT_LP) default "Normal" config GFX_GMA_INTERNAL_PORT diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 55f1637..f2ba55c 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -40,14 +40,6 @@ hex default 0x200000 -# -# The override of GFX_GMA_CPU_VARIANT should be removed once the patches -# for dynamic CPU detection are merged in libgfxinit. -# -config GFX_GMA_CPU_VARIANT - string - default "Normal" - config MAINBOARD_DIR string default asrock/h81m-hds -- To view, visit https://review.coreboot.org/c/coreboot/+/31465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Gerrit-Change-Number: 31465 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/nami: Add VBT blobs and include them in cbfs
by Arthur Heymans (Code Review) 10 May '19

10 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30427 Change subject: mb/google/nami: Add VBT blobs and include them in cbfs ...................................................................... mb/google/nami: Add VBT blobs and include them in cbfs Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc R src/mainboard/google/poppy/variants/nami/akali-data.vbt A src/mainboard/google/poppy/variants/nami/data.vbt A src/mainboard/google/poppy/variants/nami/patheon-data.vbt A src/mainboard/google/poppy/variants/nami/vayne-data.vbt 5 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30427/1 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 7f86bb7..8f4ef0c 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -41,3 +41,15 @@ cbfs-files-y += oem.bin oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw + +add_vbt_to_cbfs= \ + $(eval cbfs-files-y += $1) \ + $(eval $1-file := $2) \ + $(eval $1-type := raw) \ + $(eval $1-compression := lzma) + +$(call add_vbt_to_cbfs, akali-data.vbt, akali-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, vayne-data.vbt, vayne-vbt.bin) +$(call add_vbt_to_cbfs, data.vbt, vbt.bin) diff --git a/src/mainboard/google/poppy/variants/nami/vbt-akali.bin b/src/mainboard/google/poppy/variants/nami/akali-data.vbt similarity index 100% rename from src/mainboard/google/poppy/variants/nami/vbt-akali.bin rename to src/mainboard/google/poppy/variants/nami/akali-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/data.vbt b/src/mainboard/google/poppy/variants/nami/data.vbt new file mode 100644 index 0000000..8406362 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/patheon-data.vbt b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/vayne-data.vbt b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/30427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Gerrit-Change-Number: 30427 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31027 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..bc2f6f9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -160,10 +160,10 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, 0x10); /* GC: Enable GPIOs */ setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..ff866aa 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -246,13 +246,13 @@ u8 reg8; u8 do_reset = 0; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } @@ -260,14 +260,14 @@ if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } /* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -278,9 +278,9 @@ } /* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ if (!CONFIG_CHECK_SLFRCS_ON_RESUME @@ -1810,9 +1810,9 @@ */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2415,7 +2415,7 @@ MCHBAR32(REPC) |= (1 << 0); /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); + RCBA32(RC) = (1 << 2); /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { @@ -2829,9 +2829,9 @@ sdram_enable_rcomp(); /* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); printk(BIOS_DEBUG, "RAM initialization finished.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Gerrit-Change-Number: 31027 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: soc/intel/braswell/smbus: Init SMBus
by Michał Żygowski (Code Review) 10 May '19

10 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32062 Change subject: soc/intel/braswell/smbus: Init SMBus ...................................................................... soc/intel/braswell/smbus: Init SMBus Using Intel southbridge common implementation to retrieve SPD from DIMMs causes FSP memory init to hang. Initialize SMBus as in Intel SoC common before issuing any transactions to let FSP properly initialize memory. Also make Intel common southbridge smbus API compatible with SPD library. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 --- M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/include/soc/smbus.h M src/soc/intel/braswell/romstage/romstage.c A src/soc/intel/braswell/smbus.c 4 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32062/1 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index a538f7d..554af41 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += smbus.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c @@ -38,6 +39,7 @@ ramstage-y += sata.c ramstage-y += scc.c ramstage-y += sd.c +ramstage-y += smbus.c ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h new file mode 100644 index 0000000..f5075e1 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/smbus.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 3mdeb + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ + +#include <soc/pci_devs.h> + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define PCH_DEV_SMBUS dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)) +#else + +#include <device/pci_type.h> +#define PCH_DEV_SMBUS PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC) +#endif + +#define HOSTC 0x40 +#define HST_EN (1 << 0) + +void smbus_common_init(void); + +#endif /* _SOC_SMBUS_H_ */ diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ca1eb40..6a0226e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -40,6 +40,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/smbus.h> #include <soc/smm.h> #include <soc/spi.h> #include <build.h> @@ -194,6 +195,7 @@ spi_init(); lpc_init(); + smbus_common_init(); } /* SOC initialization after RAM is enabled */ diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c new file mode 100644 index 0000000..454c3f6 --- /dev/null +++ b/src/soc/intel/braswell/smbus.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2019 3mdeb + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/early_smbus.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <southbridge/intel/common/smbus.h> + +static const struct reg_script smbus_init_script[] = { + /* Set SMBus I/O base address */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_4, SMBUS_BASE_ADDRESS), + /* Set SMBus enable */ + REG_PCI_WRITE8(HOSTC, HST_EN), + /* Enable I/O access */ + REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + /* Disable interrupts */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), + /* Clear errors */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, +}; + +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); +} + +void smbus_common_init(void) +{ + reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 Gerrit-Change-Number: 32062 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable options for wakeup
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30447 Change subject: soc/intel/cannonlake: Enable options for wakeup ...................................................................... soc/intel/cannonlake: Enable options for wakeup Cannonlake FSP silicon init have dedicated wake up capability settings for several IP, expose the selection into coreboot. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30447/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..e5a3ae1 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -302,6 +302,13 @@ /* SATA Power Optimizer */ uint8_t satapwroptimize; + + /* Wake Up Capability */ + uint8_t codec_wake_sx; + uint8_t pcie_wake_deepsx; + uint8_t wlan_wake_sx; + uint8_t wlan_wake_deepsx; + uint8_t glan_wake_deepsx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 78b27e9..9a24242 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -225,6 +225,14 @@ /* Power Optimizer */ params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + + /* Wakeup Capability */ + params->PchHdaCodecSxWakeCapability = config->codec_wake_sx; + params->PchPmWoWlanEnable = config->wlan_wake_sx; + params->PchPmPcieWakeFromDeepSx = config->pcie_wake_deepsx; + params->PchPmWoWlanDeepSxEnable = config->wlan_wake_deepsx; + params->PchPmLanWakeFromDeepSx = config->glan_wake_deepsx; + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 Gerrit-Change-Number: 30447 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size
by Michał Żygowski (Code Review) 09 May '19

09 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31419 Change subject: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size ...................................................................... src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size The default 0xc00 size of pre-CBMEM console is too small to fit whole console log from romstage. Increase the size in order to avoid log truncation when checking console with cbmem utility. The size was adjusted by compiling and running the coreboot on apu2 with SPEW loglevel. Additionally unset the SQUELCH_EARLY_SMP option to get console output between amdinitreset and amdinitearly. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 --- M src/mainboard/pcengines/apu2/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31419/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6e65a6e..3c04b05 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -113,4 +113,16 @@ int default 128 +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x3000 + help + Increase this value if preram cbmem console is getting truncated + +config SQUELCH_EARLY_SMP + bool + default n + help + When selected only the BSP CPU will output to early console. + endif # BOARD_PCENGINES_APU2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 Gerrit-Change-Number: 31419 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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