coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

1 participants
1542 discussions

Change in ...coreboot[master]: sb/intel/i82801gx: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31256 Change subject: sb/intel/i82801gx: Use big enough type for left-shift ...................................................................... sb/intel/i82801gx: Use big enough type for left-shift Change-Id: I4abe406adeee0aa5df9e4ee067b1685e2e964717 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/usb_ehci.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31256/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index f1866a5..d453809 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -243,7 +243,7 @@ // VCi Resource Control reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); + reg32 |= (1U << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map pci_write_config32(dev, 0x120, reg32); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 6679105..3c57614 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -42,7 +42,7 @@ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); + reg32 |= (1U << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); RCBA32(0x0088) = 0x0011d000; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7497c79..13380d2 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -316,7 +316,7 @@ /* Enable Clock Gating for most devices */ reg32 = RCBA32(CG); - reg32 |= (1 << 31); // LPC clock gating + reg32 |= (1U << 31); // LPC clock gating reg32 |= (1 << 30); // PATA clock gating // SATA clock gating reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index b40c83d..b58ef6b 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -36,7 +36,7 @@ pci_write_config32(dev, PCI_COMMAND, reg32); reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 31) | (1 << 27); + reg32 |= (1U << 31) | (1 << 27); pci_write_config32(dev, 0xdc, reg32); reg32 = pci_read_config32(dev, 0xfc); -- To view, visit https://review.coreboot.org/c/coreboot/+/31256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abe406adeee0aa5df9e4ee067b1685e2e964717 Gerrit-Change-Number: 31256 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: sb/intel/i82801ix/sata.c: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31411 Change subject: sb/intel/i82801ix/sata.c: Use big enough type for left-shift ...................................................................... sb/intel/i82801ix/sata.c: Use big enough type for left-shift Change-Id: If052c7af67319e6b183eb1ba21834082e1695582 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/sata.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31411/1 diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 1968694..ee2ac53 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -43,7 +43,7 @@ /* Set AHCI access mode. No other ABAR registers should be accessed before this. */ reg32 = read32(abar + 0x04); - reg32 |= (1 << 31); + reg32 |= (1UL << 31); write32(abar + 0x04, reg32); /* CAP (HBA Capabilities) : enable power management */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If052c7af67319e6b183eb1ba21834082e1695582 Gerrit-Change-Number: 31411 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30468 Change subject: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values ...................................................................... mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/packardbell/ms2290/acpi/platform.asl 1 file changed, 67 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30468/1 diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14..e3f95ed 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -90,51 +90,101 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) + } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Gerrit-Change-Number: 30468 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30469 Change subject: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values ...................................................................... mb/lenovo/x201/acpi: Update _OSI strings and OSYS values Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x201/acpi/platform.asl 1 file changed, 68 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30469/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013b..1f55624 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -111,52 +111,103 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) + } + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Gerrit-Change-Number: 30469 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/apollolake: Remove wrong comment on stddef.h
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31910 Change subject: soc/intel/apollolake: Remove wrong comment on stddef.h ...................................................................... soc/intel/apollolake: Remove wrong comment on stddef.h Change-Id: I4305ef052ff74a6a19977327c9b60b2a1282e028 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/meminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31910/1 diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 038fa9f..0f6506b 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -17,7 +17,7 @@ #include <fsp/util.h> #include <memory_info.h> #include <soc/meminit.h> -#include <stddef.h> /* required for FspmUpd.h */ +#include <stddef.h> #include <fsp/soc_binding.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4305ef052ff74a6a19977327c9b60b2a1282e028 Gerrit-Change-Number: 31910 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: WIP: Make common macros double-evaluation safe
by Julius Werner (Code Review) 18 Apr '19

18 Apr '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32027 Change subject: WIP: Make common macros double-evaluation safe ...................................................................... WIP: Make common macros double-evaluation safe Just shaking the Jenkins tree to see what falls out for now... Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d --- M payloads/libpayload/include/compiler.h M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/stdlib.h M src/commonlib/include/commonlib/compiler.h M src/commonlib/include/commonlib/helpers.h 5 files changed, 113 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32027/1 diff --git a/payloads/libpayload/include/compiler.h b/payloads/libpayload/include/compiler.h index a830239..4ca9bad 100644 --- a/payloads/libpayload/include/compiler.h +++ b/payloads/libpayload/include/compiler.h @@ -26,4 +26,18 @@ #define __always_unused __attribute__((unused)) #define __must_check __attribute__((warn_unused_result)) +/* This evaluates to the first expression, unless that is constant in which case + it evalutates to the second. This is useful to write typeof() macros in a way + that they don't get hung up on the type of literal expressions (e.g. compare + an integer literal which is signed by default with a size_t variable). It is + generally a safe thing to do because if the constant doesn't fit into the + chosen type, you'll get a -Werror=overflow at compile time. */ +#define __SELECT_NON_CONST(expr, fallback_expr) __builtin_choose_expr( \ + __builtin_constant_p(expr), fallback_expr, expr) + +/* This creates a unique local variable name for use in macros. */ +#define __TMPNAME_3(i) __tmpname_##i +#define __TMPNAME_2(i) __TMPNAME_3(i) +#define __TMPNAME __TMPNAME_2(__COUNTER__) + #endif diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 0b9ab0d..c889605 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -66,10 +66,32 @@ #include <pci.h> #include <archive.h> -#define MIN(a,b) ((a) < (b) ? (a) : (b)) -#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) + +#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \ + __typeof__(__SELECT_NON_CONST(a, b)) var_a = a; \ + __typeof__(__SELECT_NON_CONST(b, a)) var_b = b; \ + var_a op var_b ? var_a : var_b; \ +}) + +#define __CMP(a, b, op) (__builtin_constant_p(a) && __builtin_constant_p(b) ? \ + __CMP_UNSAFE(a, b, op) : __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) + +#define MIN(a, b) __CMP(a, b, <) +#define MAX(a, b) __CMP(a, b, >) + +/* __typeof__ doesn't work on bitfield members, so provide these alternatives */ +#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <) +#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >) + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#define DIV_ROUND_UP(x, y) ({ \ + __typeof__(x) _div_local_x = x; \ + __typeof__(y) _div_local_y = y; \ + ((_div_local_x) + (_div_local_y) - 1) / (_div_local_y); \ +}) + static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; } #define LITTLE_ENDIAN 1234 diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index aaacc87..0b42ce2 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -35,8 +35,12 @@ #include <stddef.h> #include <string.h> +#define __ALIGN_MASK(x, mask) ({ \ + typeof(mask) _align_mask_local_mask = mask; \ + ((x) + _align_mask_local_mask) & ~_align_mask_local_mask; \ +}) + #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x,a) ALIGN((x),(a)) #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) #define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) diff --git a/src/commonlib/include/commonlib/compiler.h b/src/commonlib/include/commonlib/compiler.h index 2e0c454..e3d0f95 100644 --- a/src/commonlib/include/commonlib/compiler.h +++ b/src/commonlib/include/commonlib/compiler.h @@ -48,4 +48,18 @@ #define __always_inline inline __attribute__((always_inline)) #endif +/* This evaluates to the first expression, unless that is constant in which case + it evalutates to the second. This is useful to write typeof() macros in a way + that they don't get hung up on the type of literal expressions (e.g. compare + an integer literal which is signed by default with a size_t variable). It is + generally a safe thing to do because if the constant doesn't fit into the + chosen type, you'll get a -Werror=overflow at compile time. */ +#define __SELECT_NON_CONST(expr, fallback_expr) __builtin_choose_expr( \ + __builtin_constant_p(expr), fallback_expr, expr) + +/* This creates a unique local variable name for use in macros. */ +#define __TMPNAME_3(i) __tmpname_##i +#define __TMPNAME_2(i) __TMPNAME_3(i) +#define __TMPNAME __TMPNAME_2(__COUNTER__) + #endif diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index adc43ca..65c122e 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -23,41 +23,76 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #endif +#define __ALIGN_MASK(x, mask) ({ \ + __typeof__(mask) _align_mask_local_mask = mask; \ + ((x) + _align_mask_local_mask) & ~_align_mask_local_mask; \ +}) + #define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL) -#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x, a) ALIGN((x), (a)) #define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL)) #define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0) +#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) + +#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \ + __typeof__(__SELECT_NON_CONST(a, b)) var_a = a; \ + __typeof__(__SELECT_NON_CONST(b, a)) var_b = b; \ + var_a op var_b ? var_a : var_b; \ +}) + +#define __CMP(a, b, op) __builtin_choose_expr( \ + __builtin_constant_p(a) && __builtin_constant_p(b), \ + __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) + #ifndef MIN -#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MIN(a, b) __CMP(a, b, <) #endif #ifndef MAX -#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MAX(a, b) __CMP(a, b, >) #endif -#define ABS(a) (((a) < 0) ? (-(a)) : (a)) -#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) -#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) -#define SWAP(a, b) do { \ - typeof(a) tmp = a; \ - a = (typeof(a)) b; \ - b = (typeof(b)) tmp; \ - } while (0) + +/* __typeof__ doesn't work on bitfield members, so provide these alternatives */ +#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <) +#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >) + +#define ABS(a) ({ \ + __typeof__(a) _abs_local_a = a; \ + ((_abs_local_a) < 0) ? (-(_abs_local_a)) : (_abs_local_a); \ +}) + +#define IS_POWER_OF_2(x) ({ \ + __typeof__(x) _power_local_x = x; \ + ((_power_local_x) & ((_power_local_x) - 1)) == 0; \ +}) + +#define DIV_ROUND_UP(x, y) ({ \ + __typeof__(x) _div_local_x = x; \ + __typeof__(y) _div_local_y = y; \ + ((_div_local_x) + (_div_local_y) - 1) / (_div_local_y); \ +}) + +#define SWAP(a, b) do { \ + __typeof__(&a) _swap_local_a = &a; \ + __typeof__(&b) _swap_local_b = &b; \ + __typeof__(a) _swap_local_tmp = *_swap_local_a; \ + *_swap_local_a = *_swap_local_b; \ + *_swap_local_b = _swap_local_tmp; \ +} while (0) + /* * Divide positive or negative dividend by positive divisor and round * to closest integer. Result is undefined for negative divisors and * for negative dividends if the divisor variable type is unsigned. */ -#define DIV_ROUND_CLOSEST(x, divisor)( \ -{ \ - typeof(x) __x = x; \ - typeof(divisor) __d = divisor; \ - (((typeof(x))-1) > 0 || \ - ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ - (((__x) + ((__d) / 2)) / (__d)) : \ - (((__x) - ((__d) / 2)) / (__d)); \ -} \ -) +#define DIV_ROUND_CLOSEST(x, divisor)({ \ + __typeof__(x) _div_local_x = x; \ + __typeof__(divisor) _div_local_d = divisor; \ + (((__typeof__(x))-1) > 0 || \ + ((__typeof__(divisor))-1) > 0 || (_div_local_x) > 0) ? \ + (((_div_local_x) + ((_div_local_d) / 2)) / (_div_local_d)) : \ + (((_div_local_x) - ((_div_local_d) / 2)) / (_div_local_d)); \ +}) /* Standard units. */ #define KiB (1<<10) -- To view, visit https://review.coreboot.org/c/coreboot/+/32027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d Gerrit-Change-Number: 32027 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 30

Change in ...coreboot[master]: soc/intel/cnl: Generate ACPI DMAR table
by John Zhao (Code Review) 18 Apr '19

18 Apr '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31917 Change subject: soc/intel/cnl: Generate ACPI DMAR table ...................................................................... soc/intel/cnl: Generate ACPI DMAR table SoC is detected Vt-d capable. ACPI DMAR table is created and DMA-remapping hardware units entries are programmed. Device scope like IOAPIC and HPET will be added once cnl fsp upd update is available. Change-Id: I4e1ee5244c67affb13947436d81628c5dc665c9e Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/systemagent.h M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/systemagent.c M src/soc/intel/cannonlake/systemagent.c 8 files changed, 157 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31917/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 639f6c6..864cbe9 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -17,19 +17,22 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> #include <chip.h> +#include <device/mmio.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> +#include <intelblocks/p2sb.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/systemagent.h> #include <string.h> #include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> @@ -285,3 +288,78 @@ { return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); } + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; + + /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ + if (igfx_dev && igfx_dev->enabled && gfxvten && + gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; + + /* General VTBAR has to be set and in 32-bit space. */ + if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; + + /* P2SB may already be hidden. There's no clear rule, when. */ + const u8 p2sb_hidden = + pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); + + const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *dev, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + const struct soc_intel_cannonlake_config *const config = dev->chip_info; + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* Create DMAR table only if we have Vt-d capability */ + if ((config && config->ignore_vtd) || !soc_is_vtd_capable()) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 993e7f3..050e026 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -196,6 +196,7 @@ .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = &sa_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3e4bafc..1574b8e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -221,6 +221,9 @@ /* Estimated maximum platform power in Watts */ uint16_t psys_pmax; + /* Whether to ignore VT-d support of the SKU */ + int ignore_vtd; + /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; /* Enable VR specific mailbox command diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index ed9b29f..100bd11 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -52,6 +52,15 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfc000000 #define REG_BASE_SIZE 0x1000 diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h index da83c38..390bd56 100644 --- a/src/soc/intel/cannonlake/include/soc/systemagent.h +++ b/src/soc/intel/cannonlake/include/soc/systemagent.h @@ -30,10 +30,15 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) -#define BIOS_RESET_CPL 0x5da8 -#define EDRAMBAR 0x5408 -#define REGBAR 0x5420 +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define IPUVTBAR 0x7884 +#define VTVC0BAR 0x5410 +#define REGBAR 0x5420 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 @@ -43,4 +48,11 @@ #define IMRBASE 0x6A40 #define IMRLIMIT 0x6A48 +bool soc_is_vtd_capable(void); + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; #endif diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5597c4f..04a24a1 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -98,6 +98,7 @@ assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *t_cfg = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg, config); @@ -109,6 +110,15 @@ /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; + /* Enable VT-d and X2APIC */ + if (!config->ignore_vtd) { + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->X2ApicOptOut = 0; + t_cfg->VtdDisable = 0; + } + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c index 61db22e..6fb3917 100644 --- a/src/soc/intel/cannonlake/romstage/systemagent.c +++ b/src/soc/intel/cannonlake/romstage/systemagent.c @@ -16,10 +16,31 @@ */ #include <device/device.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/systemagent.h> +#include "chip.h" + +static void systemagent_vtd_init(void) +{ + const struct device *const dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct soc_intel_cannonlake_config *config = NULL; + + if (dev) + config = dev->chip_info; + if (config && config->ignore_vtd) + return; + + const bool vtd_capable = + !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + if (!vtd_capable) + return; + + sa_set_mch_bar(soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); +} void systemagent_early_init(void) { @@ -40,6 +61,9 @@ /* Set Fixed MMIO address into MCH base address */ sa_set_mch_bar(soc_fixed_mch_resources, ARRAY_SIZE(soc_fixed_mch_resources)); + + systemagent_vtd_init(); + /* Enable PAM registers */ enable_pam_region(); } diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 9c8d761..4ff4c1c 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -18,10 +18,19 @@ #include <device/device.h> #include <delay.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/systemagent.h> +#include "chip.h" + +bool soc_is_vtd_capable(void) +{ + struct device *const root_dev = SA_DEV_ROOT; + return root_dev && + !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); +} /* * SoC implementation @@ -31,6 +40,8 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { + const struct soc_intel_cannonlake_config *const config = dev->chip_info; + static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -54,6 +65,11 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) { + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); + } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/31917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1ee5244c67affb13947436d81628c5dc665c9e Gerrit-Change-Number: 31917 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

6 35

Change in ...coreboot[master]: nb/intel/sandybridge: Move southbridge code to bd82x6x
by Patrick Rudolph (Code Review) 18 Apr '19

18 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32035 Change subject: nb/intel/sandybridge: Move southbridge code to bd82x6x ...................................................................... nb/intel/sandybridge: Move southbridge code to bd82x6x Move the southbridge code to bd82x6x folder similar to the lynxpoint implementation. Untested. Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 4 files changed, 40 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/32035/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index ad579c6..b923065 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -27,20 +27,6 @@ static void sandybridge_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index b49165c..6112c76 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,9 +28,8 @@ #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> -static void early_pch_init(void) +static void early_pch_reset_pmcon(void) { u8 reg8; @@ -55,13 +54,8 @@ if (bist == 0) enable_lapic(); - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); + /* Init LPC, GPIO, BARs, disable watchdog ... */ + early_pch_init(); /* Initialize superio */ mainboard_config_superio(); @@ -100,7 +94,7 @@ post_code(0x3b); /* Perform some initialization that must run before stage2 */ - early_pch_init(); + early_pch_reset_pmcon(); post_code(0x3c); southbridge_configure_default_intmap(); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 23942fe..7fbc732 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -19,6 +19,8 @@ #include <ip_checksum.h> #include <device/pci_def.h> #include <delay.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> #include "pch.h" /* For DMI bar. */ @@ -368,3 +370,36 @@ init_dmi(); } + +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + printk(BIOS_DEBUG, " done.\n"); +} + +void early_pch_init(void) +{ + pch_enable_lpc(); + + pch_enable_bars(); + + pch_generic_setup(); + + setup_pch_gpios(&mainboard_gpio_map); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 67b0d11..0097e15 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -77,6 +77,7 @@ void mainboard_rcba_config(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void); +void early_pch_init(void); struct southbridge_usb_port { -- To view, visit https://review.coreboot.org/c/coreboot/+/32035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93 Gerrit-Change-Number: 32035 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: Kconfig: Remove unused MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID}
by HAOUAS Elyes (Code Review) 16 Apr '19

16 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32101 Change subject: Kconfig: Remove unused MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} ...................................................................... Kconfig: Remove unused MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} Change-Id: I6ad986c69c51aff8e7e49e31ffa130ff14e9a50e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/aopen/dxplplusu/Kconfig M src/mainboard/apple/macbookair4_2/Kconfig M src/mainboard/asrock/b75pro3-m/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/asus/h61m-cs/Kconfig M src/mainboard/asus/maximus_iv_gene-z/Kconfig M src/mainboard/asus/p8h61-m_lx/Kconfig M src/mainboard/asus/p8h61-m_pro/Kconfig M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/hp/2570p/Kconfig M src/mainboard/hp/2760p/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8470p/Kconfig M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/folio_9470m/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/intel/dcp847ske/Kconfig M src/mainboard/kontron/ktqm77/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/sapphire/pureplatinumh61/Kconfig M src/mainboard/supermicro/x10slm-f/Kconfig M util/autoport/bd82x6x.go 38 files changed, 0 insertions(+), 304 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32101/1 diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 3a729ce..905ddd5 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -33,12 +33,4 @@ hex default 0x4000 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x0 - endif # BOARD_AOPEN_DXPLPLUSU diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 9d4047d..82f120a 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -31,14 +31,6 @@ string default "8086,0116" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x7270 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig index 5fc3c5e..8db0eba 100644 --- a/src/mainboard/asrock/b75pro3-m/Kconfig +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -37,14 +37,6 @@ string default "B75 Pro3-M" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x1e49 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1849 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 55f1637..db2768d 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -56,14 +56,6 @@ string default "H81M-HDS" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x8c5c - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1849 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/h61m-cs/Kconfig b/src/mainboard/asus/h61m-cs/Kconfig index d21c761..60dafda 100644 --- a/src/mainboard/asus/h61m-cs/Kconfig +++ b/src/mainboard/asus/h61m-cs/Kconfig @@ -25,14 +25,6 @@ string default "H61M-CS" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig index 92d7840..a0bc318 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -46,14 +46,6 @@ string default "8086,0112" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index cc2f8a9..010641a 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -43,14 +43,6 @@ string default "P8H61-M LX" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 4d24187..cdd70d0 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -47,14 +47,6 @@ string default "8086,0152" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index 0bfde49..ff697b9 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -28,14 +28,6 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x7270 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config DRAM_RESET_GATE_GPIO # FIXME: check this int default 60 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 5fba47a..5e46365 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -40,14 +40,6 @@ string default "GA-H61M-S2PV" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x5001 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1458 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 570a1b3..24797be 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -40,14 +40,6 @@ string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - config MAINBOARD_VENDOR string default "Hewlett-Packard" diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index f2c9b20..1a31da7 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -41,12 +41,4 @@ string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - endif # BOARD_GOOGLE_PARROT diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index c9b67cc..8b3eb0f 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -43,12 +43,4 @@ string default "8086,0156" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - endif # BOARD_GOOGLE_STOUT diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig index f9da619..ff91e4d 100644 --- a/src/mainboard/hp/2570p/Kconfig +++ b/src/mainboard/hp/2570p/Kconfig @@ -49,14 +49,6 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x17df - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index af3e31b..ab29836 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -49,14 +49,6 @@ string default "8086,0116" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x162a - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index ca737ea..ca97cd6 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -52,14 +52,6 @@ string default "8086,0116" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x161c - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/8470p/Kconfig b/src/mainboard/hp/8470p/Kconfig index d8bf5ec..f23c02f 100644 --- a/src/mainboard/hp/8470p/Kconfig +++ b/src/mainboard/hp/8470p/Kconfig @@ -50,14 +50,6 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x179b - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index c60283d..6752085 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -41,14 +41,6 @@ string default "EliteBook 8770w" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x176c - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index c4b9d6d..cbfb0ed 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -35,14 +35,6 @@ string default "8086,0102" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x1495 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index f65aeed..06ca793 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -35,14 +35,6 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x18df - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index a08a9e5..475e978 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -37,14 +37,6 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x18f8 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config DRAM_RESET_GATE_GPIO # FIXME: check this int default 60 diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index dd7f1ca..b1c7bab 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -41,14 +41,6 @@ string default "8086,0106" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x2044 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config MAX_CPUS int default 2 diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index b85d938..043eb01 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -31,14 +31,6 @@ string default "pci8086,0166.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x0000 # TODO - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x0000 # TODO - config MAINBOARD_VENDOR string default "Kontron" diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index a807316..4495d79 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -34,14 +34,6 @@ string default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21dd - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 714f13f..9200ad5 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -52,12 +52,4 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x2205 - endif # BOARD_LENOVO_S230U diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index f40e9c0..ce81907 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -56,14 +56,6 @@ string default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21ce - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 71b94af..c5efb55 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -55,14 +55,6 @@ string default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21d2 - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 687edea..dbeaadb 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -38,14 +38,6 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21f3 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 47ff441..bad1837 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -60,15 +60,6 @@ string default "pci8086,0166.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fb if BOARD_LENOVO_T430S - default 0x2208 if BOARD_LENOVO_T431S - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c414083..06f296b 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -65,14 +65,6 @@ string default "pci8086,0126.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21cf - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 14f9fb2..b36460d 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -62,14 +62,6 @@ default "pci8086,0106.rom" if BOARD_LENOVO_T530 default "pci8086,0166.rom" if BOARD_LENOVO_W530 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 2f936a9..e7da8d0 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -37,12 +37,4 @@ int default 2 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fe - endif # BOARD_LENOVO_X131E diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 202fabd..520853c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -54,12 +54,4 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - endif # BOARD_LENOVO_X1_CARBON_GEN1 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 70245d2..16f42e8 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -69,13 +69,4 @@ default "8086,0116" if BOARD_LENOVO_X220I default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21db if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I - default 0x21e8 if BOARD_LENOVO_X1 - endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 3ec537a..5b34b83 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -55,12 +55,4 @@ string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - endif # BOARD_LENOVO_X230 diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index 85b2f36..13a93c5 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -32,14 +32,6 @@ string default "8086,0162" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x1007 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x174b - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 6bf0b2a..430bed3 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -44,14 +44,6 @@ string default "X10SLM+-F" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x0803 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x15d9 - config MAX_CPUS int default 8 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 265cb6f..a97ff1d 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -181,12 +181,6 @@ } KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" - /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. - But most systems don't have any of those. But the config needs to be set - nevertheless. So set it to southbridge subsys/subvendor. */ - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) - ich9GetFlashSize(ctx) DSDTDefines = append(DSDTDefines, -- To view, visit https://review.coreboot.org/c/coreboot/+/32101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ad986c69c51aff8e7e49e31ffa130ff14e9a50e Gerrit-Change-Number: 32101 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 14

Change in ...coreboot[master]: soc/intel/cannonlake: Vmx support based on Kconfig
by Ronak Kanabar (Code Review) 16 Apr '19

16 Apr '19

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32117 Change subject: soc/intel/cannonlake: Vmx support based on Kconfig ...................................................................... soc/intel/cannonlake: Vmx support based on Kconfig Change VmxEnable UPD values based on Kconfig ENABLE_VMX and remove it from Devicetree. Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32117/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 6f167c2..90b92a7 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -22,7 +22,6 @@ register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 2714b60..5b88dfc 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -26,7 +26,6 @@ register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ffdcee4..235cda8 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -65,7 +65,7 @@ if (config->VtdDisable) m_cfg->VmxEnable = 0; else - m_cfg->VmxEnable = config->VmxEnable; + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/32117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba Gerrit-Change-Number: 32117 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

8 12

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2019