coreboot-gerrit February 2019

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Change in ...coreboot[master]: src: Use macro `ACPI_FADT_LEGACY_FREE`
by Paul Menzel (Code Review) 15 Feb '19

15 Feb '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31289 Change subject: src: Use macro `ACPI_FADT_LEGACY_FREE` ...................................................................... src: Use macro `ACPI_FADT_LEGACY_FREE` Replace all instances, where 0 is used by the macro/define `ACPI_FADT_LEGACY_FREE`. Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/lenovo/t400/fadt.c M src/mainboard/lenovo/x200/fadt.c M src/mainboard/roda/rk9/fadt.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/skylake/acpi.c M src/southbridge/nvidia/ck804/fadt.c M src/southbridge/nvidia/mcp55/fadt.c 8 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31289/1 diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 99184ca..6fdc77f 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -92,7 +92,7 @@ fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index ab257f8..31336db 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -71,7 +71,7 @@ fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index ab257f8..31336db 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -71,7 +71,7 @@ fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index ab257f8..31336db 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -71,7 +71,7 @@ fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 71aa0a3..aa572ea 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -222,7 +222,7 @@ fadt->day_alrm = 0x0D; fadt->mon_alrm = 0x00; fadt->century = 0x00; - fadt->iapc_boot_arch = 0; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index f6eb659..3ad1e50 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -275,7 +275,7 @@ fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; - fadt->iapc_boot_arch = 0; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; if (!IS_ENABLED(CONFIG_NO_FADT_8042)) fadt->iapc_boot_arch |= ACPI_FADT_8042; diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c index ee9db2f..fb4cbb6 100644 --- a/src/southbridge/nvidia/ck804/fadt.c +++ b/src/southbridge/nvidia/ck804/fadt.c @@ -82,7 +82,7 @@ fadt->day_alrm = 0x7d; fadt->mon_alrm = 0x7e; fadt->century = 0x32; - fadt->iapc_boot_arch = 0; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags = 0xa5; #ifdef LONG_FADT diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index 8064b12..f1d6e9d 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -93,7 +93,7 @@ fadt->mon_alrm = 0x7e; fadt->century = 0x32; - fadt->iapc_boot_arch = 0x0; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags = 0x4a5; fadt->reset_reg.space_id = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74 Gerrit-Change-Number: 31289 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]mb/google: Remove TOL_1V8 setting for pads in GPP_F
by Kane Chen (Code Review) 15 Feb '19

15 Feb '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31368 Change subject: [WIP]mb/google: Remove TOL_1V8 setting for pads in GPP_F ...................................................................... [WIP]mb/google: Remove TOL_1V8 setting for pads in GPP_F Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nautilus/gpio.c M src/mainboard/google/poppy/variants/soraka/gpio.c 5 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/1 diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index 4cd3865..7ea5c6f 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -193,9 +193,9 @@ /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NC(GPP_F8), /* I2C4_SCL */ PAD_CFG_NC(GPP_F9), -/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, +/* I2C5_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ -/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, +/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ /* EMMC_CMD */ PAD_CFG_NC(GPP_F12), /* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index c731b52..c007b7f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -268,21 +268,21 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* F12 : EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 */ diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index cd7e0ca..6d45c73 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -265,13 +265,13 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> I2C_2_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> I2C_3_SDA */ - PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> I2C_3_SCL */ - PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */ PAD_CFG_NC(GPP_F8), /* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */ diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 4f80e2f..9fa8748 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -259,13 +259,13 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */ - PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_F6, 5K_PU, DEEP, NF1), /* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */ - PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_F7, 5K_PU, DEEP, NF1), /* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */ diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 0e24bb7..25240f0 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -268,21 +268,21 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* F12 : EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Gerrit-Change-Number: 31368 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Define VR settings
by Roy Mingi Park (Code Review) 15 Feb '19

15 Feb '19

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31405 Change subject: soc/intel/cannonlake: Define VR settings ...................................................................... soc/intel/cannonlake: Define VR settings Define VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31405/1 diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index fff68c7..25270d8 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -19,7 +19,54 @@ #include <soc/vr_config.h> static const struct vr_config default_configs[NUM_VR_DOMAINS] = { - /* TODO: define this*/ + [VR_SYSTEM_AGENT] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + }, + [VR_IA_CORE] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + }, + [VR_GT_UNSLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, + [VR_GT_SLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, }; void fill_vr_domain_config(void *params, -- To view, visit https://review.coreboot.org/c/coreboot/+/31405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2 Gerrit-Change-Number: 31405 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Fix USB ACPI configuration for CNVi BT module
by Karthik Ramasubramanian (Code Review) 15 Feb '19

15 Feb '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31387 to review the following change. Change subject: mb/google/octopus: Fix USB ACPI configuration for CNVi BT module ...................................................................... mb/google/octopus: Fix USB ACPI configuration for CNVi BT module CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix the device configuration in the devicetree. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31387/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 1d36b53..e134aa2 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -158,7 +158,7 @@ register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" - device usb 2.9 on end + device usb 2.8 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/31387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14 Gerrit-Change-Number: 31387 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: cpu/intel/speedstep: Add Netburst
by HAOUAS Elyes (Code Review) 15 Feb '19

15 Feb '19

Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/22604 to look at the new patch set (#71). Change subject: cpu/intel/speedstep: Add Netburst ...................................................................... cpu/intel/speedstep: Add Netburst CPUs Netburst CPUs hang if we read MSR_PLATFORM_INFO or MSR_EXTENDED_CONFIG. The maximum bus ratio can be read in MSR_PERF_STAT[44:40] Tested with P4 (CPUID F65) on 945G-M4 board. Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/speedstep/speedstep.c 1 file changed, 51 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/22604/71 -- To view, visit https://review.coreboot.org/c/coreboot/+/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 71 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/intel/speedstep: Add Netburst
by Kyösti Mälkki (Code Review) 15 Feb '19

15 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22604 ) Change subject: cpu/intel/speedstep: Add Netburst ...................................................................... Patch Set 70: (1 comment) https://review.coreboot.org/#/c/22604/70/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/70/src/cpu/intel/speedstep/speedstep.… PS70, Line 113: params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM; Wrong indent. I thing this all would be cleaner constructed with if () instead of nested switch(), but cannot tell for sure before seeing. -- To view, visit https://review.coreboot.org/c/coreboot/+/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 70 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Feb 2019 16:03:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/speedstep: Add Netburst
by HAOUAS Elyes (Code Review) 15 Feb '19

15 Feb '19

Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/22604 to look at the new patch set (#70). Change subject: cpu/intel/speedstep: Add Netburst ...................................................................... cpu/intel/speedstep: Add Netburst CPUs Netburst CPUs hang if we read MSR_PLATFORM_INFO or MSR_EXTENDED_CONFIG. The maximum bus ratio can be read in MSR_PERF_STAT[44:40] Tested with P4 (CPUID F65) on 945G-M4 board. Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/speedstep/speedstep.c 1 file changed, 46 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/22604/70 -- To view, visit https://review.coreboot.org/c/coreboot/+/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 70 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/intel/speedstep: Add Netburst
by Patrick Rudolph (Code Review) 15 Feb '19

15 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22604 ) Change subject: cpu/intel/speedstep: Add Netburst ...................................................................... Patch Set 69: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/22604/69/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/69/src/cpu/intel/speedstep/speedstep.… PS69, Line 42: u8 msr_extended_config_supported = c.x86 != 0xf; const bool -- To view, visit https://review.coreboot.org/c/coreboot/+/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 69 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Feb 2019 14:12:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Patrick Rudolph (Code Review) 15 Feb '19

15 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/30500/1/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S: https://review.coreboot.org/#/c/30500/1/src/arch/x86/exit_car.S@110 PS1, Line 110: pop %rbx > Just curious, are you forced to use %rbx instead of %eax here. […] yes 64bit is fine, it holds both the maximum variable mtrrs and the count of mtrrs to pop from stack https://review.coreboot.org/#/c/30500/1/src/arch/x86/exit_car.S@111 PS1, Line 111: test %rbx, %rbx > Can't you test %ebx? For all except pop's below, why use 64bit register mnemonics %rax when %eax sho […] Ack https://review.coreboot.org/#/c/30500/1/src/arch/x86/exit_car.S@114 PS1, Line 114: xor %rbx, %rbx > %rdx ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Feb 2019 14:09:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Set ELAN as the default for touch panel
by Chris Zhou (Code Review) 15 Feb '19

15 Feb '19

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31430 Change subject: mb/google/sarien: Set ELAN as the default for touch panel ...................................................................... mb/google/sarien: Set ELAN as the default for touch panel According to request of comment 35, setting ELAN as the default. BUG=b:122019253 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945 --- M src/mainboard/google/sarien/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/31430/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 4aea9f7..a976d36 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -100,7 +100,7 @@ config TOUCHSCREEN_HID string "Specify the touchscreen HID enabled for the OS" default "WCOM48E2" if BOARD_GOOGLE_ARCADA - default "NONE" if BOARD_GOOGLE_SARIEN + default "ELAN900C" if BOARD_GOOGLE_SARIEN config VBOOT select HAS_RECOVERY_MRC_CACHE -- To view, visit https://review.coreboot.org/c/coreboot/+/31430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945 Gerrit-Change-Number: 31430 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019