coreboot-gerrit February 2019

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Change in ...coreboot[master]: SMBIOS: Add new MEMORY_{TYPE,ECHNOLOGY,OPERATING} macros
by HAOUAS Elyes (Code Review) 15 Feb '19

15 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31423 Change subject: SMBIOS: Add new MEMORY_{TYPE,ECHNOLOGY,OPERATING} macros ...................................................................... SMBIOS: Add new MEMORY_{TYPE,ECHNOLOGY,OPERATING} macros Change-Id: I4e466614d0a9e8c89f298594a5785af775b22a95 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31423/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 7e24907..463b64e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -83,6 +83,21 @@ #define MEMORY_TYPE_DETAIL_NON_VOLATILE (1 << 12) #define MEMORY_TYPE_DETAIL_REGISTERED (1 << 13) #define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) +#define MEMORY_TYPE_DETAIL_LRDIMM (1 << 15) + +#define MEMORY_TECHNOLOGY_OTHER 0x01 +#define MEMORY_TECHNOLOGY_UNKNOWN 0x02 +#define MEMORY_TECHNOLOGY_DRAM 0x03 +#define MEMORY_TECHNOLOGY_NVDIMM_N 0x04 +#define MEMORY_TECHNOLOGY_NVDIMM_F 0x05 +#define MEMORY_TECHNOLOGY_NVDIMM_P 0x06 +#define MEMORY_TECHNOLOGY_INTEL_PERSISTENT_MEMORY 0x07 + +#define MEMORY_OPERATING_MODE_CAP_OTHER (1 << 1) +#define MEMORY_OPERATING_MODE_CAP_UNKNOWN (1 << 2) +#define MEMORY_OPERATING_MODE_CAP_VOLATILE (1 << 3) +#define MEMORY_OPERATING_MODE_CAP_BYTE_ACCESS_PERSISTENT (1 << 4) +#define MEMORY_OPERATING_MODE_CAP_BLOCK_ACCESS_PERSISTENT (1 << 5) typedef enum { MEMORY_BUS_WIDTH_8 = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/31423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e466614d0a9e8c89f298594a5785af775b22a95 Gerrit-Change-Number: 31423 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: include/smbios.h: Align values for readability
by HAOUAS Elyes (Code Review) 15 Feb '19

15 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31422 Change subject: include/smbios.h: Align values for readability ...................................................................... include/smbios.h: Align values for readability Change-Id: I362292e95557586e0e24a62a12a9ccc98143ef9c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31422/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 14badbc..7e24907 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,18 +52,18 @@ const char *smbios_mainboard_family(void); #endif -#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) -#define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) -#define BIOS_CHARACTERISTICS_PNP (1 << 9) -#define BIOS_CHARACTERISTICS_APM (1 << 10) -#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) -#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) -#define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) -#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) -#define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) +#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) +#define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) +#define BIOS_CHARACTERISTICS_PNP (1 << 9) +#define BIOS_CHARACTERISTICS_APM (1 << 10) +#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) +#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) +#define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) +#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) +#define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) -#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) -#define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) +#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) +#define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) #define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING (1 << 3) #define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING (1 << 4) -- To view, visit https://review.coreboot.org/c/coreboot/+/31422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I362292e95557586e0e24a62a12a9ccc98143ef9c Gerrit-Change-Number: 31422 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard
by Felix Singer (Code Review) 15 Feb '19

15 Feb '19

Hello Paul Menzel, Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28640 to look at the new patch set (#85). Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... mb/clevo/n130wu: Add mainboard Devices: - N130WU / N131WU Working: - Compiling - Seabios, iPXE - NVMe, SATA3, booting from SSD into Arch Linux - USB2, USB3 - Graphics, mDP, HDMI - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux Works, but needs testing: - Thunderbolt WIP: - Documentation Not working: - EC ACPI Untested: - Virtualization Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A Documentation/mainboard/clevo/index.md A Documentation/mainboard/clevo/n130wu/index.md A Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg M Documentation/mainboard/index.md A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/kbl-u/Kconfig A src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/Makefile.inc A src/mainboard/clevo/kbl-u/acpi/ec.asl A src/mainboard/clevo/kbl-u/acpi/superio.asl A src/mainboard/clevo/kbl-u/acpi_tables.c A src/mainboard/clevo/kbl-u/board_info.txt A src/mainboard/clevo/kbl-u/dsdt.asl A src/mainboard/clevo/kbl-u/gpio.h A src/mainboard/clevo/kbl-u/hda_verb.c A src/mainboard/clevo/kbl-u/pei_data.c A src/mainboard/clevo/kbl-u/pei_data.h A src/mainboard/clevo/kbl-u/ramstage.c A src/mainboard/clevo/kbl-u/romstage.c A src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt A src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 22 files changed, 1,286 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28640/85 -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 85 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Documentation: Add KASAN to the project ideas list
by Werner Zeh (Code Review) 15 Feb '19

15 Feb '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31414 Change subject: Documentation: Add KASAN to the project ideas list ...................................................................... Documentation: Add KASAN to the project ideas list Adding the Kernel Address Sanitizer feature to coreboot would help to find bugs. Change-Id: If00010e81147ec50e037678230df17c6888e40a2 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31414/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 0a39a88..1c23cc6 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -72,3 +72,22 @@ hardware is available. ### Mentors + +## Add Kernel Address Sanitizer functionality to coreboot +The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector. +The idea is to check every memory access (variables) for its validity +during runtime and find bugs like stack overflow or out-of-bounds accesses. +Implementing this stub into coreboot like "Undefined behavior sanitizer support" +would help to ensure code quality and make the runtime code more robust. + +### Requirements +* knowledge in the coreboot build system and the concept of stages +* the KASAN feature can be improved in a way so that the memory space needed + during runtime is not on a fixed address provided during compile time but + determined during runtime. For this to achieve a small patch to the GCC will + be helpful. Therefore minor GCC knowledge would be beneficial. +* Implementation can be initially done in QEMU and improved on different + mainboards and platforms + +### Mentors +* Werner Zeh <werner.zeh(a)gmx.net> -- To view, visit https://review.coreboot.org/c/coreboot/+/31414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If00010e81147ec50e037678230df17c6888e40a2 Gerrit-Change-Number: 31414 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common: Move PI refcode loader
by Kyösti Mälkki (Code Review) 15 Feb '19

15 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31318 Change subject: soc/amd/common: Move PI refcode loader ...................................................................... soc/amd/common: Move PI refcode loader The moved functions are only about locating and loading the refcode blobs. Separate them from the actual calls into the blob. Eventually previous binaryPI blobs should be unified share same loader code. Change-Id: I68885e7f855b195c178e746c8f3f0f49166d0def Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/Makefile.inc M src/soc/amd/common/block/pi/agesawrapper.c A src/soc/amd/common/block/pi/refcode_loader.c 3 files changed, 160 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/31318/1 diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc index ba08123..5afbb3e 100644 --- a/src/soc/amd/common/block/pi/Makefile.inc +++ b/src/soc/amd/common/block/pi/Makefile.inc @@ -4,6 +4,7 @@ romstage-y += def_callouts.c romstage-y += heapmanager.c romstage-y += image.c +romstage-y += refcode_loader.c ramstage-y += agesawrapper.c ramstage-y += amd_late_init.c @@ -11,5 +12,6 @@ ramstage-y += def_callouts.c ramstage-y += heapmanager.c ramstage-y += image.c +ramstage-y += refcode_loader.c endif diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index a57ac4f..07461b8 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -14,14 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <arch/acpi.h> -#include <cpu/x86/mtrr.h> -#include <cbfs.h> #include <cbmem.h> #include <delay.h> -#include <rmodule.h> -#include <stage_cache.h> #include <string.h> #include <timestamp.h> #include <amdblocks/s3_resume.h> @@ -480,137 +475,3 @@ return Status; } - -static int agesa_locate_file(const char *name, struct region_device *rdev, - uint32_t type) -{ - struct cbfsf fh; - - if (cbfs_boot_locate(&fh, name, &type)) - return -1; - - cbfs_file_data(rdev, &fh); - return 0; -} - -static int agesa_locate_raw_file(const char *name, struct region_device *rdev) -{ - return agesa_locate_file(name, rdev, CBFS_TYPE_RAW); -} - -static int agesa_locate_stage_file_early(const char *name, - struct region_device *rdev) -{ - const size_t metadata_sz = sizeof(struct cbfs_stage); - - if (agesa_locate_file(name, rdev, CBFS_TYPE_STAGE)) - return -1; - - /* Peel off the cbfs stage metadata. */ - return rdev_chain(rdev, rdev, metadata_sz, - region_device_sz(rdev) - metadata_sz); -} - -static int agesa_locate_stage_file_ramstage(const char *name, - struct region_device *rdev) -{ - struct prog prog = PROG_INIT(PROG_REFCODE, name); - struct rmod_stage_load rmod_agesa = { - .cbmem_id = CBMEM_ID_REFCODE, - .prog = &prog, - }; - - if (acpi_is_wakeup_s3() && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { - printk(BIOS_INFO, "AGESA: Loading stage from cache\n"); - // There is no way to tell if this succeeded. - stage_cache_load_stage(STAGE_REFCODE, &prog); - } else { - if (prog_locate(&prog)) - return -1; - - if (rmodule_stage_load(&rmod_agesa) < 0) - return -1; - - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { - printk(BIOS_INFO, "AGESA: Saving stage to cache\n"); - stage_cache_add(STAGE_REFCODE, &prog); - } - } - - return rdev_chain(rdev, prog_rdev(&prog), 0, - region_device_sz(prog_rdev(&prog))); -} - -static int agesa_locate_stage_file(const char *name, struct region_device *rdev) -{ - if (!ENV_RAMSTAGE || !IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) - return agesa_locate_stage_file_early(name, rdev); - return agesa_locate_stage_file_ramstage(name, rdev); -} - -static const char *get_agesa_cbfs_name(void) -{ - if (!IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) - return CONFIG_AGESA_CBFS_NAME; - if (!ENV_RAMSTAGE) - return CONFIG_AGESA_PRE_MEMORY_CBFS_NAME; - return CONFIG_AGESA_POST_MEMORY_CBFS_NAME; -} - -const void *agesawrapper_locate_module(const char name[8]) -{ - const void *agesa; - const AMD_IMAGE_HEADER *image; - struct region_device rdev; - size_t file_size; - const char *fname; - int ret; - - fname = get_agesa_cbfs_name(); - - if (IS_ENABLED(CONFIG_AGESA_BINARY_PI_AS_STAGE)) - ret = agesa_locate_stage_file(fname, &rdev); - else - ret = agesa_locate_raw_file(fname, &rdev); - - if (ret) - return NULL; - - file_size = region_device_sz(&rdev); - - /* Assume boot device is memory mapped so the mapping can leak. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); - - agesa = rdev_mmap_full(&rdev); - - if (!agesa) - return NULL; - - image = amd_find_image(agesa, agesa + file_size, 4096, name); - - if (!image) - return NULL; - - return (AMD_MODULE_HEADER *)image->ModuleInfoOffset; -} - -static MODULE_ENTRY agesa_dispatcher CAR_GLOBAL; - -MODULE_ENTRY agesa_get_dispatcher(void) -{ - const AMD_MODULE_HEADER *module; - static const char id[8] = AGESA_ID; - MODULE_ENTRY val = car_get_var(agesa_dispatcher); - - if (val != NULL) - return val; - - module = agesawrapper_locate_module(id); - if (!module) - return NULL; - - val = module->ModuleDispatcher; - car_set_var(agesa_dispatcher, val); - - return val; -} diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c new file mode 100644 index 0000000..864acfd --- /dev/null +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <arch/acpi.h> +#include <cbfs.h> +#include <cbmem.h> +#include <compiler.h> +#include <rules.h> +#include <rmodule.h> +#include <stage_cache.h> +#include <amdblocks/agesawrapper.h> + +static int agesa_locate_file(const char *name, struct region_device *rdev, + uint32_t type) +{ + struct cbfsf fh; + + if (cbfs_boot_locate(&fh, name, &type)) + return -1; + + cbfs_file_data(rdev, &fh); + return 0; +} + +static int agesa_locate_raw_file(const char *name, struct region_device *rdev) +{ + return agesa_locate_file(name, rdev, CBFS_TYPE_RAW); +} + +static int agesa_locate_stage_file_early(const char *name, + struct region_device *rdev) +{ + const size_t metadata_sz = sizeof(struct cbfs_stage); + + if (agesa_locate_file(name, rdev, CBFS_TYPE_STAGE)) + return -1; + + /* Peel off the cbfs stage metadata. */ + return rdev_chain(rdev, rdev, metadata_sz, + region_device_sz(rdev) - metadata_sz); +} + +static int agesa_locate_stage_file_ramstage(const char *name, + struct region_device *rdev) +{ + struct prog prog = PROG_INIT(PROG_REFCODE, name); + struct rmod_stage_load rmod_agesa = { + .cbmem_id = CBMEM_ID_REFCODE, + .prog = &prog, + }; + + if (acpi_is_wakeup_s3() && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + printk(BIOS_INFO, "AGESA: Loading stage from cache\n"); + // There is no way to tell if this succeeded. + stage_cache_load_stage(STAGE_REFCODE, &prog); + } else { + if (prog_locate(&prog)) + return -1; + + if (rmodule_stage_load(&rmod_agesa) < 0) + return -1; + + if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + printk(BIOS_INFO, "AGESA: Saving stage to cache\n"); + stage_cache_add(STAGE_REFCODE, &prog); + } + } + + return rdev_chain(rdev, prog_rdev(&prog), 0, + region_device_sz(prog_rdev(&prog))); +} + +static int agesa_locate_stage_file(const char *name, struct region_device *rdev) +{ + if (!ENV_RAMSTAGE || !IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) + return agesa_locate_stage_file_early(name, rdev); + return agesa_locate_stage_file_ramstage(name, rdev); +} + +static const char *get_agesa_cbfs_name(void) +{ + if (!IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) + return CONFIG_AGESA_CBFS_NAME; + if (!ENV_RAMSTAGE) + return CONFIG_AGESA_PRE_MEMORY_CBFS_NAME; + return CONFIG_AGESA_POST_MEMORY_CBFS_NAME; +} + +const void *agesawrapper_locate_module(const char name[8]) +{ + const void *agesa; + const AMD_IMAGE_HEADER *image; + struct region_device rdev; + size_t file_size; + const char *fname; + int ret; + + fname = get_agesa_cbfs_name(); + + if (IS_ENABLED(CONFIG_AGESA_BINARY_PI_AS_STAGE)) + ret = agesa_locate_stage_file(fname, &rdev); + else + ret = agesa_locate_raw_file(fname, &rdev); + + if (ret) + return NULL; + + file_size = region_device_sz(&rdev); + + /* Assume boot device is memory mapped so the mapping can leak. */ + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + + agesa = rdev_mmap_full(&rdev); + + if (!agesa) + return NULL; + + image = amd_find_image(agesa, agesa + file_size, 4096, name); + + if (!image) + return NULL; + + return (AMD_MODULE_HEADER *)image->ModuleInfoOffset; +} + +static MODULE_ENTRY agesa_dispatcher CAR_GLOBAL; + +MODULE_ENTRY agesa_get_dispatcher(void) +{ + const AMD_MODULE_HEADER *module; + static const char id[8] = AGESA_ID; + MODULE_ENTRY val = car_get_var(agesa_dispatcher); + + if (val != NULL) + return val; + + module = agesawrapper_locate_module(id); + if (!module) + return NULL; + + val = module->ModuleDispatcher; + car_set_var(agesa_dispatcher, val); + + return val; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68885e7f855b195c178e746c8f3f0f49166d0def Gerrit-Change-Number: 31318 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: crossgcc: Update binutils to version 2.32
by HAOUAS Elyes (Code Review) 15 Feb '19

15 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31217 Change subject: crossgcc: Update binutils to version 2.32 ...................................................................... crossgcc: Update binutils to version 2.32 Change-Id: I943863587dff6db72d12673bc30ea46f4fd4b66f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/binutils-2.31.1_mips-gold.patch D util/crossgcc/patches/binutils-2.31.1_no-bfd-doc.patch A util/crossgcc/patches/binutils-2.32_mips-gold.patch A util/crossgcc/patches/binutils-2.32_no-bfd-doc.patch D util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum A util/crossgcc/sum/binutils-2.32.tar.xz.cksum 7 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31217/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4c25629..019b011 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -52,7 +52,7 @@ MPC_VERSION=1.1.0 GCC_VERSION=8.2.0 GCC_AUTOCONF_VERSION=2.69 -BINUTILS_VERSION=2.31.1 +BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 IASL_VERSION=20190108 PYTHON_VERSION=3.7.2 diff --git a/util/crossgcc/patches/binutils-2.31.1_mips-gold.patch b/util/crossgcc/patches/binutils-2.31.1_mips-gold.patch deleted file mode 100644 index d9a4021..0000000 --- a/util/crossgcc/patches/binutils-2.31.1_mips-gold.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -urN binutils-2.27.orig/gold/configure.tgt binutils-2.27/gold/configure.tgt ---- binutils-2.27.orig/gold/configure.tgt 2016-08-03 15:36:53.000000000 +0800 -+++ binutils-2.27/gold/configure.tgt 2016-10-29 19:28:56.140587026 +0800 -@@ -157,6 +157,7 @@ - targ_obj=mips - targ_machine=EM_MIPS_RS3_LE - targ_size=32 -+ targ_extra_size=64 - targ_big_endian=false - targ_extra_big_endian=true - ;; diff --git a/util/crossgcc/patches/binutils-2.31.1_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.31.1_no-bfd-doc.patch deleted file mode 100644 index 98707d4..0000000 --- a/util/crossgcc/patches/binutils-2.31.1_no-bfd-doc.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur binutils-2.26.1/bfd/Makefile.in binutils-2.26.1.patched/bfd/Makefile.in ---- binutils-2.26.1/bfd/Makefile.in 2015-11-13 16:27:40.000000000 +0800 -+++ binutils-2.27/bfd/Makefile.in 2016-04-02 11:05:43.398422394 +0800 -@@ -459,7 +459,7 @@ - ACLOCAL_AMFLAGS = -I . -I .. -I ../config - INCDIR = $(srcdir)/../include - CSEARCH = -I. -I$(srcdir) -I$(INCDIR) --SUBDIRS = doc po -+SUBDIRS = po - bfddocdir = doc - libbfd_la_LDFLAGS = $(am__append_1) -release `cat libtool-soversion` \ - @SHARED_LDFLAGS@ $(am__empty) diff --git a/util/crossgcc/patches/binutils-2.32_mips-gold.patch b/util/crossgcc/patches/binutils-2.32_mips-gold.patch new file mode 100644 index 0000000..722367c --- /dev/null +++ b/util/crossgcc/patches/binutils-2.32_mips-gold.patch @@ -0,0 +1,11 @@ +diff -urN binutils-2.32.orig/gold/configure.tgt binutils-2.32/gold/configure.tgt +--- binutils-2.32.orig/gold/configure.tgt ++++ binutils-2.32/gold/configure.tgt +@@ -157,6 +157,7 @@ + targ_obj=mips + targ_machine=EM_MIPS_RS3_LE + targ_size=32 ++ targ_extra_size=64 + targ_big_endian=false + targ_extra_big_endian=true + ;; diff --git a/util/crossgcc/patches/binutils-2.32_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.32_no-bfd-doc.patch new file mode 100644 index 0000000..7e4bb3f --- /dev/null +++ b/util/crossgcc/patches/binutils-2.32_no-bfd-doc.patch @@ -0,0 +1,12 @@ +diff -ur binutils-2.32/bfd/Makefile.in binutils-2.32.patched/bfd/Makefile.in +--- binutils-2.32/bfd/Makefile.in ++++ binutils-2.32.patched/bfd/Makefile.in +@@ -459,7 +459,7 @@ + ACLOCAL_AMFLAGS = -I . -I .. -I ../config + INCDIR = $(srcdir)/../include + CSEARCH = -I. -I$(srcdir) -I$(INCDIR) +-SUBDIRS = doc po ++SUBDIRS = po + bfddocdir = doc + libbfd_la_LDFLAGS = $(am__append_1) -release `cat libtool-soversion` \ + @SHARED_LDFLAGS@ $(am__empty) diff --git a/util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum deleted file mode 100644 index 6a26c8f..0000000 --- a/util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -3b031410897fe224412f3a6a1b052402d2fbcc6a tarballs/binutils-2.31.1.tar.xz diff --git a/util/crossgcc/sum/binutils-2.32.tar.xz.cksum b/util/crossgcc/sum/binutils-2.32.tar.xz.cksum new file mode 100644 index 0000000..bdb84aa --- /dev/null +++ b/util/crossgcc/sum/binutils-2.32.tar.xz.cksum @@ -0,0 +1 @@ +cd45a512af1c8a508976c1beb4f5825b3bb89f4d tarballs/binutils-2.32.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/31217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943863587dff6db72d12673bc30ea46f4fd4b66f Gerrit-Change-Number: 31217 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/atlas: Add bus_speed for audio components
by Gaggery Tsai (Code Review) 15 Feb '19

15 Feb '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31406 Change subject: mb/google/poppy/variants/atlas: Add bus_speed for audio components ...................................................................... mb/google/poppy/variants/atlas: Add bus_speed for audio components This patch sets bus_speed property for audio components to fast speed. Otherwise, the default i2c clock is standard speed in max98373 and da7219 driver. BUG=b:123651555 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & check the i2c clock freqeuncy from LA is at 400KHz. Change-Id: I073ceecd837d343a960621f4b0d797462902a0cc Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/31406/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 275b27d..b5a24f3 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -316,6 +316,7 @@ register "uid" = "0" register "desc" = ""RIGHT SPEAKER AMP"" register "name" = ""MAXR"" + register "bus_speed" = "I2C_SPEED_FAST" device i2c 31 on end end chip drivers/i2c/max98373 @@ -324,6 +325,7 @@ register "uid" = "1" register "desc" = ""LEFT SPEAKER AMP"" register "name" = ""MAXL"" + register "bus_speed" = "I2C_SPEED_FAST" device i2c 32 on end end chip drivers/i2c/da7219 @@ -341,6 +343,7 @@ register "adc_1bit_rpt" = "1" register "micbias_lvl" = "2600" register "mic_amp_in_sel" = ""diff"" + register "bus_speed" = "I2C_SPEED_FAST" device i2c 1a on end end end # I2C #4 - Audio -- To view, visit https://review.coreboot.org/c/coreboot/+/31406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073ceecd837d343a960621f4b0d797462902a0cc Gerrit-Change-Number: 31406 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] mb/google/hatch: Enable DPTF functionality
by Sumeet R Pawnikar (Code Review) 15 Feb '19

15 Feb '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31276 Change subject: [WIP] mb/google/hatch: Enable DPTF functionality ...................................................................... [WIP] mb/google/hatch: Enable DPTF functionality Enable DPTF functionality on hatch platform. Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/baseboard/devicetree.cb A src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl 4 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31276/1 diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 93f7fc0..e6321ba 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -59,4 +59,15 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f2..aaef663 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -57,6 +57,11 @@ register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "44" + register "Device4Enable" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..5e3de83 --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +#endif +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/31276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Gerrit-Change-Number: 31276 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: SMBUS: Update BMC Interface Type field
by HAOUAS Elyes (Code Review) 15 Feb '19

15 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31421 Change subject: SMBUS: Update BMC Interface Type field ...................................................................... SMBUS: Update BMC Interface Type field Change-Id: I68a8515adf5b29a080f8c5c5b7a96b28bca74676 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31421/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 14badbc..da92315 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -481,9 +481,10 @@ enum smbios_bmc_interface_type { SMBIOS_BMC_INTERFACE_UNKNOWN = 0, - SMBIOS_BMC_INTERFACE_KCS, - SMBIOS_BMC_INTERFACE_SMIC, - SMBIOS_BMC_INTERFACE_BLOCK, + SMBIOS_BMC_INTERFACE_KCS = 0x01, + SMBIOS_BMC_INTERFACE_SMIC = 0x02, + SMBIOS_BMC_INTERFACE_BLOCK = 0x03, + SMBIOS_BMC_INTERFACE_SMBUS = 0x04, }; typedef enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/31421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68a8515adf5b29a080f8c5c5b7a96b28bca74676 Gerrit-Change-Number: 31421 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge/southbridge.c: Add new source to sb_clk_output_48Mhz
by Richard Spiegel (Code Review) 15 Feb '19

15 Feb '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31386 Change subject: soc/amd/stoneyridge/southbridge.c: Add new source to sb_clk_output_48Mhz ...................................................................... soc/amd/stoneyridge/southbridge.c: Add new source to sb_clk_output_48Mhz In preparation for board padmelon which will use a clock source different from the one already present in sb_clk_output_48Mhz, change its code to input the desired clock source and set appropriate register based on this input. BUG=b:none. TEST=Build and boot grunt, test again later with padmelon. Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31386/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 3ae6b4a..705fe7a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -186,6 +186,7 @@ #define MISC_CLK_CNTL1 0x40 #define CG1PLL_FBDIV_TEST BIT(26) #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ +#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ /* XHCI_PM Registers: 0xfed81c00 */ #define XHCI_PM_INDIRECT_INDEX 0x48 @@ -477,7 +478,7 @@ void enable_aoac_devices(void); void sb_enable_rom(void); void configure_stoneyridge_i2c(void); -void sb_clk_output_48Mhz(void); +void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c8d66ac..798bcb4 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -389,7 +389,7 @@ pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); } -void sb_clk_output_48Mhz(void) +void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE @@ -401,8 +401,16 @@ */ ctrl = read32(misc_clk_cntl_1_ptr); - /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + switch (osc) { + case 1: + ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + break; + case 2: + ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; + break; + default: + return; /* do nothing if invalid */ + } write32(misc_clk_cntl_1_ptr, ctrl); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914 Gerrit-Change-Number: 31386 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019