coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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1249 discussions

Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Patrick Rudolph (Code Review) 18 Feb '19

18 Feb '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30500 to look at the new patch set (#2). Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... [WIP]arch/x86/postcar: Add x86_64 support Tested on qemu x86_32 and x86_64 using additional MTRRs. Needs test on real hardware. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc M src/arch/x86/exit_car.S M src/arch/x86/gdt_init.S 3 files changed, 109 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30500/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google: Add GPU panel settings for SKL/KBL boards
by Thomas Heijligen (Code Review) 18 Feb '19

18 Feb '19

Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30247 ) Change subject: mb/google: Add GPU panel settings for SKL/KBL boards ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic74e9dac898c17ce64a94b06682997a39daeff69 Gerrit-Change-Number: 30247 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Feb 2019 17:24:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/skl/graphics: Implement panel setup
by Thomas Heijligen (Code Review) 18 Feb '19

18 Feb '19

Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30246 ) Change subject: soc/intel/skl/graphics: Implement panel setup ...................................................................... Patch Set 1: Code-Review+1 checked register offsets -- To view, visit https://review.coreboot.org/c/coreboot/+/30246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae Gerrit-Change-Number: 30246 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Feb 2019 17:23:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [HACK] Various qcs405/mistral changes
by build bot (Jenkins) (Code Review) 18 Feb '19

18 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31466 ) Change subject: [HACK] Various qcs405/mistral changes ...................................................................... Patch Set 1: (8 comments) https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@352 PS1, Line 352: gpio_configure(GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI line over 80 characters https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@353 PS1, Line 353: gpio_configure(GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO line over 80 characters https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@354 PS1, Line 354: gpio_configure(GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT);// CS line over 80 characters https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@355 PS1, Line 355: gpio_configure(GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK line over 80 characters https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@358 PS1, Line 358: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@359 PS1, Line 359: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@360 PS1, Line 360: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters https://review.coreboot.org/#/c/31466/1/src/soc/qualcomm/qcs405/spi.c@361 PS1, Line 361: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5fc77fa33a2f4610e7ba7a5b857a2155744be69 Gerrit-Change-Number: 31466 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Feb 2019 17:05:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by build bot (Jenkins) (Code Review) 18 Feb '19

18 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 13: (39 comments) https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py File util/qualcomm/createxbl.py: https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@25 PS13, Line 25: # 09/04/15 et Added -x and -d to embed xbl_sec ELF trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@68 PS13, Line 68: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@84 PS13, Line 84: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@103 PS13, Line 103: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@113 PS13, Line 113: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@121 PS13, Line 121: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@144 PS13, Line 144: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@164 PS13, Line 164: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@172 PS13, Line 172: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@192 PS13, Line 192: header_format = 'reg' trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@223 PS13, Line 223: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@231 PS13, Line 231: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@232 PS13, Line 232: # Create hash table trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@235 PS13, Line 235: target_hash, trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@237 PS13, Line 237: secure_type = image_header_secflag) trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@245 PS13, Line 245: target_hash_hd, trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@254 PS13, Line 254: # Add the hash segment into the ELF trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@272 PS13, Line 272: def merge_elfs(env, trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@284 PS13, Line 284: mbn_tools.preprocess_elf_file(elf_in_file_name1) trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@289 PS13, Line 289: mbn_tools.preprocess_elf_file(elf_in_file_name2) trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@290 PS13, Line 290: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@294 PS13, Line 294: mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@325 PS13, Line 325: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@364 PS13, Line 364: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@400 PS13, Line 400: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@477 PS13, Line 477: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@512 PS13, Line 512: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@614 PS13, Line 614: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@618 PS13, Line 618: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@621 PS13, Line 621: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@640 PS13, Line 640: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@674 PS13, Line 674: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@675 PS13, Line 675: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@681 PS13, Line 681: inp_data_offset = 0 trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@682 PS13, Line 682: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@689 PS13, Line 689: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@706 PS13, Line 706: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/createxbl.py@708 PS13, Line 708: trailing whitespace https://review.coreboot.org/#/c/29973/13/util/qualcomm/mbn_tools.py File util/qualcomm/mbn_tools.py: https://review.coreboot.org/#/c/29973/13/util/qualcomm/mbn_tools.py@1167 PS13, Line 1167: # Check if a shifting is required to accomodate for the hash segment. 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 18 Feb 2019 17:04:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 18 Feb '19

18 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 13: (95 comments) https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/clock.c@206 PS13, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/clock.c@206 PS13, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/clock.c@207 PS13, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/clock.c@207 PS13, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/clock.c@208 PS13, Line 208: BLSP2_AHB_CLK_ENA); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/clock.c@208 PS13, Line 208: BLSP2_AHB_CLK_ENA); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/qup.h: https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/include/so… PS13, Line 161: unsigned clk_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/include/so… PS13, Line 162: unsigned src_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/include/so… PS13, Line 164: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/include/so… PS13, Line 173: unsigned data_len; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/include/so… PS13, Line 178: unsigned size; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@63 PS13, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@63 PS13, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@63 PS13, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@64 PS13, Line 64: /* BLSP5 registers for SPI interface */ code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@65 PS13, Line 65: { code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@65 PS13, Line 65: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@66 PS13, Line 66: BLSP5_SPI_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@66 PS13, Line 66: BLSP5_SPI_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@67 PS13, Line 67: BLSP5_SPI_IO_CONTROL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@67 PS13, Line 67: BLSP5_SPI_IO_CONTROL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@68 PS13, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@68 PS13, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@69 PS13, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@69 PS13, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@70 PS13, Line 70: BLSP5_QUP_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@70 PS13, Line 70: BLSP5_QUP_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@71 PS13, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@71 PS13, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@72 PS13, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@72 PS13, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@73 PS13, Line 73: BLSP5_QUP_OPERATIONAL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@73 PS13, Line 73: BLSP5_QUP_OPERATIONAL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@74 PS13, Line 74: BLSP5_QUP_IO_MODES_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@74 PS13, Line 74: BLSP5_QUP_IO_MODES_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@75 PS13, Line 75: BLSP5_QUP_STATE_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@75 PS13, Line 75: BLSP5_QUP_STATE_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@76 PS13, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@76 PS13, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@77 PS13, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@77 PS13, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@78 PS13, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@78 PS13, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@79 PS13, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@79 PS13, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@80 PS13, Line 80: BLSP5_QUP_SW_RESET_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@80 PS13, Line 80: BLSP5_QUP_SW_RESET_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@81 PS13, Line 81: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@81 PS13, Line 81: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@82 PS13, Line 82: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@82 PS13, Line 82: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@83 PS13, Line 83: BLSP5_QUP_OPERATIONAL_MASK, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@83 PS13, Line 83: BLSP5_QUP_OPERATIONAL_MASK, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@84 PS13, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@84 PS13, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@85 PS13, Line 85: }, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@85 PS13, Line 85: }, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@273 PS13, Line 273: SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); line over 80 characters https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@310 PS13, Line 310: switch(slave->bus) { switch and case should be at the same indent https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@310 PS13, Line 310: switch(slave->bus) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@311 PS13, Line 311: case 5: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@311 PS13, Line 311: case 5: please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@313 PS13, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@313 PS13, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@313 PS13, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@314 PS13, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@314 PS13, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@314 PS13, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@315 PS13, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@315 PS13, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@315 PS13, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@316 PS13, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@316 PS13, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@316 PS13, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@318 PS13, Line 318: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@318 PS13, Line 318: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@319 PS13, Line 319: default: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@320 PS13, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); line over 80 characters https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@320 PS13, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@320 PS13, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@321 PS13, Line 321: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@321 PS13, Line 321: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@322 PS13, Line 322: } code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@322 PS13, Line 322: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@354 PS13, Line 354: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@428 PS13, Line 428: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@684 PS13, Line 684: "or chipselect\n", bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@684 PS13, Line 684: "or chipselect\n", bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@713 PS13, Line 713: static int xfer_vectors(const struct spi_slave *slave, open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@714 PS13, Line 714: struct spi_op vectors[], size_t count) code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@714 PS13, Line 714: struct spi_op vectors[], size_t count) please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@715 PS13, Line 715: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@716 PS13, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@716 PS13, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/13/src/soc/qualcomm/qcs405/spi.c@717 PS13, Line 717: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 18 Feb 2019 17:04:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) 18 Feb '19

18 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 13: (14 comments) https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 43: struct prog pmic = code indent should use tabs where possible https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 43: struct prog pmic = please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); code indent should use tabs where possible https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 52: if (prog_locate(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 52: if (prog_locate(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 53: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 53: goto fail; please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 55: if (cbfs_prog_stage_load(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 55: if (cbfs_prog_stage_load(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 56: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/13/src/soc/qualcomm/qcs405/qclib_exec… PS13, Line 56: goto fail; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 18 Feb 2019 17:04:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 18 Feb '19

18 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Patch Set 12: (4 comments) https://review.coreboot.org/#/c/29966/12/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/12/src/soc/qualcomm/qcs405/usb.c@137 PS12, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/12/src/soc/qualcomm/qcs405/usb.c@138 PS12, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/12/src/soc/qualcomm/qcs405/usb.c@139 PS12, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/12/src/soc/qualcomm/qcs405/usb.c@140 PS12, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 18 Feb 2019 17:04:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405: Add blsp uart driver
by build bot (Jenkins) (Code Review) 18 Feb '19

18 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 12: (25 comments) https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/cdp.h: https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 36: unsigned smem_get_board_machtype(void); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 89: SPI_CS_0 , space prohibited before that ',' (ctx:WxE) https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 119: unsigned count; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 124: unsigned base; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 126: unsigned is_macsec; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 127: unsigned mac_pwr0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 128: unsigned mac_pwr1; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 129: unsigned mac_conn_to_phy; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 172: unsigned int get_board_index(unsigned machid); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 173: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/iomap.h: https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/include/so… PS12, Line 49: #define writel_i(v,a) write32((void *)a, v) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@50 PS12, Line 50: unsigned blsp_uart; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@54 PS12, Line 54: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@56 PS12, Line 56: int i; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@56 PS12, Line 56: int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@58 PS12, Line 58: for (i = 0; i < count; i++) { code indent should use tabs where possible https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@58 PS12, Line 58: for (i = 0; i < count; i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@59 PS12, Line 59: gpio_configure(gpio->gpio, gpio->func, code indent should use tabs where possible https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@59 PS12, Line 59: gpio_configure(gpio->gpio, gpio->func, please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@60 PS12, Line 60: gpio->pull, gpio->drvstr, gpio->enable); code indent should use tabs where possible https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@60 PS12, Line 60: gpio->pull, gpio->drvstr, gpio->enable); please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@61 PS12, Line 61: gpio++; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@61 PS12, Line 61: gpio++; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@62 PS12, Line 62: } code indent should use tabs where possible https://review.coreboot.org/#/c/29964/12/src/soc/qualcomm/qcs405/uart.c@62 PS12, Line 62: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 18 Feb 2019 17:03:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by build bot (Jenkins) (Code Review) 18 Feb '19

18 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Patch Set 12: (6 comments) https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/flash_cont… File src/soc/qualcomm/qcs405/flash_controller.c: https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/flash_cont… PS12, Line 37: static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) line over 80 characters https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/flash_cont… PS12, Line 68: { that open brace { should be on the previous line https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/flash_cont… PS12, Line 78: static char name[] = "ram_flash"; static char array declaration should probably be static const char https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/flash_cont… PS12, Line 80: printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/flash_cont… PS12, Line 82: printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29959/12/src/soc/qualcomm/qcs405/mmu.c@40 PS12, Line 40: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 18 Feb 2019 17:03:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019