coreboot-gerrit February 2019

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Change in ...coreboot[master]: [WIP] Update libgfxinit for dynamic CPU detection
by Matt DeVillier (Code Review) 19 Feb '19

19 Feb '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27145 ) Change subject: [WIP] Update libgfxinit for dynamic CPU detection ...................................................................... Patch Set 1: Code-Review+1 Tested on google/parrot with both SNB/IVB CPUs/GPUs -- To view, visit https://review.coreboot.org/c/coreboot/+/27145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c349f0ee42c7b201ef0c7461c39c82dede823a9 Gerrit-Change-Number: 27145 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Feb 2019 03:52:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table
by Duncan Laurie (Code Review) 19 Feb '19

19 Feb '19

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: This was reported to cause a suspend failure (with keyboard as a wake source) so I have been holding off until we have some idea what is causing that issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 19 Feb 2019 03:21:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table
by Casper Chang (Code Review) 19 Feb '19

19 Feb '19

Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: May we know what block this CL merged? -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 19 Feb 2019 03:06:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus/variants/fleex: Update TSR1 and TSR2 PSV threshold ...
by John Su (Code Review) 19 Feb '19

19 Feb '19

John Su has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29692 ) Change subject: mb/google/octopus/variants/fleex: Update TSR1 and TSR2 PSV threshold settings ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib050194d273b20f8efd73f89d0a6a1fa52b89bc8 Gerrit-Change-Number: 29692 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1
by John Su (Code Review) 18 Feb '19

18 Feb '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31412 Change subject: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1 ...................................................................... mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1 Follow b:123461432#5 to updte GPIO H3(CNVI_EN#) for DVT1. Update setting GPIO H3 to output and low level. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31412/1 diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index e735fee..ff311b1 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -188,7 +188,7 @@ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ +/* I2S2_RXD */ PAD_CFG_GPO(GPP_H3, 0, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ /* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Gerrit-Change-Number: 31412 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Update dptf.asl for EVT1
by John Su (Code Review) 18 Feb '19

18 Feb '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31170 Change subject: mb/google/sarien/variants/sarien: Update dptf.asl for EVT1 ...................................................................... mb/google/sarien/variants/sarien: Update dptf.asl for EVT1 Follow thermal table (b:123383634 comment#1) for EVT1 tunning. BUG=b:123383634 BRANCH=sarien TEST=Built and tested on sarien system Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31170/1 diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index d6a1274..66839a0 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -13,42 +13,42 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_PASSIVE 99 #define DPTF_CPU_CRITICAL 100 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_PASSIVE 71 +#define DPTF_TSR0_CRITICAL 100 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 55 -#define DPTF_TSR1_CRITICAL 80 +#define DPTF_TSR1_PASSIVE 56 +#define DPTF_TSR1_CRITICAL 100 /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 90 +#define DPTF_TSR2_CRITICAL 100 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 5000, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 200, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 2000, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 10, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -58,16 +58,16 @@ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ 25000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ + 10000, /* TimeWindowMinimum */ + 10000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ + 3000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ + 28000, /* TimeWindowMaximum */ 100 /* StepSize */ } }) -- To view, visit https://review.coreboot.org/c/coreboot/+/31170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca Gerrit-Change-Number: 31170 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Fix for missing mem_rank info in SMBIOS
by Francois Toguo Fotso (Code Review) 18 Feb '19

18 Feb '19

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31235 Change subject: Fix for missing mem_rank info in SMBIOS ...................................................................... Fix for missing mem_rank info in SMBIOS Found-by: Google BUG=None TEST=Boot to OS: Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842 Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M 3rdparty/blobs M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 8 files changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31235/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 16058e5..678b4c4 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 16058e552279b4884b1f671e7a78752d28abd1cc +Subproject commit 678b4c4a81069bb6e10e2e59f5374b83d727cd2b diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index 755d708..0112789 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -85,6 +85,7 @@ src_dimm->SizeInMb, memory_info_hob->MemoryType, memory_info_hob->MemoryFrequencyInMHz, + src_dimm->RankInDimm, channel_info->ChannelId, src_dimm->DimmId, dram_part_num, diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index db69f51..9bfdf0b 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -91,6 +91,7 @@ src_dimm->DimmCapacity, memory_info_hob->MemoryType, memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, channel_info->ChannelId, src_dimm->DimmId, dram_part_num, diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9224ba6..24f1f12 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -93,6 +93,7 @@ src_dimm->DimmCapacity, memory_info_hob->MemoryType, memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, channel_info->ChannelId, src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index bcddb78..d714a34 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -20,13 +20,14 @@ /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, - u32 frequency, u8 channel_id, u8 dimm_id, + u32 frequency, u8 rankInDimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, u16 data_width) { dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; dimm->ddr_frequency = frequency; + dimm->rank_per_dimm = rankInDimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; strncpy((char *)dimm->module_part_number, diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 4750d3c..022271d 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -21,7 +21,7 @@ /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, - u32 frequency, u8 channel_id, u8 dimm_id, + u32 frequency, u8 rank_per_dim, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, u16 data_width); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 432cae5..3951124 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -95,6 +95,7 @@ src_dimm->DimmCapacity, memory_info_hob->MemoryType, memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, channel_info->ChannelId, src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..7a3509f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -121,6 +121,7 @@ src_dimm->DimmCapacity, ddr_type, memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDim, channel_info->ChannelId, src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, -- To view, visit https://review.coreboot.org/c/coreboot/+/31235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842 Gerrit-Change-Number: 31235 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Use real common code for VMX init
by Patrick Georgi (Code Review) 18 Feb '19

18 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29682 ) Change subject: soc/intel/skylake: Use real common code for VMX init ...................................................................... soc/intel/skylake: Use real common code for VMX init Use the common VMX implementation, and set IA32_FEATURE_CONTROL lock bit per Kconfig *after* SGX is configured (as SGX also sets bits on the IA32_FEATURE_CONTROL register). As it is now correctly based on a Kconfig, the `VmxEnable` devicetree setting vanishes. Test: build/boot google/[chell,fizz], observe Virtualization enabled under Windows 10 when VMX enabled and lock bit set. Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29682 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 26 files changed, 16 insertions(+), 52 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 44449a5..66c1c53 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -52,7 +52,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index c7c35c0..07a453d 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -88,7 +88,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround - register "VmxEnable" = "1" # Intersil VR c-state issue workaround # send VR mailbox command for IA/GT/SA rails diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index b9e87a8..d365e8f 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -44,7 +44,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 8caf8fd..cffb6df 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -54,7 +54,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" # TCC offset register "tcc_offset" = "10" diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index f512f9b..e0c7fc7 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -54,7 +54,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index 3343aa0..1b87cca 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -54,7 +54,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index 2472dde..f4e09a6 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -54,7 +54,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index d552010..56087ad 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -42,7 +42,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 7a89194..0effbd7 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -44,7 +44,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 275b27d..adf51b7 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -60,7 +60,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "speed_shift_enable" = "1" register "tdp_pl2_override" = "15" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index ad1e628..251cab8 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -57,7 +57,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d4e5d2f..5d9c096 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -56,7 +56,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" # Intersil VR c-state issue workaround # send VR mailbox command for IA/GT/SA rails diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 37edd8a..75a01c2 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -57,7 +57,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 76b9773..4d9403c 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -62,7 +62,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index cf32593..c8e4008 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -60,7 +60,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ddf74a1..4713a81 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -57,7 +57,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index be9d1df..51399dc 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -126,9 +126,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - # Enable/Disable VMX feature - register "VmxEnable" = "0" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ffa259b7..4b720bf 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -186,9 +186,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - # Enable/Disable VMX feature - register "VmxEnable" = "0" - # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index e541bfe..7036b28 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -247,8 +247,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - # Enable/Disable VMX feature - register "VmxEnable" = "0" # Use default SD card detect GPIO configuration #register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index a4fd502d..399c643 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -8,7 +8,6 @@ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "1" - register "VmxEnable" = "1" # Set the Thermal Control Circuit (TCC) activaction value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 7ff3dad..f9f7ef7 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -8,7 +8,6 @@ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "1" - register "VmxEnable" = "1" # Set the Thermal Control Circuit (TCC) activaction value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 506a041..77d259b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -26,6 +26,7 @@ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select C_ENVIRONMENT_BOOTBLOCK select FSP_M_XIP if MAINBOARD_USES_FSP2_0 @@ -65,7 +66,6 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_UART - select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 39e5056..f131a1a 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -465,9 +465,6 @@ */ u8 SendVrMbxCmd; - /* Enable/Disable VMX feature */ - u8 VmxEnable; - /* * PRMRR size setting with three options * 0x02000000 - 32MiB diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 3ade8d7..f4e17c6 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -322,7 +322,7 @@ params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; - params->CpuConfig.Bits.VmxEnable = config->VmxEnable; + params->CpuConfig.Bits.VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 413fbbb..910dcb8 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -27,6 +27,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -39,7 +40,6 @@ #include <intelblocks/mp_init.h> #include <intelblocks/sgx.h> #include <intelblocks/smm.h> -#include <intelblocks/vmx.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -467,6 +467,16 @@ smm_relocate(); } +static void vmx_configure(void *unused) +{ + set_feature_ctrl_vmx(); +} + +static void fc_lock_configure(void *unused) +{ + set_feature_ctrl_lock(); +} + static void post_mp_init(void) { /* Set Max Ratio */ @@ -486,6 +496,8 @@ mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC); + + mp_run_on_all_cpus(fc_lock_configure, NULL, 2 * USECS_PER_MSEC); } static const struct mp_ops mp_ops = { @@ -566,22 +578,3 @@ sgx_param->enable = conf->sgx_enable; return 0; } -int soc_fill_vmx_param(struct vmx_param *vmx_param) -{ - struct device *dev = SA_DEV_ROOT; - config_t *conf; - - if (!dev) { - printk(BIOS_ERR, "Failed to get root dev for checking VMX param\n"); - return -1; - } - - conf = dev->chip_info; - if (!conf) { - printk(BIOS_ERR, "Failed to get chip_info for VMX param\n"); - return -1; - } - - vmx_param->enable = conf->VmxEnable; - return 0; -} diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..6fe79f6 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -225,7 +225,7 @@ m_cfg->RMT = config->Rmt; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = config->VmxEnable; + m_cfg->VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) -- To view, visit https://review.coreboot.org/c/coreboot/+/29682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Gerrit-Change-Number: 29682 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM
by Duncan Laurie (Code Review) 18 Feb '19

18 Feb '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31436 Change subject: mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM ...................................................................... mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM The Intel SOC can only shadow the top 16MB of SPI into memory so in order to make it easier to access the NVRAM region with memory mapped interface move it above the much larger RW_LEGACY region. I tested to confirm that this region can now be read via MMIO interface and does not need to use the hwseq SPI controller. Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31436/1 diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 2408a30..db0af0f 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -8,8 +8,8 @@ } SI_BIOS@0x400000 0x1c00000 { RW_DIAG@0x0 0x12d0000 { - DIAG_NVRAM@0x0 0x10000 - RW_LEGACY(CBFS)@0x10000 0x12c0000 + RW_LEGACY(CBFS)@0x0 0x12c0000 + DIAG_NVRAM@0x12c0000 0x10000 } RW_SECTION_A@0x12d0000 0x280000 { VBLOCK_A@0x0 0x10000 -- To view, visit https://review.coreboot.org/c/coreboot/+/31436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da Gerrit-Change-Number: 31436 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/google/sarien: Create VR config settings
by Roy Mingi Park (Code Review) 18 Feb '19

18 Feb '19

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31404 Change subject: mb/google/sarien: Create VR config settings ...................................................................... mb/google/sarien: Create VR config settings Create VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31404/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a47a53d..244ba7a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -42,6 +42,82 @@ register "SlowSlewRateForSa" = "0" register "SlowSlewRateForFivr" = "0" + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d3d26f9..85d0cb0 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -46,6 +46,82 @@ register "tdp_pl2_override" = "51" register "Device4Enable" = "1" + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62 Gerrit-Change-Number: 31404 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019