coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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1249 discussions

Change in ...coreboot[master]: drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 module
by Subrata Banik (Code Review) 20 Feb '19

20 Feb '19

Hello Wonkyu Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31475 to review the following change. Change subject: drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 module ...................................................................... drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 module Add HrP 9560 module device ID (0x02F0) into device/pci_ids.h file. TEST=HrP module is getting detected during PCI enumeration Change-Id: Id0a8a7a8cf7c665bd49f27b1c50d41d26a3274ce Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/drivers/intel/wifi/wifi.c M src/include/device/pci_ids.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31475/1 diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index cd512ea..416b04b 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -350,6 +350,7 @@ /* Harrison Peak */ PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI, PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, + PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, 0 }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 751cca0..9c5ffb3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3136,6 +3136,7 @@ #define PCI_DEVICE_ID_TP_9260_SERIES_WIFI 0x2526 #define PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI 0x34f0 #define PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI 0xa0f0 +#define PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI 0x02f0 #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 -- To view, visit https://review.coreboot.org/c/coreboot/+/31475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0a8a7a8cf7c665bd49f27b1c50d41d26a3274ce Gerrit-Change-Number: 31475 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Kyösti Mälkki (Code Review) 20 Feb '19

20 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27277 ) Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/agesawr… PS5, Line 356: amd_late_run_ap_task > Just for compatibility with the remaining functions within agesawrapper, even though it's not called […] That prefix agesawrapper_ was stupid in the first place and followups shall remove the rest. So they shall be symmetrical at the end of the day. -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Feb 2019 04:00:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sifive/hifive-unleashed: Drop unneeded console_tx_flush()
by Kyösti Mälkki (Code Review) 20 Feb '19

20 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31369 Change subject: sifive/hifive-unleashed: Drop unneeded console_tx_flush() ...................................................................... sifive/hifive-unleashed: Drop unneeded console_tx_flush() Every printk() call already does console_tx_flush() so there should not be anything in transmit buffer when we return from console_init(). Change-Id: Iff2927c02d2c8031907620a056782bb014f20162 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/sifive/hifive-unleashed/romstage.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/31369/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 8277141..0611a6d 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -27,12 +27,6 @@ /* TODO: Follow Section 6.3 (FSBL) of the FU540 manual */ - /* - * Flush console before changing clock/UART divisor to prevent garbage - * being printed. - */ - console_tx_flush(); - clock_init(); // re-initialize UART -- To view, visit https://review.coreboot.org/c/coreboot/+/31369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff2927c02d2c8031907620a056782bb014f20162 Gerrit-Change-Number: 31369 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet spec
by Chris Zhou (Code Review) 20 Feb '19

20 Feb '19

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31476 Change subject: mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet spec ...................................................................... mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet spec After adjustment on Sarien EVT Touch Screen CLK (Elan): 389.7KHZ Touch Screen CLK (Melfas): 377.7KHZ Touch Pad CLK: 385KHZ BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31476/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index bcd3c26..df22aff 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -157,12 +157,12 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 190, - .fall_time_ns = 120, + .rise_time_ns = 100, + .fall_time_ns = 80, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 52, + .rise_time_ns = 80, .fall_time_ns = 110, }, .i2c[4] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d Gerrit-Change-Number: 31476 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Richard Spiegel (Code Review) 20 Feb '19

20 Feb '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27277 ) Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/agesawr… PS5, Line 356: amd_late_run_ap_task Just for compatibility with the remaining functions within agesawrapper, even though it's not called by AmdAgesaCallout), I believe this function should be called agesawrapper_amd_late_run_ap_task. https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/def_cal… File src/soc/amd/common/block/pi/def_callouts.c: https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/def_cal… PS5, Line 208: amd_late_run_ap_task agesawrapper_amd_late_run_ap_task? -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Feb 2019 00:23:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common: Add whiskeylake celeron v-0 support
by Lijian Zhao (Code Review) 19 Feb '19

19 Feb '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31433 Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ...................................................................... soc/intel/common: Add whiskeylake celeron v-0 support New whiskeylake v-0 stepping have change the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so delacre that in common code. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31433/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 751cca0..0030961 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2969,6 +2969,7 @@ #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184 #define PCI_DEVICE_ID_INTEL_GLK_IGD_EU12 0x3185 +#define PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1 0x3EA1 #define PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1 0x3EA0 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1 0x5A51 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2 0x5A59 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 19a78e7..8eebd12 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, PCI_DEVICE_ID_INTEL_GLK_IGD, PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, + PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, -- To view, visit https://review.coreboot.org/c/coreboot/+/31433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 Gerrit-Change-Number: 31433 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 19 Feb '19

19 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 33: (7 comments) https://review.coreboot.org/#/c/29563/33/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/33/src/include/memlayout.h@167 PS33, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/33/src/include/memlayout.h@167 PS33, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/33/src/security/tpm/tspi.h File src/security/tpm/tspi.h: https://review.coreboot.org/#/c/29563/33/src/security/tpm/tspi.h@50 PS33, Line 50: uint32_t tpm_extend_pcr(int pcr, const char *digest_type, uint8_t *digest, size_t digest_len, line over 80 characters https://review.coreboot.org/#/c/29563/33/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/33/src/security/tpm/tspi/log.c@36 PS33, Line 36: if (!cbmem_possibly_online() && IS_ENABLED(CONFIG_VBOOT_TCPA_LOG_RECOVERY)) { line over 80 characters https://review.coreboot.org/#/c/29563/33/src/security/tpm/tspi/log.c@45 PS33, Line 45: size_t tcpa_log_len = sizeof(struct tcpa_table) + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); line over 80 characters https://review.coreboot.org/#/c/29563/33/src/security/tpm/tspi/log.c@89 PS33, Line 89: void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, const char *digest_type, line over 80 characters https://review.coreboot.org/#/c/29563/33/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29563/33/src/security/vboot/secdata_tpm.c@86 PS33, Line 86: return tpm_extend_pcr(pcr, "SHA256", buffer, size, TPM_PCR_GBB_HWID_NAME); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 33 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 19 Feb 2019 19:02:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Test
by Felix Singer (Code Review) 19 Feb '19

19 Feb '19

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30870 ) Change subject: Test ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3fd19b493443df797cea21afbeeeae285b6eac9 Gerrit-Change-Number: 30870 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/emulation/qemu-q35: Add x86_64 support
by Patrick Rudolph (Code Review) 19 Feb '19

19 Feb '19

Patrick Rudolph has uploaded a new patch set (#15) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35: Add x86_64 support ...................................................................... mb/emulation/qemu-q35: Add x86_64 support * Enable optional x86_64 romstage, postcar and ramstage * Add Kconfig for x86_64 compilation * Add documentation for x86 qemu mainboards * Increase CAR stack as x86_64 uses more than 0x4000 bytes * Always setup MTRRs even though qemu doesn't care about them Working: * Boots to Linux * Boots to SeaBios * Drops to protected mode at end of ramstage * Enumerates PCI devices * Relocateable ramstage Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 --- M Documentation/arch/x86/index.md A Documentation/mainboard/emulation/qemu-i440fx.md A Documentation/mainboard/emulation/qemu-q35.md M Documentation/mainboard/index.md M src/arch/x86/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/romstage.c 11 files changed, 211 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29667/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 15 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/emulation/qemu-q35: x86_64 support
by Patrick Rudolph (Code Review) 19 Feb '19

19 Feb '19

Patrick Rudolph has uploaded a new patch set (#14) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35: x86_64 support ...................................................................... mb/emulation/qemu-q35: x86_64 support * Enable optional x86_64 romstage, postcar and ramstage * Add documentation for x86 qemu mainboards * Increase CAR stack as x86_64 uses more than 0x4000 bytes * Always setup MTRRs even though qemu doesn't care about them Working: * Boots to Linux * Drops to protected mode at end of ramstage * Enumerates PCI devices * Relocateable ramstage * postcar stage Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 --- M Documentation/arch/x86/index.md A Documentation/mainboard/emulation/qemu-i440fx.md A Documentation/mainboard/emulation/qemu-q35.md M Documentation/mainboard/index.md M src/arch/x86/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/romstage.c 11 files changed, 211 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29667/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2019