coreboot-gerrit February 2019

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 20 Feb '19

20 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 35: (12 comments) https://review.coreboot.org/#/c/29563/35/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/35/src/include/memlayout.h@167 PS35, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/35/src/include/memlayout.h@167 PS35, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi.h File src/security/tpm/tspi.h: https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi.h@50 PS35, Line 50: uint32_t tpm_extend_pcr(int pcr, const char *digest_type, uint8_t *digest, size_t digest_len, line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@37 PS35, Line 37: size_t tcpa_log_len = sizeof(struct tcpa_table) + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@43 PS35, Line 43: if (strncmp(TCPA_LOG_HEADER, (const char *)tclt->header, sizeof(tclt->header))) { line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@44 PS35, Line 44: tclt->max_entries = MAX_PREMEM_TCPA_LOG_ENTRIES; line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@46 PS35, Line 46: strncpy((char *)tclt->header, TCPA_LOG_HEADER, sizeof(tclt->header)); line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@54 PS35, Line 54: strncpy((char *)tclt->header, TCPA_LOG_HEADER, sizeof(tclt->header)); line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@59 PS35, Line 59: if (strncmp(TCPA_LOG_HEADER, (const char *)tclt->header, sizeof(tclt->header))) { line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@62 PS35, Line 62: strncpy((char *)tclt->header, TCPA_LOG_HEADER, sizeof(tclt->header)); line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/tpm/tspi/log.c@97 PS35, Line 97: void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, const char *digest_type, line over 80 characters https://review.coreboot.org/#/c/29563/35/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29563/35/src/security/vboot/secdata_tpm.c@86 PS35, Line 86: return tpm_extend_pcr(pcr, "SHA256", buffer, size, TPM_PCR_GBB_HWID_NAME); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 35 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 20 Feb 2019 19:44:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 20 Feb '19

20 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#35). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 22 files changed, 187 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 35 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: SoC specific microcode update check
by Ronak Kanabar (Code Review) 20 Feb '19

20 Feb '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31492 ) Change subject: soc/intel/cannonlake: SoC specific microcode update check ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/#/c/31492/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31492/2//COMMIT_MSG@13 PS2, Line 13: bootclock > bootblock done https://review.coreboot.org/#/c/31492/2//COMMIT_MSG@13 PS2, Line 13: againin > again in done https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c File src/soc/intel/cannonlake/cpu.c: https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@496 PS2, Line 496: CFL and WHL CPU die are based on KBL CPU so we need to have this check, where CNL > This line seems to be greater than 80 columns? done https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@504 PS2, Line 504: * > not required done https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@515 PS2, Line 515: else > else not required. done -- To view, visit https://review.coreboot.org/c/coreboot/+/31492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 Gerrit-Change-Number: 31492 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Wed, 20 Feb 2019 19:08:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: SoC specific microcode update check
by Ronak Kanabar (Code Review) 20 Feb '19

20 Feb '19

Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31492 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: SoC specific microcode update check ...................................................................... soc/intel/cannonlake: SoC specific microcode update check For CFL and WHL, Microcode is being loaded from FIT. Both supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootblock and ramstage. Avoid the microcode reload by checking for PRMRR support. CFL and WHL CPU die are based on KBL CPU so we need to have this check, where CNL CPU die is not based on KBL CPU so skip this check for CNL. BUG=b:124126405 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/31492/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/31492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 Gerrit-Change-Number: 31492 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: SoC specific microcode update check
by Furquan Shaikh (Code Review) 20 Feb '19

20 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31492 ) Change subject: soc/intel/cannonlake: SoC specific microcode update check ...................................................................... Patch Set 2: (5 comments) https://review.coreboot.org/#/c/31492/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31492/2//COMMIT_MSG@13 PS2, Line 13: bootclock bootblock https://review.coreboot.org/#/c/31492/2//COMMIT_MSG@13 PS2, Line 13: againin again in https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c File src/soc/intel/cannonlake/cpu.c: https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@496 PS2, Line 496: CFL and WHL CPU die are based on KBL CPU so we need to have this check, where CNL This line seems to be greater than 80 columns? https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@504 PS2, Line 504: * not required https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@515 PS2, Line 515: else else not required. -- To view, visit https://review.coreboot.org/c/coreboot/+/31492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 Gerrit-Change-Number: 31492 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Wed, 20 Feb 2019 17:07:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: take the sting out of the requirements
by Patrick Georgi (Code Review) 20 Feb '19

20 Feb '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31480 Change subject: Documentation: take the sting out of the requirements ...................................................................... Documentation: take the sting out of the requirements The requirements read a bit as if we only encourage coreboot experts to try to take on these projects. These requirements should be understood as "this is what you'll need to learn", hopefully guiding interested people in picking a project that suits their interests. Change-Id: I43b6e2e0df5f00e1ded8d14cee8c771e3f595ce7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31480/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index d80a327..e45627d 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -13,6 +13,13 @@ on them - since we started building this list for Google Summer of Code, we'll adopt its term for those people and call them mentors. +The requirements for each project aim for productive work on the project, +but it's always possible to learn them "on the job". If you have any +doubt if you can bring yourself up to speed in a required time frame +(e.g. for GSoC), feel free to ask in the community or the mentors listed +with the projects. We can then try together to figure out if you're a +good match for a project, even when requirements might not all be met. + ## Provide toolchain binaries Our crossgcc subproject provides a uniform compiler environment for working on coreboot and related projects. Sadly, building it takes hours, @@ -23,7 +30,6 @@ (shell, make, ...). ### Requirements - * coreboot knowledge: Should know how to build coreboot images and where the compiler comes into play in our build system. * other knowledge: Should know how packages or installers for their -- To view, visit https://review.coreboot.org/c/coreboot/+/31480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43b6e2e0df5f00e1ded8d14cee8c771e3f595ce7 Gerrit-Change-Number: 31480 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Add Clang support to project ideas
by Patrick Georgi (Code Review) 20 Feb '19

20 Feb '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31479 Change subject: Documentation: Add Clang support to project ideas ...................................................................... Documentation: Add Clang support to project ideas Change-Id: Iaccb5ca5606b83a4b37930b4399ddcf9eddd494b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31479/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2e43871..d80a327 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -110,3 +110,32 @@ ### Mentors * Simon Glass <sjg(a)chromium.org> for U-Boot payload projects + +## Fully support building coreboot with the Clang compiler +Most coreboot code is written in C, and it would be useful to support +a second compiler suite in addition to gcc. Clang is another popular +compiler suite and the build system generally supports building coreboot +with it, but firmware is a rather special situation and we need to +adjust coreboot and Clang some more to get usable binaries out of that +combination. + +The goal would be to get the emulation targets to boot reliably first, +but also to support real hardware. If you don't have hardware around, +you likely will find willing testers for devices they own and work from +their bug reports. + +### Requirements +* coreboot knowledge: Have a general concept of the build system +* Clang knowledge: It may be necessary to apply minor modifications to Clang + itself, but at least there will be Clang-specific compiler optoins etc to + adapt, so some idea how compilers work and how to modify their behavior is + helpful. +* hardware requirements: If you have your own hardware that is already + supported by coreboot that can be a good test target, but you will debug + other people's hardware, too. +* debugging experience: It helps if you know how to get the most out of a bug + report, generate theories, build patches to test them and figure out what's + going on from the resulting logs. + +### Mentors +* Patrick Georgi <patrick(a)georgi.software> -- To view, visit https://review.coreboot.org/c/coreboot/+/31479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaccb5ca5606b83a4b37930b4399ddcf9eddd494b Gerrit-Change-Number: 31479 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Werner Zeh (Code Review) 20 Feb '19

20 Feb '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 62: Code-Review+1 Runs fine on mc_bdx1 and mc_apl5. Thouh the stages are messured twice. The whitelist-feature works, too. -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 62 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Feb 2019 14:56:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [TEST]sb/intel/common: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review) 20 Feb '19

20 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30506 Change subject: [TEST]sb/intel/common: Remove CAR_GLOBAL use ...................................................................... [TEST]sb/intel/common: Remove CAR_GLOBAL use We have NO_CAR_GLOBAL_MIGRATION now. (yes?) Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/spi.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30506/1 diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 7c8cfe8..140839f 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -40,7 +40,7 @@ /* Don't assume GPIO_BASE is still the same */ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; #else - static u16 gpiobase CAR_GLOBAL; + static u16 gpiobase; if (gpiobase) return gpiobase; diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2de57d6..b022629 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -42,7 +42,7 @@ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; #else - static u16 pmbase CAR_GLOBAL; + static u16 pmbase; if (pmbase) return pmbase; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3ca0d6c..6ef6769 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -69,7 +69,7 @@ typedef struct spi_slave ich_spi_slave; -static int g_ichspi_lock CAR_GLOBAL = 0; +static int g_ichspi_lock = 0; typedef struct ich7_spi_regs { uint16_t spis; @@ -138,7 +138,7 @@ uint8_t fpr_max; } ich_spi_controller; -static ich_spi_controller g_cntlr CAR_GLOBAL; +static ich_spi_controller g_cntlr; enum { SPIS_SCIP = 0x0001, -- To view, visit https://review.coreboot.org/c/coreboot/+/30506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Gerrit-Change-Number: 30506 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 20 Feb '19

20 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 34: (7 comments) https://review.coreboot.org/#/c/29563/34/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/34/src/include/memlayout.h@167 PS34, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/34/src/include/memlayout.h@167 PS34, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/34/src/security/tpm/tspi.h File src/security/tpm/tspi.h: https://review.coreboot.org/#/c/29563/34/src/security/tpm/tspi.h@50 PS34, Line 50: uint32_t tpm_extend_pcr(int pcr, const char *digest_type, uint8_t *digest, size_t digest_len, line over 80 characters https://review.coreboot.org/#/c/29563/34/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/34/src/security/tpm/tspi/log.c@36 PS34, Line 36: if (!cbmem_possibly_online() && IS_ENABLED(CONFIG_VBOOT_TCPA_LOG_RECOVERY)) { line over 80 characters https://review.coreboot.org/#/c/29563/34/src/security/tpm/tspi/log.c@45 PS34, Line 45: size_t tcpa_log_len = sizeof(struct tcpa_table) + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); line over 80 characters https://review.coreboot.org/#/c/29563/34/src/security/tpm/tspi/log.c@89 PS34, Line 89: void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, const char *digest_type, line over 80 characters https://review.coreboot.org/#/c/29563/34/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29563/34/src/security/vboot/secdata_tpm.c@86 PS34, Line 86: return tpm_extend_pcr(pcr, "SHA256", buffer, size, TPM_PCR_GBB_HWID_NAME); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 34 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 20 Feb 2019 13:01:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019