coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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1249 discussions

Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard
by Felix Singer (Code Review) 14 Feb '19

14 Feb '19

Hello Paul Menzel, Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28640 to look at the new patch set (#81). Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... mb/clevo/n130wu: Add mainboard Devices: - N130WU / N131WU Working: - Compiling - Seabios, iPXE - NVMe, SATA3, booting from SSD into Arch Linux - USB2, USB3 - Graphics, mDP, HDMI - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux Works, but needs testing: - Thunderbolt WIP: - Documentation Not working: - EC ACPI Untested: - Virtualization Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A Documentation/mainboard/clevo/index.md A Documentation/mainboard/clevo/n130wu/index.md A Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg M Documentation/mainboard/index.md A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/kbl-u/Kconfig A src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/Makefile.inc A src/mainboard/clevo/kbl-u/acpi/ec.asl A src/mainboard/clevo/kbl-u/acpi/superio.asl A src/mainboard/clevo/kbl-u/acpi_tables.c A src/mainboard/clevo/kbl-u/board_info.txt A src/mainboard/clevo/kbl-u/devicetree.cb A src/mainboard/clevo/kbl-u/dsdt.asl A src/mainboard/clevo/kbl-u/gpio.h A src/mainboard/clevo/kbl-u/hda_verb.c A src/mainboard/clevo/kbl-u/pei_data.c A src/mainboard/clevo/kbl-u/pei_data.h A src/mainboard/clevo/kbl-u/ramstage.c A src/mainboard/clevo/kbl-u/romstage.c A src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt A src/mainboard/clevo/kbl-u/variants/n13xwu/overridetree.cb 23 files changed, 933 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28640/81 -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 81 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME
by Vanessa Eusebio (Code Review) 14 Feb '19

14 Feb '19

Vanessa Eusebio has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25444 ) Change subject: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME ...................................................................... Patch Set 10: > Patch Set 10: > > > Patch Set 10: > > > > Hi Julien, > > Was this tested on the latest spsInfo/spsManuf? Thanks.. > Hi Vanessa, > > I don't remember testing without the patch since I added it. > > Also I did quit Scaleway last December, so I no longer have access to NDA documentation/firmware from Intel and can't do that particular test. > > So I guess, either you can test it or we should drop this patch... > > Best Regards, > > Julien Hi Julien, Thanks for letting me know. Will test this first before approval. -- To view, visit https://review.coreboot.org/c/coreboot/+/25444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c59ff80ef19b54c2de1a6a8205afe6482adfdff Gerrit-Change-Number: 25444 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 14 Feb 2019 17:56:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 14 Feb '19

14 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 32: (7 comments) https://review.coreboot.org/#/c/29563/32/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/32/src/include/memlayout.h@167 PS32, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/32/src/include/memlayout.h@167 PS32, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/32/src/security/tpm/tspi.h File src/security/tpm/tspi.h: https://review.coreboot.org/#/c/29563/32/src/security/tpm/tspi.h@50 PS32, Line 50: uint32_t tpm_extend_pcr(int pcr, const char *digest_type, uint8_t *digest, size_t digest_len, line over 80 characters https://review.coreboot.org/#/c/29563/32/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/32/src/security/tpm/tspi/log.c@36 PS32, Line 36: if (!cbmem_possibly_online() && IS_ENABLED(CONFIG_VBOOT_TCPA_LOG_RECOVERY)) { line over 80 characters https://review.coreboot.org/#/c/29563/32/src/security/tpm/tspi/log.c@45 PS32, Line 45: size_t tcpa_log_len = sizeof(struct tcpa_table) + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); line over 80 characters https://review.coreboot.org/#/c/29563/32/src/security/tpm/tspi/log.c@89 PS32, Line 89: void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, const char *digest_type, line over 80 characters https://review.coreboot.org/#/c/29563/32/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29563/32/src/security/vboot/secdata_tpm.c@86 PS32, Line 86: return tpm_extend_pcr(pcr, "SHA256", buffer, size, TPM_PCR_GBB_HWID_NAME); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 32 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 16:52:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by build bot (Jenkins) (Code Review) 14 Feb '19

14 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 54: (14 comments) https://review.coreboot.org/#/c/29547/54/src/lib/cbfs.c File src/lib/cbfs.c: https://review.coreboot.org/#/c/29547/54/src/lib/cbfs.c@64 PS54, Line 64: if (!ret && !ENV_BOOTBLOCK && !ENV_DECOMPRESSOR && IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT)) { line over 80 characters https://review.coreboot.org/#/c/29547/54/src/lib/cbfs.c@110 PS54, Line 110: size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) line over 80 characters https://review.coreboot.org/#/c/29547/54/src/lib/cbfs.c@123 PS54, Line 123: if ((ENV_BOOTBLOCK || ENV_VERSTAGE) && !IS_ENABLED(CONFIG_COMPRESS_PRERAM_STAGES)) line over 80 characters https://review.coreboot.org/#/c/29547/54/src/lib/cbfs.c@265 PS54, Line 265: if (ENV_VERSTAGE && !IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES) && IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) { line over 80 characters https://review.coreboot.org/#/c/29547/54/src/lib/prog_loaders.c File src/lib/prog_loaders.c: https://review.coreboot.org/#/c/29547/54/src/lib/prog_loaders.c@51 PS54, Line 51: if (!ENV_BOOTBLOCK && !ENV_DECOMPRESSOR && IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT)) line over 80 characters https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_crtm.h File src/security/vboot/vboot_crtm.h: https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_crtm.h@73 PS54, Line 73: uint32_t vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type); line over 80 characters https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_crtm.c@153 PS54, Line 153: uint32_t vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type) line over 80 characters https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c@98 PS54, Line 98: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c@1… PS54, Line 104: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c@2… PS54, Line 281: return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); line over 80 characters https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c@3… PS54, Line 308: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) line over 80 characters https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c@3… PS54, Line 319: if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { line over 80 characters https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c@3… PS54, Line 324: if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) line over 80 characters https://review.coreboot.org/#/c/29547/54/src/security/vboot/vboot_logic.c@3… PS54, Line 333: if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 54 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 15:30:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Philipp Deppenwiese (Code Review) 14 Feb '19

14 Feb '19

Hello Patrick Rudolph, Aaron Durbin, Piotr Król, Julius Werner, Krystian Hebel, Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Werner Zeh, Huang Jin, York Yang, David Hendricks, Martin Roth, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29547 to look at the new patch set (#54). Change subject: security/vboot: Add measured boot mode ...................................................................... security/vboot: Add measured boot mode * Introduce a measured boot mode into vboot. * Add hook for stage measurements in prog_ops. * Implement and hook-up CRTM in vboot and check for suspend. * Documentation will be done in a follow up Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/lib/cbfs.c M src/lib/fmap.c M src/lib/prog_loaders.c M src/lib/prog_ops.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc A src/security/vboot/vboot_crtm.c A src/security/vboot/vboot_crtm.h M src/security/vboot/vboot_logic.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M util/abuild/abuild 22 files changed, 391 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29547/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 54 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 14 Feb '19

14 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#31). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 22 files changed, 183 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 31 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: binaryPI: Fix cache coherency use for AP CPUs
by Kyösti Mälkki (Code Review) 14 Feb '19

14 Feb '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26115 ) Change subject: binaryPI: Fix cache coherency use for AP CPUs ...................................................................... binaryPI: Fix cache coherency use for AP CPUs The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc 4 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Richard Spiegel: Looks good to me, approved Michał Żygowski: Looks good to me, approved diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index f444852..51c6b52 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -1438,6 +1438,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index 0fbcf77..b9cc39f 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -1179,6 +1179,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index 2399bec..4694632 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -1158,6 +1158,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index 7e12db1..6c4ad59 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -1153,6 +1153,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR # + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR -- To view, visit https://review.coreboot.org/c/coreboot/+/26115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Gerrit-Change-Number: 26115 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: binaryPI: Fix cache coherency use for AP CPUs
by Kyösti Mälkki (Code Review) 14 Feb '19

14 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26115 ) Change subject: binaryPI: Fix cache coherency use for AP CPUs ...................................................................... Patch Set 9: > Patch Set 9: > > > Patch Set 8: Code-Review+1 > > > > > Although still cbmem utility reports: > > > *** Pre-CBMEM romstage console overflowed, log truncated! *** > > > > > > Is there not enough "space" during CAR to store the whole log? Tried setting cbmem console area size to 256KiB, but it seems not to be the case. > > > > You need to adapt `PRERAM_CBMEM_CONSOLE_SIZE` as far as I know. > > Yes, it works. Thank You. Only sort-of. There is neither build-time or runtime detection what is a safe limit here with binaryPI. CAR setup is.. well complex. -- To view, visit https://review.coreboot.org/c/coreboot/+/26115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Gerrit-Change-Number: 26115 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 15:16:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: binaryPI: Fix cache coherency use for AP CPUs
by Michał Żygowski (Code Review) 14 Feb '19

14 Feb '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26115 ) Change subject: binaryPI: Fix cache coherency use for AP CPUs ...................................................................... Patch Set 9: Sorry Kyösti, accidentally changed Uploader and Committer when uploading related patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/26115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Gerrit-Change-Number: 26115 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 15:07:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: binaryPI: Fix cache coherency use for AP CPUs
by Michał Żygowski (Code Review) 14 Feb '19

14 Feb '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26115 ) Change subject: binaryPI: Fix cache coherency use for AP CPUs ...................................................................... Patch Set 9: > Patch Set 8: Code-Review+1 > > > Although still cbmem utility reports: > > *** Pre-CBMEM romstage console overflowed, log truncated! *** > > > > Is there not enough "space" during CAR to store the whole log? Tried setting cbmem console area size to 256KiB, but it seems not to be the case. > > You need to adapt `PRERAM_CBMEM_CONSOLE_SIZE` as far as I know. Yes, it works. Thank You. -- To view, visit https://review.coreboot.org/c/coreboot/+/26115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Gerrit-Change-Number: 26115 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 15:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019