coreboot-gerrit February 2019

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Change in ...coreboot[master]: util/ifdtools: Make EC region readable to BIOS/CPU
by Bora Guvendik (Code Review) 14 Feb '19

14 Feb '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31377 Change subject: util/ifdtools: Make EC region readable to BIOS/CPU ...................................................................... util/ifdtools: Make EC region readable to BIOS/CPU Allow EC region to be readable by BIOS/CPU so that flashrom can read it. BUG=b:123199222 TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, run firmware_LockedME test. Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31377/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 85623fd..a97f352 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -969,8 +969,8 @@ case PLATFORM_CNL: case PLATFORM_ICL: case PLATFORM_SKLKBL: - /* CPU/BIOS can read descriptor, BIOS and GbE. */ - fmba->flmstr1 |= 0xb << rd_shift; + /* CPU/BIOS can read descriptor, BIOS, EC and GbE. */ + fmba->flmstr1 |= 0x10b << rd_shift; /* CPU/BIOS can write BIOS and Gbe. */ fmba->flmstr1 |= 0xa << wr_shift; /* ME can read descriptor, ME and GbE. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306 Gerrit-Change-Number: 31377 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by build bot (Jenkins) (Code Review) 14 Feb '19

14 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 51: (14 comments) https://review.coreboot.org/#/c/29547/51/src/lib/cbfs.c File src/lib/cbfs.c: https://review.coreboot.org/#/c/29547/51/src/lib/cbfs.c@39 PS51, Line 39: uint32_t __weak vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type) line over 80 characters https://review.coreboot.org/#/c/29547/51/src/lib/cbfs.c@106 PS51, Line 106: size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) line over 80 characters https://review.coreboot.org/#/c/29547/51/src/lib/cbfs.c@119 PS51, Line 119: if ((ENV_BOOTBLOCK || ENV_VERSTAGE) && !IS_ENABLED(CONFIG_COMPRESS_PRERAM_STAGES)) line over 80 characters https://review.coreboot.org/#/c/29547/51/src/lib/cbfs.c@261 PS51, Line 261: if (ENV_VERSTAGE && !IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES) && IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) { line over 80 characters https://review.coreboot.org/#/c/29547/51/src/lib/fmap.c File src/lib/fmap.c: https://review.coreboot.org/#/c/29547/51/src/lib/fmap.c@31 PS51, Line 31: uint32_t __weak vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type) line over 80 characters https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_crtm.h File src/security/vboot/vboot_crtm.h: https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_crtm.h@70 PS51, Line 70: uint32_t vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type); line over 80 characters https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_crtm.c@154 PS51, Line 154: uint32_t vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type) line over 80 characters https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c@98 PS51, Line 98: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c@1… PS51, Line 104: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c@2… PS51, Line 281: return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); line over 80 characters https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c@3… PS51, Line 308: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) line over 80 characters https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c@3… PS51, Line 319: if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { line over 80 characters https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c@3… PS51, Line 324: if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) line over 80 characters https://review.coreboot.org/#/c/29547/51/src/security/vboot/vboot_logic.c@3… PS51, Line 333: if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 51 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 07:48:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Philipp Deppenwiese (Code Review) 14 Feb '19

14 Feb '19

Hello Patrick Rudolph, Aaron Durbin, Piotr Król, Julius Werner, Krystian Hebel, Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Werner Zeh, Huang Jin, York Yang, David Hendricks, Martin Roth, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29547 to look at the new patch set (#51). Change subject: security/vboot: Add measured boot mode ...................................................................... security/vboot: Add measured boot mode * Introduce a measured boot mode into vboot. * Add hook for stage measurements in prog_ops. * Implement and hook-up CRTM in vboot and check for suspend. * Documentation will be done in a follow up Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/lib/cbfs.c M src/lib/fmap.c M src/lib/prog_loaders.c M src/lib/prog_ops.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc A src/security/vboot/vboot_crtm.c A src/security/vboot/vboot_crtm.h M src/security/vboot/vboot_logic.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M util/abuild/abuild 22 files changed, 402 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29547/51 -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 51 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by build bot (Jenkins) (Code Review) 14 Feb '19

14 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 50: (15 comments) https://review.coreboot.org/#/c/29547/50/src/lib/cbfs.c File src/lib/cbfs.c: https://review.coreboot.org/#/c/29547/50/src/lib/cbfs.c@39 PS50, Line 39: uint32_t __weak vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type) line over 80 characters https://review.coreboot.org/#/c/29547/50/src/lib/cbfs.c@106 PS50, Line 106: size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) line over 80 characters https://review.coreboot.org/#/c/29547/50/src/lib/cbfs.c@119 PS50, Line 119: if ((ENV_BOOTBLOCK || ENV_VERSTAGE) && !IS_ENABLED(CONFIG_COMPRESS_PRERAM_STAGES)) line over 80 characters https://review.coreboot.org/#/c/29547/50/src/lib/cbfs.c@261 PS50, Line 261: if (ENV_VERSTAGE && !IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES) && IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) { line over 80 characters https://review.coreboot.org/#/c/29547/50/src/lib/fmap.c File src/lib/fmap.c: https://review.coreboot.org/#/c/29547/50/src/lib/fmap.c@31 PS50, Line 31: uint32_t __weak vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type) line over 80 characters https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_crtm.h File src/security/vboot/vboot_crtm.h: https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_crtm.h@70 PS50, Line 70: uint32_t vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type); line over 80 characters https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_crtm.c@154 PS50, Line 154: uint32_t vboot_measure_region_hook(const struct region_device *region, const char *name, uint32_t type) line over 80 characters https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_crtm.c@213 PS50, Line 213: } adding a line without newline at end of file https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c@98 PS50, Line 98: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c@1… PS50, Line 104: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c@2… PS50, Line 281: return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); line over 80 characters https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c@3… PS50, Line 308: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) line over 80 characters https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c@3… PS50, Line 319: if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { line over 80 characters https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c@3… PS50, Line 324: if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) line over 80 characters https://review.coreboot.org/#/c/29547/50/src/security/vboot/vboot_logic.c@3… PS50, Line 333: if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 50 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 07:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Philipp Deppenwiese (Code Review) 14 Feb '19

14 Feb '19

Hello Patrick Rudolph, Aaron Durbin, Piotr Król, Julius Werner, Krystian Hebel, Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Werner Zeh, Huang Jin, York Yang, David Hendricks, Martin Roth, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29547 to look at the new patch set (#50). Change subject: security/vboot: Add measured boot mode ...................................................................... security/vboot: Add measured boot mode * Introduce a measured boot mode into vboot. * Add hook for stage measurements in prog_ops. * Implement and hook-up CRTM in vboot and check for suspend. * Documentation will be done in a follow up Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/lib/cbfs.c M src/lib/fmap.c M src/lib/prog_loaders.c M src/lib/prog_ops.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc A src/security/vboot/vboot_crtm.c A src/security/vboot/vboot_crtm.h M src/security/vboot/vboot_logic.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M util/abuild/abuild 22 files changed, 402 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29547/50 -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 50 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: binaryPI: Fix cache coherency use for AP CPUs
by Kyösti Mälkki (Code Review) 14 Feb '19

14 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26115 ) Change subject: binaryPI: Fix cache coherency use for AP CPUs ...................................................................... Patch Set 8: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/26115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Gerrit-Change-Number: 26115 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Feb 2019 03:40:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: binaryPI: Fix cache coherency use for AP CPUs
by Kyösti Mälkki (Code Review) 14 Feb '19

14 Feb '19

Kyösti Mälkki has removed a vote on this change. Change subject: binaryPI: Fix cache coherency use for AP CPUs ...................................................................... Removed Code-Review-2 by Kyösti Mälkki <kyosti.malkki(a)gmail.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/26115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Gerrit-Change-Number: 26115 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteVote

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Change in ...coreboot[master]: mb/google/kahlee/variants/liara: Update eDP power off timing sequence
by chris wang (Code Review) 14 Feb '19

14 Feb '19

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30042 ) Change subject: mb/google/kahlee/variants/liara: Update eDP power off timing sequence ...................................................................... Patch Set 1: sorry just notice this message. Thanks, Martin! -- To view, visit https://review.coreboot.org/c/coreboot/+/30042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5540db34fa2d1fdea9326a2131c3ed50aacbaa9b Gerrit-Change-Number: 30042 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Thu, 14 Feb 2019 03:01:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 14 Feb '19

14 Feb '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 14 Feb 2019 01:36:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd: Add Merlin Falcon soc code
by Richard Spiegel (Code Review) 14 Feb '19

14 Feb '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31232 Change subject: soc/amd: Add Merlin Falcon soc code ...................................................................... soc/amd: Add Merlin Falcon soc code In preparation to add padmelon to coreboot, add the the code for the soc Merlin Falcon used by padmelon. BUG=b:none. TEST=Tested later with pasmelon board. Change-Id: I66cbf4c9a74b7726cbf5d483f6ca3f998442a51f Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/Kconfig A src/soc/amd/merlinfalcon/BiosCallOuts.c A src/soc/amd/merlinfalcon/Kconfig A src/soc/amd/merlinfalcon/Makefile.inc A src/soc/amd/merlinfalcon/acpi.c A src/soc/amd/merlinfalcon/acpi/AmdImc.asl A src/soc/amd/merlinfalcon/acpi/acpi_wake_source.asl A src/soc/amd/merlinfalcon/acpi/cpu.asl A src/soc/amd/merlinfalcon/acpi/globalnvs.asl A src/soc/amd/merlinfalcon/acpi/gpio_lib.asl A src/soc/amd/merlinfalcon/acpi/lpc.asl A src/soc/amd/merlinfalcon/acpi/northbridge.asl A src/soc/amd/merlinfalcon/acpi/pci_int.asl A src/soc/amd/merlinfalcon/acpi/pcie.asl A src/soc/amd/merlinfalcon/acpi/sb_fch.asl A src/soc/amd/merlinfalcon/acpi/sb_pci0_fch.asl A src/soc/amd/merlinfalcon/acpi/sleepstates.asl A src/soc/amd/merlinfalcon/acpi/soc.asl A src/soc/amd/merlinfalcon/acpi/usb.asl A src/soc/amd/merlinfalcon/bootblock/bootblock.c A src/soc/amd/merlinfalcon/chip.c A src/soc/amd/merlinfalcon/chip.h A src/soc/amd/merlinfalcon/cpu.c A src/soc/amd/merlinfalcon/enable_usbdebug.c A src/soc/amd/merlinfalcon/finalize.c A src/soc/amd/merlinfalcon/gpio.c A src/soc/amd/merlinfalcon/hda.c A src/soc/amd/merlinfalcon/i2c.c A src/soc/amd/merlinfalcon/imc.c A src/soc/amd/merlinfalcon/include/soc/acpi.h A src/soc/amd/merlinfalcon/include/soc/amd_pci_int_defs.h A src/soc/amd/merlinfalcon/include/soc/cpu.h A src/soc/amd/merlinfalcon/include/soc/fchec.h A src/soc/amd/merlinfalcon/include/soc/gpio.h A src/soc/amd/merlinfalcon/include/soc/imc.h A src/soc/amd/merlinfalcon/include/soc/iomap.h A src/soc/amd/merlinfalcon/include/soc/northbridge.h A src/soc/amd/merlinfalcon/include/soc/nvs.h A src/soc/amd/merlinfalcon/include/soc/pci_devs.h A src/soc/amd/merlinfalcon/include/soc/romstage.h A src/soc/amd/merlinfalcon/include/soc/smbus.h A src/soc/amd/merlinfalcon/include/soc/smi.h A src/soc/amd/merlinfalcon/include/soc/southbridge.h A src/soc/amd/merlinfalcon/iommu.c A src/soc/amd/merlinfalcon/lpc.c A src/soc/amd/merlinfalcon/mca.c A src/soc/amd/merlinfalcon/monotonic_timer.c A src/soc/amd/merlinfalcon/nb_util.c A src/soc/amd/merlinfalcon/northbridge.c A src/soc/amd/merlinfalcon/pmutil.c A src/soc/amd/merlinfalcon/ramtop.c A src/soc/amd/merlinfalcon/reset.c A src/soc/amd/merlinfalcon/romstage.c A src/soc/amd/merlinfalcon/sata.c A src/soc/amd/merlinfalcon/sb_util.c A src/soc/amd/merlinfalcon/sm.c A src/soc/amd/merlinfalcon/smbus.c A src/soc/amd/merlinfalcon/smbus_spd.c A src/soc/amd/merlinfalcon/smi.c A src/soc/amd/merlinfalcon/smi_util.c A src/soc/amd/merlinfalcon/smihandler.c A src/soc/amd/merlinfalcon/southbridge.c A src/soc/amd/merlinfalcon/spi.c A src/soc/amd/merlinfalcon/tsc_freq.c A src/soc/amd/merlinfalcon/uart.c A src/soc/amd/merlinfalcon/usb.c 66 files changed, 11,686 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31232/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66cbf4c9a74b7726cbf5d483f6ca3f998442a51f Gerrit-Change-Number: 31232 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019