coreboot-gerrit February 2019

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Add GPIO H3 and H15 for DVT1
by John Su (Code Review) 13 Feb '19

13 Feb '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31330 Change subject: mb/google/sarien/variants/sarien: Add GPIO H3 and H15 for DVT1 ...................................................................... mb/google/sarien/variants/sarien: Add GPIO H3 and H15 for DVT1 Follow b:123342945 to add GPIO H3 and H15 for DVT1. BUG=b:123342945 TEST=Built and tested on sarien system Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/31330/1 diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index f773265..6c20f4e 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -188,7 +188,7 @@ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ /* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */ @@ -200,7 +200,7 @@ /* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE), +/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), /* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), /* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8 Gerrit-Change-Number: 31330 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: coreboot: check TPM mode on normal boot
by Keith Short (Code Review) 13 Feb '19

13 Feb '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31260 Change subject: coreboot: check TPM mode on normal boot ...................................................................... coreboot: check TPM mode on normal boot When booting into Alt OS legacy mode, the TPM is disabled before handing off control to the OS. On a reboot back to Chrome OS, we must check the TPM mode. If TPM or key-ladder is disabled, trigger a reboot of the Cr50 to restore TPM functionality. BUG=b:121463033 BRANCH=none TEST=Built depthcharge on sarien and grunt platforms. TEST=Ran 'gsctool -a -m disable' and reboot. Verfied coreboot sends VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and then the platform boots normally. Tested-by: Keith Short <keithshort(a)chromium.org> Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/include/elog.h M src/mainboard/google/sarien/chromeos.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss/vendor/cr50/cr50.h M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/cr50_enable_update.c 8 files changed, 203 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31260/1 diff --git a/src/include/elog.h b/src/include/elog.h index 31891e0..f1d5314 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -223,6 +223,9 @@ #define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 #define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + struct elog_event_extended_event { u8 event_type; u32 event_complement; diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index f9e42e0..9466124 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -116,7 +116,7 @@ return 1; } -void mainboard_cr50_update_reset(void) +void mainboard_prepare_cr50_reset(void) { #if ENV_RAMSTAGE /* Ensure system powers up after CR50 reset */ diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index f1c5a37..991e9a6 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -266,6 +266,10 @@ uint16_t *sub_command = command_body; switch (*sub_command) { + case TPM2_CR50_SUB_CMD_IMMEDIATE_RESET: + rc |= obuf_write_be16(ob, sub_command[0]); + rc |= obuf_write_be16(ob, sub_command[1]); + break; case TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS: rc |= obuf_write_be16(ob, *sub_command); break; @@ -276,6 +280,18 @@ case TPM2_CR50_SUB_CMD_GET_REC_BTN: rc |= obuf_write_be16(ob, *sub_command); break; + case TPM2_CR50_SUB_CMD_TPM_MODE: + /* The Cr50 TPM_MODE command supports an optional parameter. + * When the parameter is present the Cr50 will attempt to change + * the TPM state (enable or disable) and returns the new state + * in the response. When the parameter is absent, the Cr50 + * returns the current TPM state. + * + * Coreboot currently only uses the TPM get capability and does + * not set a new TPM state with the Cr50. + */ + rc |= obuf_write_be16(ob, *sub_command); + break; default: /* Unsupported subcommand. */ printk(BIOS_WARNING, "Unsupported cr50 subcommand: 0x%04x\n", @@ -471,12 +487,16 @@ return -1; switch (vcr->vc_subcommand) { + case TPM2_CR50_SUB_CMD_IMMEDIATE_RESET: + break; case TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS: break; case TPM2_CR50_SUB_CMD_TURN_UPDATE_ON: return ibuf_read_be8(ib, &vcr->num_restored_headers); case TPM2_CR50_SUB_CMD_GET_REC_BTN: return ibuf_read_be8(ib, &vcr->recovery_button_state); + case TPM2_CR50_SUB_CMD_TPM_MODE: + return ibuf_read_be8(ib, &vcr->tpm_mode); default: printk(BIOS_ERR, "%s:%d - unsupported vendor command %#04x!\n", diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 6952169..991cbcf 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -298,6 +298,7 @@ union { uint8_t num_restored_headers; uint8_t recovery_button_state; + uint8_t tpm_mode; }; }; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index 450ad97..97954db 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -68,3 +68,55 @@ *recovery_button_state = response->vcr.recovery_button_state; return TPM_SUCCESS; } + +uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode, int *cr50_must_reset) +{ + struct tpm2_response *response; + uint16_t mode_command = TPM2_CR50_SUB_CMD_TPM_MODE; + *cr50_must_reset = 0; + *tpm_mode = TPM_MODE_INVALID; + + printk(BIOS_INFO, "Reading cr50 TPM mode\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command); + + if (!response) + return TPM_E_INTERNAL_INCONSISTENCY; + + if (response->hdr.tpm_code == VENDOR_RC_INTERNAL_ERROR) { + /* + * The Cr50 returns VENDOR_RC_INTERNAL_ERROR iff the key ladder + * is disabled. The Cr50 requires a reboot to re-enable the key + * ladder. + */ + *cr50_must_reset = 1; + } else if (response->hdr.tpm_code) { + /* Only other error expected is VENDOR_RC_NO_SUCH_SUBCOMMAND + * if communicating with a down rev Cr50 firmware. + */ + return TPM_E_INTERNAL_INCONSISTENCY; + } else + *tpm_mode = response->vcr.tpm_mode; + + return (TPM_SUCCESS); +} + +uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms) +{ + struct tpm2_response *response; + uint16_t reset_command_body[] = { + TPM2_CR50_SUB_CMD_IMMEDIATE_RESET, timeout_ms + }; + + /* + * Issue an immediate reset to the Cr50. + */ + printk(BIOS_INFO, "Issuing Cr50 reset\n"); + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, + &reset_command_body); + + if (!response) + return TPM_E_INTERNAL_INCONSISTENCY; + + return TPM_SUCCESS; +} diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index a1ab539..94b825f 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -23,9 +23,32 @@ to extending generically because the marshaling code is assuming all knowledge of all commands. */ #define TPM2_CR50_VENDOR_COMMAND ((TPM_CC)(TPM_CC_VENDOR_BIT_MASK | 0)) +#define TPM2_CR50_SUB_CMD_IMMEDIATE_RESET (19) #define TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS (21) #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24) #define TPM2_CR50_SUB_CMD_GET_REC_BTN (29) +#define TPM2_CR50_SUB_CMD_TPM_MODE (40) + +/* Cr50 vendor-specific error codes. */ +#define VENDOR_RC_ERR 0x00000500 +enum cr50_vendor_rc { + VENDOR_RC_INTERNAL_ERROR = (VENDOR_RC_ERR | 6), + VENDOR_RC_NO_SUCH_COMMAND = (VENDOR_RC_ERR | 127), +}; + +enum cr50_tpm_mode { + /* TPM is enabled, and may be set to either ENABLED or DISABLED mode. */ + TPM_MODE_ENABLED = 0, + + /* TPM is enabled, and mode may not be changed. */ + TPM_MODE_LOCKED_ENABLED = 1, + + /* TPM is disabled, and mode may not be changed. */ + TPM_MODE_LOCKED_DISABLED = 2, + + TPM_MODE_INVALID, +}; + /** * CR50 specific tpm command to enable nvmem commits before internal timeout @@ -53,4 +76,24 @@ */ uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state); +/** + * CR50 specific TPM command sequence to query the current TPM mode. + * + * Returns value indicates success or failure of accessing the TPM; in case of + * success the cr50_must_reset output parameter indicates if the Cr50 must be + * reset to restore full capability. On success, the tpm_mode parameter is + * set to the current TPM mode. + */ +uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode, int *cr50_must_reset); + +/** + * CR50 specific TPM command sequence to trigger an immediate reset to the Cr50 + * device after the specified timeout in milliseconds. A timeout of zero means + * "IMMEDIATE REBOOT". + * + * Returns value indicates success or failure of accessing the TPM. + */ +uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms); + + #endif /* CR50_TSS_STRUCTURES_H_ */ diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index f7e2ae9..6831261 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -33,8 +33,11 @@ static inline void reboot_from_watchdog(void) { return; } #endif /* CONFIG_CHROMEOS */ -/* Defined as weak function in cr50_enable_update.c */ -void mainboard_cr50_update_reset(void); +/** + * Perform any platform specific actions required prior to resetting the Cr50. + * Defined as weak function in cr50_enable_update.c + */ +void mainboard_prepare_cr50_reset(void); struct romstage_handoff; diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index da9a16d..31aad90 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -22,8 +22,58 @@ #include <vb2_api.h> #include <security/vboot/vboot_common.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <delay.h> -void __weak mainboard_cr50_update_reset(void) {} +#define C50_RESET_DELAY_MS 1000 + +void __weak mainboard_prepare_cr50_reset(void) {} + +/** + * Check of the Cr50 TPM state requires a chip reset of the Cr50 device. + * + * Returns 0 if the Cr50 TPM state is good (or cannot be determined). Returns 1 + * if the Cr50 was reset. + */ +static int cr50_check_tpm(uint16_t timeout_ms) +{ + int ret; + int cr50_must_reset = 0; + uint8_t tpm_mode; + + ret = tlcl_cr50_get_tpm_mode(&tpm_mode, &cr50_must_reset); + + if (ret != TPM_SUCCESS) { + /* TPM command failed, continue booting. */ + printk(BIOS_ERR, + "Attempt to get CR50 TPM mode failed: %x\n", + ret); + return 0; + } + + /* If the TPM mode has been locked, a Cr50 reset is required as vboot + * may need to disable the TPM. + */ + if (tpm_mode != TPM_MODE_ENABLED) { + cr50_must_reset = 1; + } + + /* If TPM state is okay, no reset needed. */ + if (!cr50_must_reset) + return 0; + + ret = tlcl_cr50_immediate_reset(timeout_ms); + + if (ret != TPM_SUCCESS) { + /* TPM command failed, continue booting. */ + printk(BIOS_ERR, + "Attempt to reset CR50 failed: %x\n", + ret); + return 0; + } + + /* Cr50 was reset successfully */ + return 1; +} static void enable_update(void *unused) { @@ -43,7 +93,8 @@ } /* Reboot in 1000 ms if necessary. */ - ret = tlcl_cr50_enable_update(1000, &num_restored_headers); + ret = tlcl_cr50_enable_update(C50_RESET_DELAY_MS, + &num_restored_headers); if (ret != TPM_SUCCESS) { printk(BIOS_ERR, "Attempt to enable CR50 update failed: %x\n", @@ -51,20 +102,37 @@ return; } - /* If no headers were restored there is no reset forthcoming. */ - if (!num_restored_headers) - return; + if (!num_restored_headers) { + /* If no headers were restored there is no reset forthcoming due + * to a Cr50 firmware update. Also check if the Cr50 TPM mode + * requires a reset. + * + * TODO: to eliminate a TPM command during every boot, the + * TURN_UPDATE_ON command could be enhanced/replaced in the Cr50 + * firmware to perform the TPM mode/key-ladder check in addition + * to the FW version check. + */ + + /* + * If the Cr50 was not reset, continue booting. + */ + if (!cr50_check_tpm(C50_RESET_DELAY_MS)) + return; + + printk(BIOS_INFO, "Waiting for CR50 reset to enable TPM.\n"); + elog_add_event(ELOG_TYPE_CR50_NEED_RESET); + } else { + printk(BIOS_INFO, + "Waiting for CR50 reset to pick up update.\n"); + elog_add_event(ELOG_TYPE_CR50_UPDATE); + } /* Give mainboard a chance to take action */ - mainboard_cr50_update_reset(); - - elog_add_event(ELOG_TYPE_CR50_UPDATE); + mainboard_prepare_cr50_reset(); /* clear current post code avoid chatty eventlog on subsequent boot*/ post_code(0); - printk(BIOS_INFO, "Waiting for CR50 reset to pick up update.\n"); - if (IS_ENABLED(CONFIG_POWER_OFF_ON_CR50_UPDATE)) poweroff(); halt(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a Gerrit-Change-Number: 31260 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Configure touchpad GPIO pad for non-inversion
by Aamir Bohra (Code Review) 13 Feb '19

13 Feb '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31328 Change subject: mb/google/hatch: Configure touchpad GPIO pad for non-inversion ...................................................................... mb/google/hatch: Configure touchpad GPIO pad for non-inversion This implementation configures touchpad GPIO(GPP_A21) pad in non-inversion mode i.e Rx PAD state is not inverted as it is sent from GPIO to IOAPIC. BUG=b:123315212 TEST=Verify touchpad is working fine Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/31328/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index f8d5d7d..37e16ec 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -28,7 +28,7 @@ /* WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* TRACKPAD_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, NONE), /* SRCCLKREQ1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_14_WLAN_CLKREQ_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5 Gerrit-Change-Number: 31328 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: Add Nehalem for FSB detection
by Kyösti Mälkki (Code Review) 13 Feb '19

13 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31339 Change subject: cpu/intel/common: Add Nehalem for FSB detection ...................................................................... cpu/intel/common: Add Nehalem for FSB detection Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31339/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 9296785..83220de 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -39,8 +39,11 @@ case 0x17: /* Enhanced Core */ ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; - case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ - case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x25: /* Nehalem BCLK fixed at 133MHz */ + ret = 133; + break; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ ret = 100; -- To view, visit https://review.coreboot.org/c/coreboot/+/31339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Gerrit-Change-Number: 31339 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: cpu/intel/common: Split get_ia32_fsb()
by Kyösti Mälkki (Code Review) 13 Feb '19

13 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31338 Change subject: cpu/intel/common: Split get_ia32_fsb() ...................................................................... cpu/intel/common: Split get_ia32_fsb() It is desireable to not have printk() inside a function body that can be used for udelay(). This avoids potential infinite recursion. Change-Id: Ie67fc2a8da8351f22794e4d36c55b887c298e8ca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31338/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 1f7c391..9296785 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -18,7 +18,7 @@ #include <console/console.h> #include <commonlib/helpers.h> -int get_ia32_fsb(void) +static int get_fsb(void) { struct cpuinfo_x86 c; static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; @@ -60,6 +60,14 @@ break; } } + return ret; +} + +int get_ia32_fsb(void) +{ + int ret; + + ret = get_fsb(); if (ret == -1) printk(BIOS_ERR, "FSB not found\n"); if (ret == -2) -- To view, visit https://review.coreboot.org/c/coreboot/+/31338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie67fc2a8da8351f22794e4d36c55b887c298e8ca Gerrit-Change-Number: 31338 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Don't use CAR_GLOBAL
by Patrick Georgi (Code Review) 13 Feb '19

13 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30515 ) Change subject: soc/intel/icelake: Don't use CAR_GLOBAL ...................................................................... soc/intel/icelake: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30515 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/icelake/romstage/romstage.c 2 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Aaron Durbin: Looks good to me, approved diff --git a/src/soc/intel/icelake/romstage/power_state.c b/src/soc/intel/icelake/romstage/power_state.c index 3f1a211..fd25217 100644 --- a/src/soc/intel/icelake/romstage/power_state.c +++ b/src/soc/intel/icelake/romstage/power_state.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 432cae5..3df4f4f 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -14,7 +14,6 @@ */ #include <arch/io.h> -#include <arch/early_variables.h> #include <assert.h> #include <chip.h> #include <cpu/x86/mtrr.h> @@ -33,7 +32,7 @@ #include <string.h> #include <timestamp.h> -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -112,7 +111,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps = car_get_var_ptr(&power_state); + struct chipset_power_state *ps = &power_state; console_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/30515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Gerrit-Change-Number: 30515 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/baytrail: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 13 Feb '19

13 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30511 Change subject: soc/intel/baytrail: Don't use CAR_GLOBAL ...................................................................... soc/intel/baytrail: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30511/1 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 0e1d57e..72ded61 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -134,7 +134,7 @@ return NULL; } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3 Gerrit-Change-Number: 30511 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/broadwell: Don't use CAR_GLOBAL
by Patrick Georgi (Code Review) 13 Feb '19

13 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30513 ) Change subject: soc/intel/broadwell: Don't use CAR_GLOBAL ...................................................................... soc/intel/broadwell: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Idca207b4f05d1844ce6612dbecaad6faeb68725a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30513 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/romstage/power_state.c 1 file changed, 3 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index cfb2418..2affb26 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <arch/io.h> #include <cbmem.h> #include <console/console.h> @@ -30,14 +29,14 @@ #include <soc/pm.h> #include <soc/romstage.h> -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; struct chipset_power_state *ps_car; - ps_car = car_get_var_ptr(&power_state); + ps_car = &power_state; ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { @@ -99,7 +98,7 @@ /* Fill power state structure from ACPI PM registers */ struct chipset_power_state *fill_power_state(void) { - struct chipset_power_state *ps = car_get_var_ptr(&power_state); + struct chipset_power_state *ps = &power_state; ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/30513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca207b4f05d1844ce6612dbecaad6faeb68725a Gerrit-Change-Number: 30513 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/cannonlake: Don't use CAR_GLOBAL
by Patrick Georgi (Code Review) 13 Feb '19

13 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30514 ) Change subject: soc/intel/cannonlake: Don't use CAR_GLOBAL ...................................................................... soc/intel/cannonlake: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30514 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/sarien/chromeos.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/cannonlake/romstage/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index f9e42e0..4cd6e16 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -14,7 +14,6 @@ */ #include <arch/acpi.h> -#include <arch/early_variables.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> @@ -31,7 +30,7 @@ REC_MODE_NOT_REQUESTED, REC_MODE_REQUESTED, }; -static enum rec_mode_state saved_rec_mode CAR_GLOBAL; +static enum rec_mode_state saved_rec_mode; void fill_lb_gpios(struct lb_gpios *gpios) { @@ -85,7 +84,7 @@ int get_recovery_mode_switch(void) { - enum rec_mode_state state = car_get_var(saved_rec_mode); + enum rec_mode_state state = saved_rec_mode; uint8_t recovery_button_state = 0; /* Check the global variable first. */ @@ -106,7 +105,7 @@ REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; /* Store the state in case this is called again in verstage. */ - car_set_var(saved_rec_mode, state); + saved_rec_mode = state; return state == REC_MODE_REQUESTED; } diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c index 99a93ac..4214fcc 100644 --- a/src/soc/intel/cannonlake/romstage/power_state.c +++ b/src/soc/intel/cannonlake/romstage/power_state.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9224ba6..9e25e55 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,7 +14,6 @@ */ #include <arch/io.h> -#include <arch/early_variables.h> #include <assert.h> #include <chip.h> #include <cpu/x86/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/30514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Gerrit-Change-Number: 30514 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: superio/nsc/pc87417: Use common early_serial
by Felix Held (Code Review) 13 Feb '19

13 Feb '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31337 ) Change subject: superio/nsc/pc87417: Use common early_serial ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32fa5970ca7ca634833a0e39da66c1f89ed33fe Gerrit-Change-Number: 31337 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 13 Feb 2019 10:08:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2019