coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: drivers/i2c/lm96000: Add new hardware-monitoring IC
by Felix Held (Code Review) 13 Feb '19

13 Feb '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21194 ) Change subject: drivers/i2c/lm96000: Add new hardware-monitoring IC ...................................................................... Patch Set 8: please have a look at my comments on patch set 4 -- To view, visit https://review.coreboot.org/c/coreboot/+/21194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7df3107bffb7f8e45e71c4c1fbe4eb0a9e3cd03 Gerrit-Change-Number: 21194 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 13 Feb 2019 09:54:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: drivers/i2c/nct7802y: Add new hardware-monitoring IC
by Felix Held (Code Review) 13 Feb '19

13 Feb '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29475 ) Change subject: drivers/i2c/nct7802y: Add new hardware-monitoring IC ...................................................................... Patch Set 5: (2 comments) my other comments from the first patch set are already addressed, but those two remain https://review.coreboot.org/#/c/29475/5/src/drivers/i2c/nct7802y/nct7802y_f… File src/drivers/i2c/nct7802y/nct7802y_fan.c: https://review.coreboot.org/#/c/29475/5/src/drivers/i2c/nct7802y/nct7802y_f… PS5, Line 68: div did you check what I commented on this line in patchset 1? https://review.coreboot.org/#/c/29475/5/src/drivers/i2c/nct7802y/nct7802y_f… PS5, Line 82: return; I'd print a warning in this case -- To view, visit https://review.coreboot.org/c/coreboot/+/29475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ea79e12941804e398c6304a08170a776f4ca76 Gerrit-Change-Number: 29475 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Feb 2019 09:52:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4
by Uwe Poeche (Code Review) 13 Feb '19

13 Feb '19

Uwe Poeche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31344 Change subject: siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4 ...................................................................... siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4 This patch provides the necessary changes to get HW TPM working. Change-Id: I9af7e1a8623302eca46f5ecd8e498678ccda92ad Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31344/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 247b052..060d695 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -6,6 +6,9 @@ select DRIVER_INTEL_I210 select APL_SET_MIN_CLOCK_RATIO select DRIVERS_I2C_RX6110SA + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM + select TPM_ON_FAST_SPI config UART_FOR_CONSOLE default 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 4928701..8aaf32e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -102,7 +102,12 @@ device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO - device pci 1f.0 on end # - LPC + device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # - LPC device pci 1f.1 on end # - SMBUS end end + -- To view, visit https://review.coreboot.org/c/coreboot/+/31344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9af7e1a8623302eca46f5ecd8e498678ccda92ad Gerrit-Change-Number: 31344 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: siemens/mc_apl2: Remove double entry into devicetree
by Mario Scheithauer (Code Review) 13 Feb '19

13 Feb '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31345 Change subject: siemens/mc_apl2: Remove double entry into devicetree ...................................................................... siemens/mc_apl2: Remove double entry into devicetree Remove a double entry for LPC device in the devicetree. Change-Id: Ib5b4f760251236d6a8b4aba719666daa97e7813d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31345/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 7a0b886..42c474e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -105,7 +105,6 @@ device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO - device pci 1f.0 on end # - LPC device pci 1f.0 on # - LPC chip drivers/pc80/tpm device pnp 0c31.0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/31345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5b4f760251236d6a8b4aba719666daa97e7813d Gerrit-Change-Number: 31345 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by Xiang Wang (Code Review) 13 Feb '19

13 Feb '19

Xiang Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 30 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: riscv: save FDT pointer from mscratch to HLS
by Xiang Wang (Code Review) 13 Feb '19

13 Feb '19

Xiang Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27545 ) Change subject: riscv: save FDT pointer from mscratch to HLS ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5 Gerrit-Change-Number: 27545 Gerrit-PatchSet: 29 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary
by Xiang Wang (Code Review) 13 Feb '19

13 Feb '19

Xiang Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29916 ) Change subject: Fix coreboot table record alignment to 8-byte boundary ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846be0e26ab3c81858d8cf727517e1462035e64 Gerrit-Change-Number: 29916 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Subrata Banik (Code Review) 13 Feb '19

13 Feb '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31375 ) Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Wed, 13 Feb 2019 05:24:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Rizwan Qureshi (Code Review) 13 Feb '19

13 Feb '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31375 ) Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Wed, 13 Feb 2019 05:12:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: RFC: riscv: Add initial support for 32bit boards
by Philipp Hug (Code Review) 13 Feb '19

13 Feb '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31253 Change subject: RFC: riscv: Add initial support for 32bit boards ...................................................................... RFC: riscv: Add initial support for 32bit boards * Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * Should we choose between rv32/rv64 per stage? ARCH_BOOTBLOCK_RISCV_RV32? How can we do that without having a separate rv32 toolchain? TEST=Boots to "Payload not loaded." on 32bit qemu Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/bootblock.S M src/arch/riscv/include/arch/smp/atomic.h M src/arch/riscv/include/bits.h M src/arch/riscv/include/mcall.h M src/arch/riscv/ramstage.S M src/arch/riscv/smp.c M src/lib/libgcc.c M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig.name M src/mainboard/emulation/spike-riscv/Kconfig M src/soc/ucb/riscv/Kconfig 12 files changed, 89 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31253/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 9d91f0c..d5f6295 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -86,6 +86,10 @@ bootblock-c-ccopts += $(riscv_flags) bootblock-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_bootblock += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_BOOTBLOCK_RISCV ################################################################################ @@ -116,6 +120,10 @@ romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_romstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_ROMSTAGE_RISCV ################################################################################ @@ -161,5 +169,9 @@ ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_ramstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_RAMSTAGE_RISCV endif #CONFIG_ARCH_RISCV diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index d4b8be7..b0796f9 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -16,6 +16,7 @@ */ #include <arch/encoding.h> +#include <bits.h> #include <mcall.h> .section ".text._start", "ax", %progbits @@ -44,7 +45,7 @@ slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h index de7fd19..8030844 100644 --- a/src/arch/riscv/include/arch/smp/atomic.h +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -47,7 +47,7 @@ # define atomic_inc(v) atomic_add(v, 1) # define atomic_dec(v) atomic_add(v, -1) #else -static inline int atomic_add(atomic_t *v, int inc) +static inline int atomic_add(volatile atomic_t *v, int inc) { long flags = disable_irqsave(); int res = v->counter; @@ -56,7 +56,7 @@ return res; } -static inline int atomic_swap(atomic_t *v, int swp) +static inline int atomic_swap(volatile atomic_t *v, int swp) { long flags = disable_irqsave(); int res = v->counter; diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h index f69c7ec..d824f3e 100644 --- a/src/arch/riscv/include/bits.h +++ b/src/arch/riscv/include/bits.h @@ -47,10 +47,19 @@ #define STR(x) XSTR(x) #define XSTR(x) #x -# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LOG_REGBYTES 3 +#if __riscv_xlen == 64 +#define SLL32 sllw +#define STORE sd +#define LOAD ld +#define LWU lwu +#define LOG_REGBYTES 3 +#else +#define SLL32 sll +#define STORE sw +#define LOAD lw +#define LWU lw +#define LOG_REGBYTES 2 +#endif #define REGBYTES (1 << LOG_REGBYTES) diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index cd1ed6d..192d2b4 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -18,7 +18,13 @@ // NOTE: this is the size of hls_t below. A static_assert would be // nice to have. +#if __riscv_xlen == 64 #define HLS_SIZE 88 +#endif + +#if __riscv_xlen == 32 +#define HLS_SIZE 52 +#endif /* We save 37 registers, currently. */ #define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) @@ -26,6 +32,7 @@ #ifndef __ASSEMBLER__ #include <arch/encoding.h> +#include <arch/smp/atomic.h> #include <stdint.h> typedef struct { @@ -38,8 +45,8 @@ struct blocker { void *arg; void (*fn)(void *arg); - uint32_t sync_a; - uint32_t sync_b; + atomic_t sync_a; + atomic_t sync_b; }; typedef struct { diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 115a55f..28183e5 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -14,6 +14,7 @@ */ #include <arch/encoding.h> +#include <bits.h> #include <mcall.h> .section ".text._start", "ax", %progbits @@ -27,7 +28,7 @@ slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 8942ec5..b32e4b8 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -32,13 +32,13 @@ /* waiting for work hart */ do { barrier(); - } while (SYNCA != 0x01234567); + } while (atomic_read(&SYNCA) != 0x01234567); clear_csr(mstatus, MSTATUS_MIE); write_csr(mie, MIP_MSIP); /* count how many cores enter the halt */ - __sync_fetch_and_add(&SYNCB, 1); + atomic_add(&SYNCB, 1); do { barrier(); @@ -49,17 +49,17 @@ } else { /* Initialize the counter and * mark the work hart into smp_pause */ - SYNCB = 0; - SYNCA = 0x01234567; + atomic_set(&SYNCB, 0); + atomic_set(&SYNCA, 0x01234567); /* waiting for other Hart to enter the halt */ do { barrier(); - } while (SYNCB + 1 < CONFIG_MAX_CPUS); + } while (atomic_read(&SYNCB) + 1 < CONFIG_MAX_CPUS); /* initialize for the next call */ - SYNCA = 0; - SYNCB = 0; + atomic_set(&SYNCA, 0); + atomic_set(&SYNCB, 0); } #undef SYNCA #undef SYNCB diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index 99a0749..3e5bef8 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -20,7 +20,7 @@ * <lib.h> in case GCC does not have an assembly version for this arch. */ -#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ +#if !IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_ARCH_RISCV_RV32) /* work around lack of --gc-sections on x86 */ int __clzsi2(u32 a); int __clzsi2(u32 a) { diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index ecaa764..d15c99e 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -16,6 +16,21 @@ # util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf # qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf + +if BOARD_EMULATION_QEMU_RISCV_RV64 + +config BOARD_EMULATION_QEMU_RISCV + def_bool y + select ARCH_RISCV_RV64 +endif + +if BOARD_EMULATION_QEMU_RISCV_RV32 + +config BOARD_EMULATION_QEMU_RISCV + def_bool y + select ARCH_RISCV_RV32 +endif + if BOARD_EMULATION_QEMU_RISCV config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig.name b/src/mainboard/emulation/qemu-riscv/Kconfig.name index e9243e6..61fd919 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig.name +++ b/src/mainboard/emulation/qemu-riscv/Kconfig.name @@ -1,2 +1,5 @@ -config BOARD_EMULATION_QEMU_RISCV - bool "QEMU riscv" +config BOARD_EMULATION_QEMU_RISCV_RV64 + bool "QEMU RISC-V rv64" + +config BOARD_EMULATION_QEMU_RISCV_RV32 + bool "QEMU RISC-V rv32" diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index f8c98ab..03046f72 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ARCH_RISCV_RV64 select SOC_UCB_RISCV select BOARD_ROMSIZE_KB_4096 select DRIVERS_UART_8250MEM diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index aa352d9..ad48c1c 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,5 +1,4 @@ config SOC_UCB_RISCV - select ARCH_RISCV_RV64 select ARCH_RISCV_S select ARCH_RISCV_U select ARCH_RISCV_PMP @@ -15,6 +14,8 @@ if SOC_UCB_RISCV +if ARCH_RISCV_RV64 + config RISCV_ARCH string default "rv64imafd" @@ -27,6 +28,24 @@ string default "medany" +endif + +if ARCH_RISCV_RV32 + +config RISCV_ARCH + string + default "rv32im" + +config RISCV_ABI + string + default "ilp32" + +config RISCV_CODEMODEL + string + default "medany" + +endif + config RISCV_WORKING_HARTID int default 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/31253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Gerrit-Change-Number: 31253 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

4 15

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019