Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31352 )
Change subject: soc/intel/apl: Implement "Power State after Failure"
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/31352/2/src/soc/intel/common/block/fast_spi…
File src/soc/intel/common/block/fast_spi/Makefile.inc:
https://review.coreboot.org/#/c/31352/2/src/soc/intel/common/block/fast_spi…
PS2, Line 17: ifeq ($(CONFIG_SPI_FLASH_SMM),y)
> How is this related?
To access the NVRAM setting from SMM, you need access to CBFS
(`cmos.layout`) which in case of APL needs access to the flash
descriptor to locate it. What made the flaw here obvious:
`fast_spi.c` is only about the SPI controller not the flash
access, but `SPI_FLASH_SMM` is about flash access, thus the
former shouldn't be guarded.
Actually, I don't know what the guard is there for anyway. All
the other stages don't have one and I doubt `fast_spi_flash.c`
is used anywhere but in ramstage.
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Nico Huber has uploaded a new patch set (#3) to the change originally created by Thomas Heijligen. ( https://review.coreboot.org/c/coreboot/+/31352 )
Change subject: soc/intel/apl: Implement "Power State after Failure"
......................................................................
soc/intel/apl: Implement "Power State after Failure"
Add missing functionality around the already selected
HAVE_POWER_STATE_AFTER_FAILURE, that is, configure what
power state to enter after G3.
Beside the Kconfig settings, we allow NVRAM to override
the choice via `power_on_after_fail`.
Change-Id: Ibf218b90088a45349c54f4b881e895bb852e88bb
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/pmc.c
M src/soc/intel/common/block/fast_spi/Makefile.inc
3 files changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31352/3
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31353 )
Change subject: intel/apollolake: Add HDA to disable_dev function
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31353/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31353/2//COMMIT_MSG@8
PS2, Line 8:
> Why?
There warning below the added lines should explain enough, no? "Because it was missing"?
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Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29900 )
Change subject: soc/intel/apl: Disable LPC Clock Run feature after FSP-S
......................................................................
Abandoned
The hook is hard to implement correctly and we can avoid the issue
by being more careful about the pad configuration.
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Change subject: drivers/intel/fsp2_0: Add hook to fix up FSP-S
......................................................................
Abandoned
Not worth the hassle. Also, would make it harder to distinguish the work
within the blob from that in coreboot (i.e. raises license questions
again). The original problem fixed with this hook can be avoided in
different ways.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 )
Change subject: util/inteltool: Add Apollo Lake GPIO groups and names
......................................................................
Patch Set 5: Code-Review+1
+2 to Felix' changes
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31353 )
Change subject: intel/apollolake: Add HDA to disable_dev function
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31353/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31353/2//COMMIT_MSG@8
PS2, Line 8:
Why?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31352 )
Change subject: soc/intel/apl: Implement "Power State after Failure"
......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/31352/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31352/2//COMMIT_MSG@8
PS2, Line 8:
Could you elaborate please?
https://review.coreboot.org/#/c/31352/2/src/soc/intel/common/block/fast_spi…
File src/soc/intel/common/block/fast_spi/Makefile.inc:
https://review.coreboot.org/#/c/31352/2/src/soc/intel/common/block/fast_spi…
PS2, Line 17: ifeq ($(CONFIG_SPI_FLASH_SMM),y)
How is this related?
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