coreboot-gerrit February 2019

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Change in ...coreboot[master]: google/kahlee: No need to guard with HAVE_ACPI_RESUME
by Kyösti Mälkki (Code Review) 12 Feb '19

12 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31317 Change subject: google/kahlee: No need to guard with HAVE_ACPI_RESUME ...................................................................... google/kahlee: No need to guard with HAVE_ACPI_RESUME Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 3 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31317/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ebdcc93..ed48593 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -195,12 +195,10 @@ return variant_get_ehci_oc_map(map); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) void mainboard_suspend_resume(void) { variant_mainboard_suspend_resume(); } -#endif struct chip_operations mainboard_ops = { .init = mainboard_init, @@ -214,11 +212,9 @@ return 0; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) void __weak variant_mainboard_suspend_resume(void) { } -#endif const char *smbios_mainboard_sku(void) { diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index da65bd8..e3cde3e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -31,8 +31,6 @@ const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size); const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) void variant_mainboard_suspend_resume(void); -#endif #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index d1a3492..71aca73 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -32,13 +32,11 @@ return sku; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) void variant_mainboard_suspend_resume(void) { /* Enable backlight - GPIO 133 active low */ gpio_set(GPIO_133, 0); } -#endif void board_bh720(struct device *dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8 Gerrit-Change-Number: 31317 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by build bot (Jenkins) (Code Review) 12 Feb '19

12 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 4: (28 comments) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@108 PS4, Line 108: "*GPIO_72", "GP_CAMERASB10","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@109 PS4, Line 109: "*GPIO_73", "GP_CAMERASB11","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@116 PS4, Line 116: "JTAGX" , "*JTAGX", "n/a", "n/a", "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@123 PS4, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@123 PS4, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@167 PS4, Line 167: "PMC_SPI_FS2", "*PMC_SPI_FS2", "FST_SPI_CS2_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@181 PS4, Line 181: "*GPIO_74", "AVS_I2S1_MCLK" , "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@186 PS4, Line 186: "*GPIO_79", "AVS_DMIC_CLK_A1", "AVS_I2S4_BCLK","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@187 PS4, Line 187: "*GPIO_80", "AVS_DMIC_CLK_B1", "AVS_I2S4_WS_SYNC","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@191 PS4, Line 191: "*GPIO_84", "AVS_I2S2_MCLK", "AVS_HDA_RST_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@319 PS4, Line 319: "*GPIO_134", "LPSS_I2C5_SDA","ISH_I2C0_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@320 PS4, Line 320: "*GPIO_135", "LPSS_I2C5_SCL","ISH_I2C0_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@321 PS4, Line 321: "*GPIO_136", "LPSS_I2C6_SDA","ISH_I2C1_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@322 PS4, Line 322: "*GPIO_137", "LPSS_I2C6_SCL","ISH_I2C1_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@323 PS4, Line 323: "*GPIO_138", "LPSS_I2C7_SDA","ISH_I2C2_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@324 PS4, Line 324: "*GPIO_139", "LPSS_I2C7_SCL","ISH_I2C2_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@326 PS4, Line 326: "*GPIO_147", "ISH_GPIO_1", "AVS_I2S6_WS_SYNC", "AVS_HDA_WS_SYNC", line over 80 characters https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@329 PS4, Line 329: "*GPIO_150", "ISH_GPIO_4", "AVS_I2S5_BCLK", "LPSS_UART2_RXD", line over 80 characters https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@330 PS4, Line 330: "*GPIO_151", "ISH_GPIO_5", "AVS_I2S5_WS_SYNC", "LPSS_UART2_TXD", line over 80 characters https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@331 PS4, Line 331: "*GPIO_152", "ISH_GPIO_6", "AVS_I2S5_SDI", "LPSS_UART2_RTS_B", line over 80 characters https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@332 PS4, Line 332: "*GPIO_153", "ISH_GPIO_7", "AVS_I2S5_SDO", "LPSS_UART2_CTS_B", line over 80 characters https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@339 PS4, Line 339: "OSC_CLK_OUT_0","*OSC_CLK_OUT_0", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@340 PS4, Line 340: "OSC_CLK_OUT_1","*OSC_CLK_OUT_1", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@341 PS4, Line 341: "OSC_CLK_OUT_2","*OSC_CLK_OUT_2", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@342 PS4, Line 342: "OSC_CLK_OUT_3","*OSC_CLK_OUT_3", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@343 PS4, Line 343: "OSC_CLK_OUT_4","*OSC_CLK_OUT_4", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@344 PS4, Line 344: "*PMU_AC_PRESENT","PMU_AC_PRESENT", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/4/util/inteltool/gpio_groups.c@353 PS4, Line 353: "*PMU_WAKE_B", "PMU_WAKE_B/EMMC_PWR_EN_N","n/a", "n/a", space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 12 Feb 2019 00:01:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 12 Feb '19

12 Feb '19

Felix Singer has uploaded a new patch set (#4) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c 2 files changed, 353 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29897/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/intel/bdw: Remove spurious comment
by Nico Huber (Code Review) 11 Feb '19

11 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31321 Change subject: soc/intel/bdw: Remove spurious comment ...................................................................... soc/intel/bdw: Remove spurious comment Change-Id: I45f2ca809a6acfcb80a742d29c045d04888e4d7f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/broadwell/bootblock/cpu.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31321/1 diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 2d56f32..6e677d1 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -41,7 +41,6 @@ msr_t msr; disable_cache(); - /* Why only top 4MiB ? */ set_var_mtrr(1, CACHE_ROM_BASE_C, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45f2ca809a6acfcb80a742d29c045d04888e4d7f Gerrit-Change-Number: 31321 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: riscv: realign our naming with the true names
by ron minnich (Code Review) 11 Feb '19

11 Feb '19

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31079 Change subject: riscv: realign our naming with the true names ...................................................................... riscv: realign our naming with the true names The riscv world has decided that riscv means rv32 riscv64 means rv64 and that, further, nobody is going to use names like rv32 or rv64! Poor choices IMHO but seems it's too late to change. This is the first step on aligning coreboot naming to the outside world. Partly this is needed for a 32-bit RISCV processor coming to you soon, but largely it's good to be aligned with everyone else's naming. A primary goal here is that src/arch/riscv continues to mean "all riscv regardless of word size" even though it arguably is not following the naming. But the 32- and 64-bit isa's are essentially the same save for XLEN, so this ought to work. Choosing 32- or 64-bit is done in mainboards, hence the name change for the emulation targets. With luck, we might someday be able to say "build the emulation target and pick the 32-bit variant" but our naming does not quite allow that yet. In future commits we'll probably want to move src/soc/ucb/riscv to src/soc/ucb/riscv64 but it's nice to minimize breakage. Change-Id: If842767a4b6c5e82df99b5a57b524b88044afcba Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M MAINTAINERS R src/mainboard/emulation/qemu-riscv64/Kconfig R src/mainboard/emulation/qemu-riscv64/Kconfig.name R src/mainboard/emulation/qemu-riscv64/Makefile.inc R src/mainboard/emulation/qemu-riscv64/board_info.txt R src/mainboard/emulation/qemu-riscv64/devicetree.cb R src/mainboard/emulation/qemu-riscv64/mainboard.c R src/mainboard/emulation/qemu-riscv64/memlayout.ld R src/mainboard/emulation/qemu-riscv64/mtime.c R src/mainboard/emulation/qemu-riscv64/rom_media.c R src/mainboard/emulation/qemu-riscv64/romstage.c R src/mainboard/emulation/qemu-riscv64/uart.c D src/mainboard/emulation/spike-riscv/Kconfig.name R src/mainboard/emulation/spike-riscv64/Kconfig A src/mainboard/emulation/spike-riscv64/Kconfig.name R src/mainboard/emulation/spike-riscv64/Makefile.inc R src/mainboard/emulation/spike-riscv64/board_info.txt R src/mainboard/emulation/spike-riscv64/clint.c R src/mainboard/emulation/spike-riscv64/devicetree.cb R src/mainboard/emulation/spike-riscv64/mainboard.c R src/mainboard/emulation/spike-riscv64/memlayout.ld R src/mainboard/emulation/spike-riscv64/rom_media.c R src/mainboard/emulation/spike-riscv64/romstage.c R src/mainboard/emulation/spike-riscv64/uart.c 24 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31079/1 diff --git a/MAINTAINERS b/MAINTAINERS index fbaad69..8131178 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,7 +141,7 @@ F: src/arch/riscv/ F: src/soc/sifive/ F: src/soc/ucb/ -F: src/mainboard/emulation/*-riscv/ +F: src/mainboard/emulation/*-riscv*/ F: src/mainboard/sifive/ F: util/riscv/ diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv64/Kconfig similarity index 91% rename from src/mainboard/emulation/qemu-riscv/Kconfig rename to src/mainboard/emulation/qemu-riscv64/Kconfig index 528b21e..62b8e3a 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv64/Kconfig @@ -27,11 +27,11 @@ config MAINBOARD_DIR string - default emulation/qemu-riscv + default emulation/qemu-riscv64 config MAINBOARD_PART_NUMBER string - default "QEMU RISCV" + default "QEMU RISCV64" config MAX_CPUS int @@ -41,4 +41,4 @@ int default 32768 -endif # BOARD_EMULATION_QEMU_RISCV +endif # BOARD_EMULATION_QEMU_RISCV64 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig.name b/src/mainboard/emulation/qemu-riscv64/Kconfig.name similarity index 61% rename from src/mainboard/emulation/qemu-riscv/Kconfig.name rename to src/mainboard/emulation/qemu-riscv64/Kconfig.name index e9243e6..54454cb 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig.name +++ b/src/mainboard/emulation/qemu-riscv64/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_EMULATION_QEMU_RISCV - bool "QEMU riscv" + bool "QEMU riscv64" diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv64/Makefile.inc similarity index 100% rename from src/mainboard/emulation/qemu-riscv/Makefile.inc rename to src/mainboard/emulation/qemu-riscv64/Makefile.inc diff --git a/src/mainboard/emulation/qemu-riscv/board_info.txt b/src/mainboard/emulation/qemu-riscv64/board_info.txt similarity index 100% rename from src/mainboard/emulation/qemu-riscv/board_info.txt rename to src/mainboard/emulation/qemu-riscv64/board_info.txt diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv64/devicetree.cb similarity index 100% rename from src/mainboard/emulation/qemu-riscv/devicetree.cb rename to src/mainboard/emulation/qemu-riscv64/devicetree.cb diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv64/mainboard.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/mainboard.c rename to src/mainboard/emulation/qemu-riscv64/mainboard.c diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv64/memlayout.ld similarity index 100% rename from src/mainboard/emulation/qemu-riscv/memlayout.ld rename to src/mainboard/emulation/qemu-riscv64/memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv64/mtime.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/mtime.c rename to src/mainboard/emulation/qemu-riscv64/mtime.c diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv64/rom_media.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/rom_media.c rename to src/mainboard/emulation/qemu-riscv64/rom_media.c diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv64/romstage.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/romstage.c rename to src/mainboard/emulation/qemu-riscv64/romstage.c diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv64/uart.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/uart.c rename to src/mainboard/emulation/qemu-riscv64/uart.c diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name deleted file mode 100644 index 17549c6..0000000 --- a/src/mainboard/emulation/spike-riscv/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -config BOARD_EMULATION_SPIKE_RISCV - bool "SPIKE riscv" - help diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv64/Kconfig similarity index 86% rename from src/mainboard/emulation/spike-riscv/Kconfig rename to src/mainboard/emulation/spike-riscv64/Kconfig index f8c98ab..c09b621 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv64/Kconfig @@ -12,7 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -if BOARD_EMULATION_SPIKE_RISCV +if BOARD_EMULATION_SPIKE_RISCV64 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,14 +24,14 @@ config MAINBOARD_DIR string - default emulation/spike-riscv + default emulation/spike-riscv64 config MAINBOARD_PART_NUMBER string - default "SPIKE RISCV" + default "SPIKE RISCV64" config MAX_CPUS int default 1 -endif # BOARD_EMULATION_SPIKE_RISCV +endif # BOARD_EMULATION_SPIKE_RISCV64 diff --git a/src/mainboard/emulation/spike-riscv64/Kconfig.name b/src/mainboard/emulation/spike-riscv64/Kconfig.name new file mode 100644 index 0000000..b743bd5 --- /dev/null +++ b/src/mainboard/emulation/spike-riscv64/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_EMULATION_SPIKE_RISCV64 + bool "SPIKE riscv64" + help diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv64/Makefile.inc similarity index 100% rename from src/mainboard/emulation/spike-riscv/Makefile.inc rename to src/mainboard/emulation/spike-riscv64/Makefile.inc diff --git a/src/mainboard/emulation/spike-riscv/board_info.txt b/src/mainboard/emulation/spike-riscv64/board_info.txt similarity index 100% rename from src/mainboard/emulation/spike-riscv/board_info.txt rename to src/mainboard/emulation/spike-riscv64/board_info.txt diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv64/clint.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/clint.c rename to src/mainboard/emulation/spike-riscv64/clint.c diff --git a/src/mainboard/emulation/spike-riscv/devicetree.cb b/src/mainboard/emulation/spike-riscv64/devicetree.cb similarity index 100% rename from src/mainboard/emulation/spike-riscv/devicetree.cb rename to src/mainboard/emulation/spike-riscv64/devicetree.cb diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv64/mainboard.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/mainboard.c rename to src/mainboard/emulation/spike-riscv64/mainboard.c diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv64/memlayout.ld similarity index 100% rename from src/mainboard/emulation/spike-riscv/memlayout.ld rename to src/mainboard/emulation/spike-riscv64/memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv64/rom_media.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/rom_media.c rename to src/mainboard/emulation/spike-riscv64/rom_media.c diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv64/romstage.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/romstage.c rename to src/mainboard/emulation/spike-riscv64/romstage.c diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv64/uart.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/uart.c rename to src/mainboard/emulation/spike-riscv64/uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If842767a4b6c5e82df99b5a57b524b88044afcba Gerrit-Change-Number: 31079 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: libpayload: add memchr to libc
by Philipp Hug (Code Review) 11 Feb '19

11 Feb '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31354 Change subject: libpayload: add memchr to libc ...................................................................... libpayload: add memchr to libc libfdt requires memchr. Add missing function to libc. Change-Id: I872026559d16a352f350147c9d7c4be97456a99f Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M payloads/libpayload/include/string.h M payloads/libpayload/libc/memory.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31354/1 diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index ca5d513..4aff0e8 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -39,6 +39,7 @@ void *memset(void *s, int c, size_t n); void *memcpy(void *dst, const void *src, size_t n); void *memmove(void *dst, const void *src, size_t n); +void *memchr(const void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t len); /** @} */ diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c index 25c2b3a..8ee3eed 100644 --- a/payloads/libpayload/libc/memory.c +++ b/payloads/libpayload/libc/memory.c @@ -145,3 +145,15 @@ int memcmp(const void *s1, const void *s2, size_t n) __attribute__((weak, alias("default_memcmp"))); + + +void *memchr(const void *s, int c, size_t n) +{ + unsigned char *p = (unsigned char *)s; + while (n--) + if (*p != (unsigned char)c) + p++; + else + return p; + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I872026559d16a352f350147c9d7c4be97456a99f Gerrit-Change-Number: 31354 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/amd/common: Remove redundant ACPI S3 test
by Marshall Dawson (Code Review) 11 Feb '19

11 Feb '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27276 ) Change subject: soc/amd/common: Remove redundant ACPI S3 test ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27276/4/src/soc/amd/stoneyridge/Kconfig File src/soc/amd/stoneyridge/Kconfig: https://review.coreboot.org/#/c/27276/4/src/soc/amd/stoneyridge/Kconfig@a53 PS4, Line 53: > Also, I plan to reuse that s3_resume.c with improved stage_cache and mrc_cache code with agesa/family16 that definetly can do fastboot... The stage_cache/mrc_cache is definitely a plus. ST and I assume CZ(MF) can't do an S5 fastboot because there's now the PMU handling that DRAM training. It doesn't know how to reuse info from a prior boot. I believe Family 15h Mod 60h was where that first showed up; I don't believe Kavari, but definitely no F16h I've ever heard of. -- To view, visit https://review.coreboot.org/c/coreboot/+/27276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Gerrit-Change-Number: 27276 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Feb 2019 22:52:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Kyösti Mälkki (Code Review) 11 Feb '19

11 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27277 ) Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/27277/4/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/27277/4/src/soc/amd/common/block/pi/agesawr… PS4, Line 374: When we reach here, we have either Func==AGESA_RUNFUNC_ONAP or Func==AGESA_RUNFUNC_ON_ALL_APS Looking into implementation of AmdLateRunApTask() it's expected FunctionNumber equals one of the entries in ApDispatchTable. In CarrizoPi, cpuF15CzBtcBefore() and RUN_BTC_ON_ALL_APS is sort of example what happens. https://review.coreboot.org/#/c/27277/4/src/soc/amd/common/block/pi/agesawr… PS4, Line 370: : : : : : : > Have you verified that AGESA actually fills these parameters of ApExeParams? Seems to, I was mostly staring at that FunctionNumber field. -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Feb 2019 22:28:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Richard Spiegel (Code Review) 11 Feb '19

11 Feb '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27277 ) Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27277/4/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/27277/4/src/soc/amd/common/block/pi/agesawr… PS4, Line 370: : : : : : : Have you verified that AGESA actually fills these parameters of ApExeParams? -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Feb 2019 22:06:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Marshall Dawson (Code Review) 11 Feb '19

11 Feb '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27277 ) Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... Patch Set 4: I'm not convinced yet that this is correct, although I agree with your premise. The PI blob is built so that all callouts run through a function named AmdAgesaCallout(). This, in turn, calls a pointer with arguments Func, Data, ConfigPtr). As a result, I believe the PI version of agesawrapper.c is written correctly to unwrap the information. Unfortunately, I don't observe the function being run in agesawrapper.c, so it's not obvious whether there's a bug. The stoney PI source doesn't call AmdLateRunApTask() -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Feb 2019 21:50:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019