coreboot-gerrit February 2019

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Change in ...coreboot[master]: soc/intel/icelake: Don't use CAR_GLOBAL
by Aaron Durbin (Code Review) 11 Feb '19

11 Feb '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30515 ) Change subject: soc/intel/icelake: Don't use CAR_GLOBAL ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Gerrit-Change-Number: 30515 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Feb 2019 14:42:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/socket_mPGA604: Fix for TSC_CONSTANT_RATE
by Paul Menzel (Code Review) 11 Feb '19

11 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31343 ) Change subject: cpu/intel/socket_mPGA604: Fix for TSC_CONSTANT_RATE ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/31343/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31343/1//COMMIT_MSG@7 PS1, Line 7: Fix for TSC_CONSTANT_RATE Statement: Fix TSC_CONSTANT_RATE -- To view, visit https://review.coreboot.org/c/coreboot/+/31343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02b93cefc9a8e18ad55c944fa7119b04fbbacd66 Gerrit-Change-Number: 31343 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Feb 2019 13:34:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/common: Remove redundant ACPI S3 test
by Paul Menzel (Code Review) 11 Feb '19

11 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27276 ) Change subject: soc/amd/common: Remove redundant ACPI S3 test ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/27276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Gerrit-Change-Number: 27276 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Feb 2019 13:29:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/galileo: Drop the FSP1.1 option
by Arthur Heymans (Code Review) 11 Feb '19

11 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30946 Change subject: mb/intel/galileo: Drop the FSP1.1 option ...................................................................... mb/intel/galileo: Drop the FSP1.1 option This board is EOL and has FSP2.0 support, so drop the older version. Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/galileo/Makefile.inc M src/mainboard/intel/galileo/romstage.c M src/soc/intel/quark/Kconfig M src/soc/intel/quark/Makefile.inc D src/soc/intel/quark/fsp1_1.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/include/soc/romstage.h M src/soc/intel/quark/romstage/Makefile.inc D src/soc/intel/quark/romstage/fsp1_1.c D src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h 12 files changed, 11 insertions(+), 671 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30946/1 diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 0af03e5..0f49c7f 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -23,6 +23,10 @@ select SOC_INTEL_QUARK select MAINBOARD_HAS_I2C_TPM_ATMEL select MAINBOARD_HAS_TPM2 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_STAGE + config MAINBOARD_DIR string @@ -46,31 +50,6 @@ should initialize. choice - prompt "FSP version" - default FSP_VERSION_2_0 - -config FSP_VERSION_1_1 - bool "FSP 1.1" - select PLATFORM_USES_FSP1_1 -# select ADD_FSP_RAW_BIN - help - Use FSP 1_1 binary -config FSP_VERSION_2_0 - bool "FSP 2.0" - select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING - select POSTCAR_STAGE - help - Use FSP 2.0 binary - -endchoice - -config FSP_VERSION - string - default "fsp1_1" if FSP_VERSION_1_1 - default "fsp2_0" if FSP_VERSION_2_0 - -choice prompt "FSP binary type" default FSP_BUILD_TYPE_DEBUG @@ -92,28 +71,14 @@ choice prompt "FSP type" - depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 - default FSP_TYPE_1_1_PEI if FSP_VERSION_1_1 - default FSP_TYPE_2_0_PEI if FSP_VERSION_2_0 + default FSP_TYPE_2_0_PEI -config FSP_TYPE_1_1 - bool "MemInit subroutine" - depends on FSP_VERSION_1_1 - help - FSP 1.1 implemented as subroutines, no EDK-II cores -config FSP_TYPE_1_1_PEI - bool "SEC + PEI Core + MemInit PEIM" - depends on FSP_VERSION_1_1 - help - FSP 1.1 implemented using SEC and PEI core config FSP_TYPE_2_0 bool "MemInit subroutine" - depends on FSP_VERSION_2_0 help FSP 2.0 implemented as subroutines, no EDK-II cores config FSP_TYPE_2_0_PEI bool "SEC + PEI Core + MemInit PEIM" - depends on FSP_VERSION_2_0 help FSP 2.0 implemented using SEC and PEI core @@ -121,26 +86,22 @@ config FSP_TYPE string - default "Fsp1_1" if FSP_TYPE_1_1 - default "Fsp1_1Pei" if FSP_TYPE_1_1_PEI default "Fsp2_0" if FSP_TYPE_2_0 default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI config FSP_DEBUG_ALL bool "Enable all FSP debug support" - depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 default y # Enable display and verification for coreboot build tests select DISPLAY_HOBS select DISPLAY_MTRRS select DISPLAY_SMM_MEMORY_MAP select DISPLAY_UPD_DATA - select DISPLAY_ESRAM_LAYOUT if FSP_VERSION_2_0 - select DISPLAY_FSP_CALLS_AND_STATUS if FSP_VERSION_2_0 - select DISPLAY_FSP_HEADER if FSP_VERSION_2_0 - select POSTCAR_CONSOLE if FSP_VERSION_2_0 - select VERIFY_HOBS if FSP_VERSION_2_0 - select DISPLAY_FSP_ENTRY_POINTS if FSP_VERSION_1_1 + select DISPLAY_ESRAM_LAYOUT + select DISPLAY_FSP_CALLS_AND_STATUS + select DISPLAY_FSP_HEADER + select POSTCAR_CONSOLE + select VERIFY_HOBS help Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA also turn on FSP 2.0 debug support for ESRAM_LAYOUT, diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 60c0ee0..3c6c7bd 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -13,10 +13,6 @@ ## GNU General Public License for more details. ## -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0)$(CONFIG_PLATFORM_USES_FSP1_1),y) -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/$(CONFIG_FSP_VERSION)/quark -endif - bootblock-y += gpio.c bootblock-y += reg_access.c diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c index baf9af3..7e06c94 100644 --- a/src/mainboard/intel/galileo/romstage.c +++ b/src/mainboard/intel/galileo/romstage.c @@ -1,26 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -#include <fsp/romstage.h> - -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} -#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ +/* Dummy */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index beed8cd..2a0c132 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -107,17 +107,6 @@ Indicate that ESRAM has been successfully initialized. If the SD LED does not light then the ESRAM initialization needs to be debugged. -config ENABLE_DEBUG_LED_FINDFSP - bool "SD LED indicates fsp.bin file was found" - depends on PLATFORM_USES_FSP1_1 - default n - select ENABLE_DEBUG_LED - help - Indicate that fsp.bin was found. If the SD LED does not light then - the code between ESRAM initialization through find_fsp needs to - debugged. Start by verifying that the correct fsp.bin is in the - image. - config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY bool "SD LED indicates bootblock.c successfully entered" default n @@ -160,12 +149,10 @@ config DCACHE_RAM_BASE hex - default 0x80070000 if PLATFORM_USES_FSP1_1 default 0x80000000 config DCACHE_RAM_SIZE hex - default 0x8000 if PLATFORM_USES_FSP1_1 default 0x40000 config DISPLAY_ESRAM_LAYOUT @@ -197,48 +184,12 @@ # SoC code to boot coreboot and its payload. ##### -config ADD_FSP_RAW_BIN - bool "Add the Intel FSP binary to the flash image without relocation" - default n - depends on PLATFORM_USES_FSP1_1 - help - Select this option to add an Intel FSP binary to - the resulting coreboot image. - - Note: Without this binary, coreboot builds relying on the FSP - will not boot - -config FSP_FILE - string "Intel FSP binary path and filename" - default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP.fd" - depends on PLATFORM_USES_FSP1_1 - depends on ADD_FSP_RAW_BIN - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex - default 0xfff80000 - depends on PLATFORM_USES_FSP1_1 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - config FSP_ESRAM_LOC hex - default 0x80000000 if PLATFORM_USES_FSP1_1 default 0x80040000 help The location in ESRAM where a copy of the FSP binary is placed. -config RELOCATE_FSP_INTO_DRAM - bool "Relocate FSP into DRAM" - default n - depends on PLATFORM_USES_FSP1_1 - help - Relocate the FSP binary into DRAM before the call to SiliconInit. - config FSP_M_FILE string depends on PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 654f0a7..f1382f5 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -49,7 +49,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c -ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c deleted file mode 100644 index 41dbb6c..0000000 --- a/src/soc/intel/quark/fsp1_1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <fsp/util.h> -#include <soc/ramstage.h> - -void fsp_silicon_init(bool s3wake) -{ - if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) - intel_silicon_init(); - else - fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake); -} - -void soc_silicon_init_params(SILICON_INIT_UPD *upd) -{ -} - -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new) -{ -} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index c682a24..a3fb02f 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -25,10 +25,6 @@ } __packed; struct chipset_power_state *get_power_state(void); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -struct chipset_power_state *fill_power_state(void); -#else int fill_power_state(void); -#endif #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 821f43e..da2eb61 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -20,15 +20,9 @@ #include <arch/cpu.h> #include <chip.h> #include <device/device.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -#include <fsp/ramstage.h> -#endif #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(struct device *dev); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -void fsp_silicon_init(bool s3wake); -#endif asmlinkage void chipset_teardown_car(void); #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 43d420e..fb8a844 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,11 +22,7 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -#include <fsp/romstage.h> -#else #include <soc/car.h> -#endif #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 3a33f43..742a4fa 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -19,7 +19,6 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c endif # CONFIG_PLATFORM_USES_FSP2_0 -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c deleted file mode 100644 index 88f7376..0000000 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/early_variables.h> -#include <console/console.h> -#include "../chip.h" -#include <fsp/memmap.h> -#include <fsp/util.h> -#include <soc/pci_devs.h> -#include <soc/QuarkNcSocId.h> -#include <soc/romstage.h> -#include <string.h> - -extern void asmlinkage light_sd_led(void); - -asmlinkage void *car_stage_c_entry(void) -{ - FSP_INFO_HEADER *fih; - struct cache_as_ram_params car_params = {0}; - void *top_of_stack; - - post_code(0x20); - - /* Copy the FSP binary into ESRAM */ - memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, - 0x00040000); - - /* Locate the FSP header in ESRAM */ - fih = find_fsp(CONFIG_FSP_ESRAM_LOC); - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)) - light_sd_led(); - - /* Start the early verstage/romstage code */ - post_code(0x2A); - car_params.fih = fih; - top_of_stack = cache_as_ram_main(&car_params); - - /* Initialize MTRRs and switch stacks after RAM initialized */ - return top_of_stack; -} - -static struct chipset_power_state power_state CAR_GLOBAL; - -struct chipset_power_state *get_power_state(void) -{ - return (struct chipset_power_state *)car_get_var_ptr(&power_state); -} - -struct chipset_power_state *fill_power_state(void) -{ - struct chipset_power_state *ps = get_power_state(); - - ps->prev_sleep_state = 0; - printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; -} - -size_t mmap_region_granularity(void) -{ - /* Align to 8 MiB by default */ - return 8 << 20; -} - -/* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) -{ - const struct device *dev; - const struct soc_intel_quark_config *config; - void *rmu_data; - size_t rmu_data_len; - - /* Locate the configuration data from devicetree.cb */ - dev = pcidev_path_on_root(LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_CRIT, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Clear SMI and wake events */ - clear_smi_and_wake_events(); - - /* Locate the RMU data file in flash */ - rmu_data = locate_rmu_file(&rmu_data_len); - if (!rmu_data) - die("Microcode file (rmu.bin) not found."); - - /* Display the ESRAM layout */ - if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { - printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); - printk(BIOS_SPEW, - "+-------------------+ 0x80080000 - ESRAM end\n"); - if (_car_relocatable_data_end != (void *)0x80080000) { - printk(BIOS_SPEW, "| |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_relocatable_data_end); - } - printk(BIOS_SPEW, "| coreboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_stack_end); - printk(BIOS_SPEW, "| coreboot stack |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p", - _car_stack_start); - if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { - printk(BIOS_SPEW, "\n"); - printk(BIOS_SPEW, "| vboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%08x", - CONFIG_DCACHE_RAM_BASE); - } - printk(BIOS_SPEW, " (CONFIG_DCACHE_RAM_BASE)\n"); - - printk(BIOS_SPEW, "| FSP data |\n"); - printk(BIOS_SPEW, "+-------------------+\n"); - printk(BIOS_SPEW, "| FSP stack |\n"); - printk(BIOS_SPEW, "+-------------------+\n"); - printk(BIOS_SPEW, "| FSP binary |\n"); - printk(BIOS_SPEW, - "+-------------------+ 0x80000000 - ESRAM start\n\n"); - } - - /* Update the UPD data for MemoryInit */ - upd->AddrMode = config->AddrMode; - upd->ChanMask = config->ChanMask; - upd->ChanWidth = config->ChanWidth; - upd->DramDensity = config->DramDensity; - upd->DramRonVal = config->DramRonVal; - upd->DramRttNomVal = config->DramRttNomVal; - upd->DramRttWrVal = config->DramRttWrVal; - upd->DramSpeed = config->DramSpeed; - upd->DramType = config->DramType; - upd->DramWidth = config->DramWidth; - upd->EccScrubBlkSize = config->EccScrubBlkSize; - upd->EccScrubInterval = config->EccScrubInterval; - upd->Flags = config->Flags; - upd->FspReservedMemoryLength = config->FspReservedMemoryLength; - upd->RankMask = config->RankMask; - upd->RmuBaseAddress = (uintptr_t)rmu_data; - upd->RmuLength = rmu_data_len; - upd->SerialPortWriteChar = console_log_level(BIOS_SPEW) - ? (uintptr_t)fsp_write_line : 0; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->SmmTsegSize : 0; - upd->SocRdOdtVal = config->SocRdOdtVal; - upd->SocWrRonVal = config->SocWrRonVal; - upd->SocWrSlewRate = config->SocWrSlewRate; - upd->SrInt = config->SrInt; - upd->SrTemp = config->SrTemp; - upd->tCL = config->tCL; - upd->tFAW = config->tFAW; - upd->tRAS = config->tRAS; - upd->tRRD = config->tRRD; - upd->tWTR = config->tWTR; -} - -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) -{ - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); - fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), - old->AddrMode, new->AddrMode); - fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), - old->ChanMask, new->ChanMask); - fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), - old->ChanWidth, new->ChanWidth); - fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), - old->DramDensity, new->DramDensity); - fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), - old->DramRonVal, new->DramRonVal); - fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), - old->DramRttNomVal, new->DramRttNomVal); - fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), - old->DramRttWrVal, new->DramRttWrVal); - fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), - old->DramSpeed, new->DramSpeed); - fsp_display_upd_value("DramType", sizeof(old->DramType), - old->DramType, new->DramType); - fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), - old->DramWidth, new->DramWidth); - fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), - old->EccScrubBlkSize, new->EccScrubBlkSize); - fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), - old->EccScrubInterval, new->EccScrubInterval); - fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, - new->Flags); - fsp_display_upd_value("FspReservedMemoryLength", - sizeof(old->FspReservedMemoryLength), - old->FspReservedMemoryLength, new->FspReservedMemoryLength); - fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, - new->RankMask); - fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), - old->RmuBaseAddress, new->RmuBaseAddress); - fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), - old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortPollForChar", - sizeof(old->SerialPortPollForChar), - old->SerialPortPollForChar, new->SerialPortPollForChar); - fsp_display_upd_value("SerialPortReadChar", - sizeof(old->SerialPortReadChar), - old->SerialPortReadChar, new->SerialPortReadChar); - fsp_display_upd_value("SerialPortWriteChar", - sizeof(old->SerialPortWriteChar), - old->SerialPortWriteChar, new->SerialPortWriteChar); - fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), - old->SmmTsegSize, new->SmmTsegSize); - fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), - old->SocRdOdtVal, new->SocRdOdtVal); - fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), - old->SocWrRonVal, new->SocWrRonVal); - fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), - old->SocWrSlewRate, new->SocWrSlewRate); - fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, - new->SrInt); - fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, - new->SrTemp); - fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); - fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); - fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); - fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); - fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); -} - -void soc_after_ram_init(struct romstage_params *params) -{ - /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ - disable_rom_shadow(); - - /* Initialize the PCIe bridges */ - pcie_init(); -} diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h deleted file mode 100644 index 743e4ee..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ /dev/null @@ -1,245 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPDVPD_H__ -#define __FSPUPDVPD_H__ - -#pragma pack(1) - - -#define MAX_CHANNELS_NUM 1 -#define MAX_DIMMS_NUM 1 - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DDR3 is 18 bytes however for - DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - - -typedef struct { -/** Offset 0x0018 -**/ - UINT64 Signature; -/** Offset 0x0020 -**/ - UINT64 Revision; -/** Offset 0x0028 -**/ - UINT32 RmuBaseAddress; -/** Offset 0x002C -**/ - UINT32 RmuLength; -/** Offset 0x0030 -**/ - UINT32 Reserved_30; -/** Offset 0x0034 -**/ - UINT32 tRAS; -/** Offset 0x0038 -**/ - UINT32 tWTR; -/** Offset 0x003C -**/ - UINT32 tRRD; -/** Offset 0x0040 -**/ - UINT32 tFAW; -/** Offset 0x0044 -**/ - UINT32 Flags; -/** Offset 0x0048 -**/ - UINT8 DramWidth; -/** Offset 0x0049 -**/ - UINT8 DramSpeed; -/** Offset 0x004A -**/ - UINT8 DramType; -/** Offset 0x004B -**/ - UINT8 RankMask; -/** Offset 0x004C -**/ - UINT8 ChanMask; -/** Offset 0x004D -**/ - UINT8 ChanWidth; -/** Offset 0x004E -**/ - UINT8 AddrMode; -/** Offset 0x004F -**/ - UINT8 SrInt; -/** Offset 0x0050 -**/ - UINT8 SrTemp; -/** Offset 0x0051 -**/ - UINT8 DramRonVal; -/** Offset 0x0052 -**/ - UINT8 DramRttNomVal; -/** Offset 0x0053 -**/ - UINT8 DramRttWrVal; -/** Offset 0x0054 -**/ - UINT8 SocRdOdtVal; -/** Offset 0x0055 -**/ - UINT8 SocWrRonVal; -/** Offset 0x0056 -**/ - UINT8 SocWrSlewRate; -/** Offset 0x0057 -**/ - UINT8 DramDensity; -/** Offset 0x0058 -**/ - UINT8 tCL; -/** Offset 0x0059 -**/ - UINT8 EccScrubInterval; -/** Offset 0x005A -**/ - UINT8 EccScrubBlkSize; -/** Offset 0x005B -**/ - UINT8 SmmTsegSize; -/** Offset 0x005C -**/ - UINT32 FspReservedMemoryLength; -/** Offset 0x0060 -**/ - UINT32 MrcDataPtr; -/** Offset 0x0064 -**/ - UINT32 MrcDataLength; -/** Offset 0x0068 -**/ - UINT32 SerialPortPollForChar; -/** Offset 0x006C -**/ - UINT32 SerialPortReadChar; -/** Offset 0x0070 -**/ - UINT32 SerialPortWriteChar; -/** Offset 0x0074 -**/ - UINT8 ReservedMemoryInitUpd[12]; -} MEMORY_INIT_UPD; - -typedef struct { -/** Offset 0x0080 -**/ - UINT64 Signature; -/** Offset 0x0088 -**/ - UINT64 Revision; -/** Offset 0x0090 -**/ - UINT16 PcdRegionTerminator; -} SILICON_INIT_UPD; - -#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -typedef struct _UPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 Signature; -/** Offset 0x0008 -**/ - UINT64 Revision; -/** Offset 0x0010 -**/ - UINT32 MemoryInitUpdOffset; -/** Offset 0x0014 -**/ - UINT32 SiliconInitUpdOffset; -/** Offset 0x0018 -**/ - MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0080 -**/ - SILICON_INIT_UPD SiliconInitUpd; -} UPD_DATA_REGION; - -#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ -#define FSP_IMAGE_REV 0x00000000 - -typedef struct _VPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 PcdVpdRegionSign; -/** Offset 0x0008 - PcdImageRevision -**/ - UINT32 PcdImageRevision; -/** Offset 0x000C -**/ - UINT32 PcdUpdRegionOffset; -} VPD_DATA_REGION; - -#pragma pack() - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Gerrit-Change-Number: 30946 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: soc/intel/baytrail: Use non-evict CAR setup
by Arthur Heymans (Code Review) 11 Feb '19

11 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30814 Change subject: soc/intel/baytrail: Use non-evict CAR setup ...................................................................... soc/intel/baytrail: Use non-evict CAR setup The CAR setup is almost identical to the cpu/intel/non-evict CAR setup, with the only difference that L2 cache needs to be separately enabled. Currently this assumes that it is possible to use a static Kconfig option to cover all CPU's requiring this. Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/Kconfig A src/cpu/intel/car/non-evict/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/romstage/Makefile.inc D src/soc/intel/baytrail/romstage/cache_as_ram.inc 6 files changed, 21 insertions(+), 218 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30814/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index f5d0ab9..18f73b4 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -36,3 +36,4 @@ source src/cpu/intel/turbo/Kconfig source src/cpu/intel/common/Kconfig source src/cpu/intel/microcode/Kconfig +source src/cpu/intel/car/non-evict/Kconfig diff --git a/src/cpu/intel/car/non-evict/Kconfig b/src/cpu/intel/car/non-evict/Kconfig new file mode 100644 index 0000000..faf13e7 --- /dev/null +++ b/src/cpu/intel/car/non-evict/Kconfig @@ -0,0 +1,5 @@ +config CPU_HAS_L2_ENABLE_MSR + bool + help + Select this in Kconfig of CPU sockets/SOC where the CPU + has an MSR to enable the L2 CPU cache diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d2beaa7..3203159 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -24,6 +24,7 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e .global bootblock_pre_c_entry @@ -133,6 +134,18 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr +#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR) + /* + * Enable the L2 cache. Currently this assumes that this + * only affect socketed CPU's for which this is always valid, + * hence the static preprocesser. + */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr +#endif + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index ade908f..e824ee4 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -40,6 +40,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select CPU_INTEL_COMMON + select CPU_HAS_L2_ENABLE_MSR config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index aa10ba6..f1a3463 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h romstage-y += romstage.c romstage-y += raminit.c diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc deleted file mode 100644 index 4326636..0000000 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> -#include <cpu/x86/msr.h> - -#include "fmap_config.h" - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) -#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) -#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) - -#define NoEvictMod_MSR 0x2e0 -#define BBL_CR_CTL3_MSR 0x11e - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Configure the default memory type to uncacheable as well as disable - * fixed and variable range mtrrs. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x22) - /* Zero the variable MTRRs. */ - movl $IA32_MCG_CAP, %ecx - rdmsr - movzx %al, %ebx - /* First variable MTRR. */ - movl $MTRR_PHYS_BASE(0), %ecx - xorl %eax, %eax - xorl %edx, %edx -1: - wrmsr - inc %ecx - dec %ebx - jnz 1b - - /* Clear/disable fixed MTRRs */ - mov $fixed_mtrr_list_size, %ebx - xor %eax, %eax - xor %edx, %edx - -clear_fixed_mtrr: - add $-2, %ebx - movzwl fixed_mtrr_list(%ebx), %ecx - wrmsr - jnz clear_fixed_mtrr - - /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ - movl $0x80000008, %eax - cpuid - movb %al, %cl - sub $32, %cl - movl $1, %edx - shl %cl, %edx - subl $1, %edx - - /* Preload high word of address mask (in %edx) for Variable - * MTRRs 0 and 1. - */ -addrsize_set_high: - xorl %eax, %eax - movl $MTRR_PHYS_MASK(0), %ecx - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - wrmsr - - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - rdmsr - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x25) - /* Set code caching up for romstage. */ - movl $(MTRR_PHYS_BASE(1)), %ecx - movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x26) - - /* Enable the L2 cache. */ - movl $BBL_CR_CTL3_MSR, %ecx - rdmsr - orl $0x100, %eax - wrmsr - - post_code(0x27) - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - wrmsr - - post_code(0x28) - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* enable no evict mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $2, %eax - wrmsr - - post_code(0x29) - - /* Setup the stack. */ - mov $_car_stack_end, %esp - - /* Need to align stack to 16 bytes at call instruction. Account for - the pushes below. */ - andl $0xfffffff0, %esp - subl $4, %esp - - /* push TSC and BIST to stack */ - movd %mm0, %eax - pushl %eax /* BIST */ - movd %mm2, %eax - pushl %eax /* tsc[63:32] */ - movd %mm1, %eax - pushl %eax /* tsc[31:0] */ - -before_c_entry: - post_code(0x2a) - call bootblock_c_entry_bist - - /* Should never see this postcode */ - post_code(POST_DEAD_CODE) - -.Lhlt: - hlt - jmp .Lhlt - -fixed_mtrr_list: - .word MTRR_FIX_64K_00000 - .word MTRR_FIX_16K_80000 - .word MTRR_FIX_16K_A0000 - .word MTRR_FIX_4K_C0000 - .word MTRR_FIX_4K_C8000 - .word MTRR_FIX_4K_D0000 - .word MTRR_FIX_4K_D8000 - .word MTRR_FIX_4K_E0000 - .word MTRR_FIX_4K_E8000 - .word MTRR_FIX_4K_F0000 - .word MTRR_FIX_4K_F8000 -fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/c/coreboot/+/30814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Gerrit-Change-Number: 30814 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Revert "cpu/x86/mtrr: Fix sign overflow"
by Nico Huber (Code Review) 11 Feb '19

11 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31290 Change subject: Revert "cpu/x86/mtrr: Fix sign overflow" ...................................................................... Revert "cpu/x86/mtrr: Fix sign overflow" This reverts commit 6bbc8d8050b1d51ec4bf15003a2da54e20d476c7. The macro is used in assembly where integer suffixes are not portable. Also, it is unclear how this can overflow as it's already the macros purpose to avoid the overflow. Change-Id: I12c9bfe40891ae3afbfda05f60a20b59e2954aed Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31290/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 0398a2e..eb7d78d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -150,7 +150,7 @@ #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ -#define _FROM_4G_TOP(x) (((1UL << 20) - ((x) >> 12)) << 12) +#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12) /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. -- To view, visit https://review.coreboot.org/c/coreboot/+/31290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12c9bfe40891ae3afbfda05f60a20b59e2954aed Gerrit-Change-Number: 31290 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/lenovo/h8/Kconfig: increase ps2 timeout from 3000 to 5000ms
by Michael Bacarella (Code Review) 11 Feb '19

11 Feb '19

Michael Bacarella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31279 Change subject: ec/lenovo/h8/Kconfig: increase ps2 timeout from 3000 to 5000ms ...................................................................... ec/lenovo/h8/Kconfig: increase ps2 timeout from 3000 to 5000ms On my Thinkpad T420 the default 3000ms SeaBIOS timeout is too short, it takes nearly 5000ms for my keyboard to become ready. Timing out before it's ready leads to pretty bad behavior: I cannot use my keyboard at all to control SeaBIOS, nor the subsequent GRUB instance. (Linux is fine though, probably because it does its own keyboard init) Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Change-Id: Id1681bf3921c8b5dc124d4c4e9072f146f84f3a2 --- M src/ec/lenovo/h8/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31279/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f9b0b14..9df60de 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -7,7 +7,7 @@ config SEABIOS_PS2_TIMEOUT int depends on PAYLOAD_SEABIOS - default 3000 + default 5000 config H8_BEEP_ON_DEATH bool "Beep on fatal error" -- To view, visit https://review.coreboot.org/c/coreboot/+/31279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1681bf3921c8b5dc124d4c4e9072f146f84f3a2 Gerrit-Change-Number: 31279 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Move FSP_DEBUG_LEVEL option here
by Nico Huber (Code Review) 11 Feb '19

11 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31300 Change subject: soc/intel/fsp_broadwell_de: Move FSP_DEBUG_LEVEL option here ...................................................................... soc/intel/fsp_broadwell_de: Move FSP_DEBUG_LEVEL option here It is not mentioned in the FSP spec and doesn't seem to be implemented for any other FSP than the Broadwell-DE one. Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/fsp1_0/Kconfig M src/soc/intel/fsp_broadwell_de/fsp/Kconfig M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c 3 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31300/1 diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index b2338aa..4ce528f 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -34,17 +34,6 @@ hex default 0x4000 -config FSP_1_0_DEBUG_LEVEL - int "FSP debug level (0-3)" - default 0 - range 0 3 - help - Select the debug level, where: - 0: DISABLED - 1: MINIMUM - 2: NORMAL - 3: MAXIMUM - config FSP_HEADER_PATH string "Location of FSP headers" help diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig index b4f4886..f958e71 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig @@ -127,3 +127,14 @@ default n help Enable EHCI controller 2 + +config FSP_DEBUG_LEVEL + int "FSP debug level (0-3)" + default 0 + range 0 3 + help + Select the debug level, where: + 0: DISABLED + 1: MINIMUM + 2: NORMAL + 3: MAXIMUM diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index ef6212e..b8ef6b1 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -69,7 +69,7 @@ if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) UpdData->SerialPortType = 0; - UpdData->DebugOutputLevel = CONFIG_FSP_1_0_DEBUG_LEVEL; + UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL; /* * Memory Down -- To view, visit https://review.coreboot.org/c/coreboot/+/31300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e Gerrit-Change-Number: 31300 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQ
by Edward Hill (Code Review) 11 Feb '19

11 Feb '19

Edward Hill has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31278 Change subject: mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQ ...................................................................... mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQ Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. On this platform, interrupts are routed via the GPIO controller so need to be registered using GpioInt instead of Interrupt. BUG=b:123750725 BRANCH=grunt TEST=MKBP events still received (with matching EC and kernel changes) Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f Signed-off-by: Edward Hill <ecgh(a)chromium.org> --- M src/ec/google/chromeec/acpi/cros_ec.asl M src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h M src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h M src/mainboard/google/kahlee/variants/baseboard/gpio.c 4 files changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31278/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index a5f9202..d41071e 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -32,6 +32,17 @@ }) #endif +#ifdef EC_ENABLE_SYNC_IRQ_GPIO + Name (_CRS, ResourceTemplate () + { + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, ,) + { + EC_SYNC_IRQ + } + }) +#endif + #ifdef EC_ENABLE_MKBP_DEVICE Device (CKSC) { diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h index e90724e..12c6de6 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h @@ -15,3 +15,9 @@ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h index 5a6b540..3ddabb1 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h @@ -14,3 +14,6 @@ */ #include <baseboard/gpio.h> + +/* EC sync irq is AGPIO 10 */ +#define EC_SYNC_IRQ 10 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index e9ae28c..9db26c7 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -117,8 +117,8 @@ /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ PAD_GPI(GPIO_8, PULL_UP), - /* GPIO_10 - SLP_S0_L (currently not used) */ - PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), + /* GPIO_10 - SLP_S0_L, EC_SYNC_IRQ */ + PAD_GPI(GPIO_10, PULL_UP), /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ PAD_SCI(GPIO_11, PULL_UP, EDGE_LOW), -- To view, visit https://review.coreboot.org/c/coreboot/+/31278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f Gerrit-Change-Number: 31278 Gerrit-PatchSet: 1 Gerrit-Owner: Edward Hill <ecgh(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: remove the upcoming events chapter from the conference...
by Martin Kepplinger (Code Review) 11 Feb '19

11 Feb '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31266 Change subject: Documentation: remove the upcoming events chapter from the conferences page ...................................................................... Documentation: remove the upcoming events chapter from the conferences page I think our docs inside of the codebase might not be the ideal place to announce future events. First, they might be scheduled so shortly before the conference that the change, if at all done, would barely make it to the repo and the web. Also, _if_ really maintained, it would churn the docs unnessesarily. But, I doubt that anyone of us would want to maintain this here at all. Lastly, I think that nobody out there would _look for_ upcoming events in coreboot's documentation. We have bigger problems in the Documentation directory than this :) Change-Id: I918e17a427405a05722c6e0d61dc422f94cac809 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M Documentation/community/conferences.md 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31266/1 diff --git a/Documentation/community/conferences.md b/Documentation/community/conferences.md index 61a945a..e282aba 100644 --- a/Documentation/community/conferences.md +++ b/Documentation/community/conferences.md @@ -10,10 +10,6 @@ Depending on the nature of the conference, coreboot developers might bring their development kit with them and conduct development sessions. -## Upcoming events - -TODO: add them - ## Talks [Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_fa… by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebo…) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf )) (2019-02-03) -- To view, visit https://review.coreboot.org/c/coreboot/+/31266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I918e17a427405a05722c6e0d61dc422f94cac809 Gerrit-Change-Number: 31266 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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