coreboot-gerrit February 2019

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Change in ...coreboot[master]: Documentation: add the most recent talks to the conferences page
by Martin Kepplinger (Code Review) 11 Feb '19

11 Feb '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31265 Change subject: Documentation: add the most recent talks to the conferences page ...................................................................... Documentation: add the most recent talks to the conferences page Add Philipps great 35c3 talk and Davids and Andreas fosdem talk to the conferences page. linuxboot adds those to their website too but they can't be linked to too often :) Change-Id: I1e7ce078020dc5e9c9d9d47210c70ee16ef2f82e Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M Documentation/community/conferences.md 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31265/1 diff --git a/Documentation/community/conferences.md b/Documentation/community/conferences.md index 5531d51..61a945a 100644 --- a/Documentation/community/conferences.md +++ b/Documentation/community/conferences.md @@ -16,4 +16,7 @@ ## Talks -TODO: link to recorded talks +[Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_fa… by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebo…) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf )) (2019-02-03) + +[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018) +([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27) -- To view, visit https://review.coreboot.org/c/coreboot/+/31265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e7ce078020dc5e9c9d9d47210c70ee16ef2f82e Gerrit-Change-Number: 31265 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: add link to chromebookdb.com to distribution page
by Martin Kepplinger (Code Review) 11 Feb '19

11 Feb '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31263 Change subject: Documentation: add link to chromebookdb.com to distribution page ...................................................................... Documentation: add link to chromebookdb.com to distribution page As suggested by Philipp, let's add this link. Change-Id: I6ff21f37a04dc5a9c3db1ff7ac9a786fb0b51211 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M Documentation/distributions.md 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31263/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index f73b90c..b3b9dac 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -17,11 +17,12 @@ ### ChromeOS Devices -All ChromeOS devices (Chromebooks, Chromeboxes, Chromebit, etc) released from -2012 onward use coreboot for their main system firmware. Additionally, starting -with the 2013 Chromebook Pixel, the firmware running on the Embedded Controller -(EC - a small microcontroller which provides functions like battery management, -keyboard support, and sensor interfacing) is open source as well. +All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes, +Chromebit, etc) released from 2012 onward use coreboot for their main system +firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware +running on the Embedded Controller (EC - a small microcontroller which provides +functions like battery management, keyboard support, and sensor interfacing) +is open source as well. ### Libretrend -- To view, visit https://review.coreboot.org/c/coreboot/+/31263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff21f37a04dc5a9c3db1ff7ac9a786fb0b51211 Gerrit-Change-Number: 31263 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: add the Heads project to the list of distributions
by Martin Kepplinger (Code Review) 11 Feb '19

11 Feb '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31257 Change subject: Documentation: add the Heads project to the list of distributions ...................................................................... Documentation: add the Heads project to the list of distributions As this is a unique, actively maintained project, we should probably point there too. The text is just copied parts of the http://osresearch.net/ website. Change-Id: Ib2a8e4b28bc94c5dc6a1ae9388f96ad2c502ccab Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M Documentation/distributions.md 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31257/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index eaa61be..f73b90c 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -59,3 +59,15 @@ His firmware images are significantly older, and not actively maintained or supported, but worth a look if you need Legacy Boot support and is not available via Mr Chromebox's firmware. + +### Heads + +[Heads](http://osresearch.net) is an open source custom firmware and OS +configuration for laptops and servers that aims to provide slightly better +physical security and protection for data on the system. Unlike +[Tails](https://tails.boum.org/), which aims to be a stateless OS that leaves +no trace on the computer of its presence, Heads is intended for the case where +you need to store data and state on the computer. +Heads is not just another Linux distribution – it combines physical hardening +of specific hardware platforms and flash security features with custom coreboot +firmware and a Linux boot loader in ROM. -- To view, visit https://review.coreboot.org/c/coreboot/+/31257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2a8e4b28bc94c5dc6a1ae9388f96ad2c502ccab Gerrit-Change-Number: 31257 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: amd: Remove unused defines
by Peter Lemenkov (Code Review) 11 Feb '19

11 Feb '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31288 Change subject: amd: Remove unused defines ...................................................................... amd: Remove unused defines grep -ER $FAM10_SCAN_PCI_BUS\|FAM10_ALLOCATE_IO_RANGE$ shows nothing. Change-Id: Id0d321c80a9a393fcc0d9c2a5a675dba48516160 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c 19 files changed, 0 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31288/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index bb14c59..244dfad 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -15,9 +15,6 @@ #define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7d245e7..a3de524 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -15,10 +15,6 @@ #define SYSTEM_TYPE 1 /* SERVER = 0, DESKTOP = 1, MOBILE = 2 */ -/* used by incoherent_ht */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 538e7a7..217e292 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -17,10 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 58fea20..d19ebda 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -15,10 +15,6 @@ #define SYSTEM_TYPE 0 /* SERVER */ -/* used by incoherent_ht */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 0e65b53..d4a9fe3 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -15,10 +15,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ -/* used by incoherent_ht */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 59579fb..e25120e 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -17,9 +17,6 @@ * GNU General Public License for more details. */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 3f78c4c..db81a93 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -17,9 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 4802b9d..a9117f7 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -17,10 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 8dbd9e5..d86db7a 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -17,9 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 061764d..d3794af 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -15,9 +15,6 @@ #define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 252add0..9119041 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -17,9 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index bfbb519..6d2eed4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -21,9 +21,6 @@ * GNU General Public License for more details. */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 16d3068..77f85d9 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -17,9 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 9701193..95ac19e 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -18,9 +18,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 9770cf7..b5acf36 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -15,9 +15,6 @@ * GNU General Public License for more details. */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index ed6d0ac..18a4631b0 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -15,9 +15,6 @@ * GNU General Public License for more details. */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 83b9956..e3dc87d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -15,9 +15,6 @@ * GNU General Public License for more details. */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index ef3a372..7ca47b4 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -17,9 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index a3bc1d4..babac6f 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -15,9 +15,6 @@ * GNU General Public License for more details. */ -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0d321c80a9a393fcc0d9c2a5a675dba48516160 Gerrit-Change-Number: 31288 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/pcengines/apu2/OemCustomize.c: Enable CPB feature
by Michał Żygowski (Code Review) 11 Feb '19

11 Feb '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31229 Change subject: src/mainboard/pcengines/apu2/OemCustomize.c: Enable CPB feature ...................................................................... src/mainboard/pcengines/apu2/OemCustomize.c: Enable CPB feature Enable Core Performance Boost feature in automatic mode. Also enable C6 state which is a dependency for proper CPB operation. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5e080bfaee06fd13cedf5151d4a598ec212213f2 --- M src/mainboard/pcengines/apu2/OemCustomize.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/31229/1 diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index a729860..700f4c7 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -97,4 +97,6 @@ ) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->PlatformConfig.CStateMode = CStateModeC6; + InitEarly->PlatformConfig.CpbMode = CpbModeAuto; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e080bfaee06fd13cedf5151d4a598ec212213f2 Gerrit-Change-Number: 31229 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/pci_ops: Move questionable pci_locate() variants
by Kyösti Mälkki (Code Review) 11 Feb '19

11 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31304 Change subject: device/pci_ops: Move questionable pci_locate() variants ...................................................................... device/pci_ops: Move questionable pci_locate() variants These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0. It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>. There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere. Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/io.h M src/device/pci_early.c M src/include/device/pci.h M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c 9 files changed, 82 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31304/1 diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 71e3ba0..4b4a178 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -205,10 +205,6 @@ #ifdef __SIMPLE_DEVICE__ -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - - #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) #include <arch/pci_io_cfg.h> @@ -268,47 +264,6 @@ pci_io_write_config32(dev, where, value); } -static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id, - pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -static inline pci_devfn_t pci_locate_device(unsigned int pci_id, - pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -static inline pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, - unsigned int bus) -{ - pci_devfn_t dev, last; - - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - - for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - /* Generic functions for pnp devices */ static __always_inline void pnp_write_config( pnp_devfn_t dev, uint8_t reg, uint8_t value) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 9086e64..ea2ebd5 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -165,3 +165,34 @@ pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); } + +/* FIXME: A lot of issues using the following, please avoid. + * Assumes 256 PCI busses, scans them all even when PCI bridges are still + * disabled. Probes all functions even if 0 is not present. + */ +pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} + +pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus) +{ + pci_devfn_t dev, last; + + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f0724e0f..71d6b20 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -133,6 +133,12 @@ return pops; } +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); +pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); + #ifdef __SIMPLE_DEVICE__ unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap, unsigned int last); diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 2c722c8..7cbc141 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -17,6 +17,18 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> + +static pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} /* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ static void amd8111_enable_rom(void) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 70cf340..167986f 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <device/pci.h> #include <reset.h> #include "sb700.h" diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 2861ff0..62b20a3 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -17,6 +17,21 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ static void bcm5785_enable_rom(void) diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index c59343d..38b797d 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -17,8 +17,23 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> #include "i82371eb.h" +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} + static void bootblock_southbridge_init(void) { u16 reg16; diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 8ae7669..720cb0d 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <arch/io.h> +#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index de16717..4e91c0a 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <arch/io.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <southbridge/intel/common/smbus.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Gerrit-Change-Number: 31304 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: device/pci_early.c: Drop some guards
by Kyösti Mälkki (Code Review) 11 Feb '19

11 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31303 Change subject: device/pci_early.c: Drop some guards ...................................................................... device/pci_early.c: Drop some guards With PCI_DEV() always defined it is no longer necessary to exclude this code from building. Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/init.c M src/device/Makefile.inc M src/device/pci_early.c M src/include/device/pci.h 4 files changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31303/1 diff --git a/src/console/init.c b/src/console/init.c index 8aa7d7d..89be51b 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -74,10 +74,9 @@ if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT)) car_set_var(console_inited, 1); -#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) - if (!ENV_SMM && !ENV_RAMSTAGE) + if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && + !ENV_SMM && !ENV_RAMSTAGE) pci_early_bridge_init(); -#endif console_hw_init(); diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bed0f71..39df1c7 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -13,7 +13,6 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c -ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c @@ -28,12 +27,10 @@ romstage-y += device_const.c ramstage-y += device_const.c -ifeq ($(CONFIG_ARCH_X86),y) bootblock-$(CONFIG_PCI) += pci_early.c verstage-$(CONFIG_PCI) += pci_early.c romstage-$(CONFIG_PCI) += pci_early.c postcar-$(CONFIG_PCI) += pci_early.c -endif subdirs-y += oprom dram diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 4cf8c7e..9086e64 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -18,9 +18,10 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> #include <delay.h> -#if !ENV_RAMSTAGE unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; @@ -68,9 +69,6 @@ { return pci_find_next_capability(dev, cap, 0); } -#endif - -#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) { @@ -167,4 +165,3 @@ pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); } -#endif /* CONFIG_EARLY_PCI_BRIDGE */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index b750205..f0724e0f 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -143,7 +143,6 @@ unsigned int pci_find_capability(struct device *dev, unsigned int cap); #endif /* __SIMPLE_DEVICE__ */ -void pci_early_bridge_init(void); void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); @@ -157,4 +156,6 @@ #endif /* CONFIG_PCI */ +void pci_early_bridge_init(void); + #endif /* PCI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac Gerrit-Change-Number: 31303 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: device/pci: Always define PCI_DEV()
by Kyösti Mälkki (Code Review) 11 Feb '19

11 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31302 Change subject: device/pci: Always define PCI_DEV() ...................................................................... device/pci: Always define PCI_DEV() This has uses outside ARCH_x86 and/or __PRE_RAM__. Change-Id: I2eec674ec5ba4ffe03a20db0f73cf87e5e4b4d0d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/io.h M src/include/device/pci_type.h 2 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31302/1 diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 1a27994..71e3ba0 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -205,11 +205,6 @@ #ifdef __SIMPLE_DEVICE__ -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) - #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) @@ -273,7 +268,6 @@ pci_io_write_config32(dev, where, value); } -#define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev) { diff --git a/src/include/device/pci_type.h b/src/include/device/pci_type.h index 2849ece..0b08e8d 100644 --- a/src/include/device/pci_type.h +++ b/src/include/device/pci_type.h @@ -19,4 +19,11 @@ typedef u32 pci_devfn_t; typedef u32 pnp_devfn_t; +#define PCI_DEV(SEGBUS, DEV, FN) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) + +#define PCI_DEV_INVALID (0xffffffffU) + #endif /* DEVICE_PCI_TYPE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eec674ec5ba4ffe03a20db0f73cf87e5e4b4d0d Gerrit-Change-Number: 31302 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: cpu/intel/car/p3: Update microcode in CAR setup
by Kyösti Mälkki (Code Review) 11 Feb '19

11 Feb '19

Kyösti Mälkki has uploaded a new patch set (#4) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/30776 ) Change subject: cpu/intel/car/p3: Update microcode in CAR setup ...................................................................... cpu/intel/car/p3: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30682 --- M src/cpu/intel/car/p3/cache_as_ram.S 1 file changed, 33 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30776/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9 Gerrit-Change-Number: 30776 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: cpu/intel/car/p3: Update microcode in CAR setup
by HAOUAS Elyes (Code Review) 11 Feb '19

11 Feb '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30776 ) Change subject: cpu/intel/car/p3: Update microcode in CAR setup ...................................................................... Patch Set 3: > (1 comment) () Are missing -- To view, visit https://review.coreboot.org/c/coreboot/+/30776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9 Gerrit-Change-Number: 30776 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 11 Feb 2019 11:11:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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