coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: cpu/intel/car/p3: Update microcode in CAR setup
by HAOUAS Elyes (Code Review) 11 Feb '19

11 Feb '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30776 ) Change subject: cpu/intel/car/p3: Update microcode in CAR setup ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30776/3/src/cpu/intel/car/p3/cache_as_ram.S File src/cpu/intel/car/p3/cache_as_ram.S: https://review.coreboot.org/#/c/30776/3/src/cpu/intel/car/p3/cache_as_ram.S… PS3, Line 105: CACHE_ROM_BASE | MTRR_TYPE_WRPROT ( CACHE_ROM_BASE | MTRR_TYPE_WRPROT ) ? -- To view, visit https://review.coreboot.org/c/coreboot/+/30776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9 Gerrit-Change-Number: 30776 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 11 Feb 2019 07:38:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27277 to look at the new patch set (#4). Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... soc/amd/common: Fix AmdLateRunApTask() Third parameter ConfigPtr of the callout is of type AP_EXE_PARAMS and needs to be passed back to AGESA with AmdLateRunApTask() call. Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/def_callouts.c 3 files changed, 6 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/27277/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: arch/x86: Drop stale comment
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31294 Change subject: arch/x86: Drop stale comment ...................................................................... arch/x86: Drop stale comment Change-Id: I1ba6dfb502ff053ccf82d2acc5fefbbfe09d647b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/io.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/31294/1 diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index f62dc6c..1a27994 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -216,11 +216,6 @@ #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write - * memory above 4G, We don't need to set %fs, and %gs anymore - * Before that We need to use %gs, and leave %fs to other RAM access - */ - #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba6dfb502ff053ccf82d2acc5fefbbfe09d647b Gerrit-Change-Number: 31294 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: nb/via/vx900: Replace pci_mod_configX()
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31272 Change subject: nb/via/vx900: Replace pci_mod_configX() ...................................................................... nb/via/vx900: Replace pci_mod_configX() If clr_mask == 0, use pci_or_configX(). If clr_mask != 0, invert mask and use pci_update_configX(). Change-Id: I4ae64e9b635b3759e4cffc4bbdf029411a4e0f42 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/via/epia-m850/romstage.c M src/northbridge/via/vx900/chrome9hd.c M src/northbridge/via/vx900/early_host_bus_ctl.c M src/northbridge/via/vx900/early_vx900.c M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/memmap.c M src/northbridge/via/vx900/northbridge.c M src/northbridge/via/vx900/pci_util.c M src/northbridge/via/vx900/raminit_ddr3.c M src/northbridge/via/vx900/sata.c M src/northbridge/via/vx900/traf_ctrl.c M src/northbridge/via/vx900/vx900.h 12 files changed, 85 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31272/1 diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index d9ed0e6..8c3a4c3 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -96,5 +96,5 @@ /* FIXME: See if this is needed or take this out please */ /* Disable Memcard and SDIO */ - pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4)); + pci_or_config8(LPC, 0x51, (1 << 7) | (1 << 4)); } diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 8d2cf9c..abba4d3 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -151,7 +151,7 @@ pci_write_config8(dev, 0xb2, ((0xff << (fb_pow - 2)) & ~(1 << 7))); vga_sr_write(0x68, (0xff << (fb_pow - 1))); /* And also that the framebuffer is in the system, RAM */ - pci_mod_config8(dev, 0xb0, 0, 1 << 0); + pci_or_config8(dev, 0xb0, 1 << 0); } /** @@ -175,13 +175,13 @@ /* Step 1 - Enable VGA controller */ /* FIXME: This is the VGA hole @ 640k-768k, and the vga port io * We need the port IO, but can we disable the memory hole? */ - pci_mod_config8(mcu, 0xa4, 0, (1 << 7)); /* VGA memory hole */ + pci_or_config8(mcu, 0xa4, (1 << 7)); /* VGA memory hole */ /* Step 2 - Forward MDA cycles to GFX */ - pci_mod_config8(host, 0x4e, 0, (1 << 1)); + pci_or_config8(host, 0x4e, (1 << 1)); /* Step 3 - Enable GFX I/O space */ - pci_mod_config8(dev, PCI_COMMAND, 0, PCI_COMMAND_IO); + pci_or_config8(dev, PCI_COMMAND, PCI_COMMAND_IO); /* Step 4 - Enable video subsystem */ vga_enable_mask((1 << 0), (1 << 0)); @@ -248,7 +248,7 @@ struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); /* FIXME: here? -=- ACLK 250MHz */ - pci_mod_config8(mcu, 0xbb, 0, 0x01); + pci_or_config8(mcu, 0xbb, 0x01); } static void chrome9hd_disable(struct device *dev) @@ -257,7 +257,7 @@ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); /* Disable GFX - This step effectively renders the GFX inert * It won't even show up as a PCI device during enumeration */ - pci_mod_config8(mcu, 0xa1, 1 << 7, 0); + pci_update_config8(mcu, 0xa1, (u8)~(1 << 7), 0); } static struct device_operations chrome9hd_operations = { diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c index 159b2a4..92bb44d 100644 --- a/src/northbridge/via/vx900/early_host_bus_ctl.c +++ b/src/northbridge/via/vx900/early_host_bus_ctl.c @@ -19,32 +19,32 @@ static void vx900_cpu_bus_preram_setup(void) { /* Faster CPU to DRAM Cycle */ - pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08); + pci_update_config8(HOST_BUS, 0x50, ~0x0f, 0x08); /* CPU Interface Control - Basic Options */ - pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c); + pci_or_config8(HOST_BUS, 0x51, 0x6c); /*CPU Interface Control - Advanced Options */ pci_write_config8(HOST_BUS, 0x52, 0xc7); /* Enable 8QW burst and 4QW request merging [4] and [2] * and special mode for read cycles bit[3] */ - pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 4) | (1 << 2) | (1 << 3)); + pci_or_config8(HOST_BUS, 0x54, (1 << 4) | (1 << 2) | (1 << 3)); /* High priority upstream requests on V4 bus */ pci_write_config8(HOST_BUS, 0x56, 0x03); /* CPU to DRAM extra 1T access control */ - pci_mod_config8(HOST_BUS, 0x59, 0x00, (1 << 2)); + pci_or_config8(HOST_BUS, 0x59, (1 << 2)); /* Queue reordering */ - pci_mod_config8(HOST_BUS, 0x5f, 0x00, (1 << 6)); + pci_or_config8(HOST_BUS, 0x5f, (1 << 6)); /* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */ - pci_mod_config8(HOST_BUS, 0x98, 0x00, 0x60); + pci_or_config8(HOST_BUS, 0x98, 0x60); /* 1T delay for data on CPU bus */ pci_write_config8(HOST_BUS, 0x9e, 0x0e); /* Arbitrate ownership of DRAM controller a few cycles earlier */ - pci_mod_config8(HOST_BUS, 0x9f, 0x00, (1 << 7)); + pci_or_config8(HOST_BUS, 0x9f, (1 << 7)); /* Write retire policy */ pci_write_config8(HOST_BUS, 0x5d, 0xa2); /* Occupancy timer */ pci_write_config8(HOST_BUS, 0x53, 0x44); /* Medium Threshold for Write Retire Policy - 6 requests */ - pci_mod_config8(HOST_BUS, 0x56, 0x00, 0x60); + pci_or_config8(HOST_BUS, 0x56, 0x60); /* Bandwidth timer */ pci_write_config8(HOST_BUS, 0x5e, 0x44); } diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 1260941..fe858b6 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -109,7 +109,7 @@ pci_write_config8(MCU, 0x83, 0x31); /* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */ - pci_mod_config8(LPC, 0x41, 1 << 7, 0); /* LPC ROM 896k - 960k */ + pci_update_config8(LPC, 0x41, (u8)~(1 << 7), 0); /* LPC ROM 896k - 960k */ pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */ pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */ @@ -126,5 +126,5 @@ void vx900_disable_gfx(void) { /* Disable GFX */ - pci_mod_config8(MCU, 0xa1, 1 << 7, 0); + pci_update_config8(MCU, 0xa1, (u8)~(1 << 7), 0); } diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 27e2384..40c4299 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -53,7 +53,7 @@ struct northbridge_via_vx900_config *nb = (void *)dev->chip_info; /* GPIO 11,10 to SATALED [1,0] */ - pci_mod_config8(dev, 0xe4, 0, 1 << 0); + pci_or_config8(dev, 0xe4, 1 << 0); /* Route the external interrupt line */ extint = nb->ext_int_route_to_pirq; @@ -65,7 +65,7 @@ extint); val = extint - 'A'; val |= (1 << 3); /* bit3 enables the external int */ - pci_mod_config8(dev, 0x55, 0xf, val); + pci_update_config8(dev, 0x55, ~0xf, val); } } @@ -78,11 +78,11 @@ /* FIXME: Setting this seems to hang our system */ /* Positive decoding for ROM + APIC + On-board IO ports */ - pci_mod_config8(dev, 0x6c, 0, (1 << 2) | (1 << 3) | (1 << 7)); + pci_or_config8(dev, 0x6c, (1 << 2) | (1 << 3) | (1 << 7)); /* Enable DMA channels. BIOS guide recommends DMA channel 2 off */ pci_write_config8(dev, 0x53, 0xfb); /* Disable PCI/DMA Memory Cycles Output to PCI Bus */ - pci_mod_config8(dev, 0x5b, (1 << 5), 0); + pci_update_config8(dev, 0x5b, ~(1 << 5), 0); /* DMA bandwidth control - Improved bandwidth */ pci_write_config8(dev, 0x53, 0xff); /* ISA Positive Decoding control */ @@ -147,20 +147,20 @@ * So much work for one line of code. Talk about bloat :) * The 8259 PIC should still work even if the IOAPIC is enabled, so * there's no crime in enabling the IOAPIC here. */ - pci_mod_config8(dev, 0x58, 0, 1 << 6); + pci_or_config8(dev, 0x58, 1 << 6); } static void vx900_lpc_interrupt_stuff(struct device *dev) { /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports * And enable I/O recovery time */ - pci_mod_config8(dev, 0x40, 0, (1 << 2) | (1 << 6)); + pci_or_config8(dev, 0x40, (1 << 2) | (1 << 6)); /* Set serial IRQ frame width to 6 PCI cycles (recommended by VIA) * And enable serial IRQ */ - pci_mod_config8(dev, 0x52, 3 << 0, (1 << 3) | (1 << 0)); + pci_update_config8(dev, 0x52, ~(3 << 0), (1 << 3) | (1 << 0)); /* Disable IRQ12 storm FIXME: bad comment */ - pci_mod_config8(dev, 0x51, (1 << 2), 0); + pci_update_config8(dev, 0x51, ~(1 << 2), 0); pci_write_config8(dev, 0x4c, (1 << 6)); @@ -253,12 +253,12 @@ PCI_DEVICE_ID_VIA_VX900_LPC, 0); /* Take care of INTA -> INTD */ - pci_mod_config8(lpc, 0x55, (0xf << 4), pirq[0] << 4); + pci_update_config8(lpc, 0x55, (u8)~(0xf << 4), pirq[0] << 4); pci_write_config8(lpc, 0x56, pirq[1] | (pirq[2] << 4)); pci_write_config8(lpc, 0x57, pirq[3] << 4); /* Enable INTE -> INTH to be on separate IRQs */ - pci_mod_config8(lpc, 0x46, 0, 1 << 4); + pci_or_config8(lpc, 0x46, 1 << 4); /* Now do INTE -> INTH */ pci_write_config8(lpc, 0x44, pirq[4] | (pirq[5] << 4)); pci_write_config8(lpc, 0x45, pirq[6] | (pirq[7] << 4)); diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 8cc7607..9940502 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -83,7 +83,7 @@ fb_pow--; size_mb = (1 << fb_pow); - pci_mod_config8(MCU, 0xa1, 7 << 4, (fb_pow - 2) << 4); + pci_update_config8(MCU, 0xa1, ~(7 << 4), (fb_pow - 2) << 4); } /* Gets the configured framebuffer size as a power of 2 */ diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index ca41450..41a1073 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -129,7 +129,7 @@ /* The "start remapping from where ?" register */ reg16 = ((tolm >> 20) & 0xfff) << 4; - pci_mod_config16(mcu, 0x84, 0xfff0, reg16); + pci_update_config16(mcu, 0x84, (u16)~0xfff0, reg16); /* Find the chunk size */ tor = vx900_get_top_of_ram(mcu); diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index 08e2b54..afd35a1 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -38,45 +38,3 @@ printk(BIOS_DEBUG, "\n"); } } - -#ifdef __SIMPLE_DEVICE__ -void pci_mod_config8(pci_devfn_t dev, unsigned int where, uint8_t clr_mask, - uint8_t set_mask) -#else -void pci_mod_config8(struct device *dev, unsigned int where, uint8_t clr_mask, - uint8_t set_mask) -#endif -{ - uint8_t reg8 = pci_read_config8(dev, where); - reg8 &= ~clr_mask; - reg8 |= set_mask; - pci_write_config8(dev, where, reg8); -} - -#ifdef __SIMPLE_DEVICE__ -void pci_mod_config16(pci_devfn_t dev, unsigned int where, - uint16_t clr_mask, uint16_t set_mask) -#else -void pci_mod_config16(struct device *dev, unsigned int where, - uint16_t clr_mask, uint16_t set_mask) -#endif -{ - uint16_t reg16 = pci_read_config16(dev, where); - reg16 &= ~clr_mask; - reg16 |= set_mask; - pci_write_config16(dev, where, reg16); -} - -#ifdef __SIMPLE_DEVICE__ -void pci_mod_config32(pci_devfn_t dev, unsigned int where, - uint32_t clr_mask, uint32_t set_mask) -#else -void pci_mod_config32(struct device *dev, unsigned int where, - uint32_t clr_mask, uint32_t set_mask) -#endif -{ - uint32_t reg32 = pci_read_config32(dev, where); - reg32 &= ~clr_mask; - reg32 |= set_mask; - pci_write_config32(dev, where, reg32); -} diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 7acab31..59d206c 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -485,9 +485,9 @@ /* Enable strong CLK driving for DIMMs with more than one rank */ if (dimm->dimm[0].ranks > 1) - pci_mod_config8(MCU, 0xd6, 0, (1 << 7)); + pci_or_config8(MCU, 0xd6, (1 << 7)); if (dimm->dimm[1].ranks > 1) - pci_mod_config8(MCU, 0xd6, 0, (1 << 6)); + pci_or_config8(MCU, 0xd6, (1 << 6)); /* DRAM ODT Lookup Table */ for (i = 0;; i++) { @@ -528,7 +528,7 @@ val = 0x8 | vr; /* Now move the value to the appropriate PR */ val <<= (pr * 4); - pci_mod_config16(MCU, 0x54, 0xf << (pr * 4), val); + pci_update_config16(MCU, 0x54, ~(0xf << (pr * 4)), val); printram("Mapping PR %u to VR %u\n", pr, vr); } @@ -629,7 +629,7 @@ val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); printram("Selected tWTR : %uT\n", val); reg8 |= ((val - 2) & 0x7); - pci_mod_config8(MCU, 0xc4, 0x3f, reg8); + pci_update_config8(MCU, 0xc4, ~0x3f, reg8); /* DRAM Timing for All Ranks - VI * [7:6] CKE Assertion Minimum Pulse Width @@ -662,7 +662,7 @@ u8 val; /* Step 1 - Reset the PLL */ - pci_mod_config8(MCU, 0x90, 0x00, 0x0f); + pci_or_config8(MCU, 0x90, 0x0f); /* Wait at least 10 ns; VIA code delays by 640us */ udelay(640); @@ -681,30 +681,30 @@ ctrl->tCK = TCK_266MHZ; } /* Restart the PLL with the desired frequency */ - pci_mod_config8(MCU, 0x90, 0x0f, val); + pci_update_config8(MCU, 0x90, ~0x0f, val); /* Step 3 - Wait for PLL to stabilize */ udelay(2000); /* Step 4 - Reset the DLL - Clear [7,4] */ - pci_mod_config8(MCU, 0x6b, 0x90, 0x00); + pci_update_config8(MCU, 0x6b, (u8)~0x90, 0x00); udelay(2000); /* Step 5 - Enable the DLL - Set bits [7,4] to 01b */ - pci_mod_config8(MCU, 0x6b, 0x00, 0x10); + pci_or_config8(MCU, 0x6b, 0x10); udelay(2000); /* Step 6 - Start DLL Calibration - Set bit [7] */ - pci_mod_config8(MCU, 0x6b, 0x00, 0x80); + pci_or_config8(MCU, 0x6b, 0x80); udelay(5); /* Step 7 - Finish DLL Calibration - Clear bit [7] */ - pci_mod_config8(MCU, 0x6b, 0x80, 0x00); + pci_update_config8(MCU, 0x6b, (u8)~0x80, 0x00); /* Step 8 - If we have registered DIMMs, we need to set bit[0] */ if (spd_dimm_is_registered_ddr3(ctrl->dimm_type)) { printram("Enabling RDIMM support in memory controller\n"); - pci_mod_config8(MCU, 0x6c, 0x00, 0x01); + pci_or_config8(MCU, 0x6c, 0x01); } } @@ -803,7 +803,7 @@ /* Was already done for us before calling us */ /* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ - pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ + pci_update_config8(MCU, 0x6b, ~0x07, 0x03); /* MSR Enable */ /* Step 09 - Issue MR2 cycle. Read a double word from the address * depended on DRAM's Rtt_WR and CWL settings. */ @@ -853,7 +853,7 @@ udelay(1000); /* Step 13 - Set Fun3_RX6B[2:0] to 110b (Long ZQ calibration cmd) */ - pci_mod_config8(MCU, 0x6b, 0x07, 0x06); /* Long ZQ */ + pci_update_config8(MCU, 0x6b, ~0x07, 0x06); /* Long ZQ */ /* Step 14 - Read a double word from any address of the DIMM. */ volatile_read(0); udelay(1000); @@ -873,9 +873,9 @@ vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP); /* Step 01 - Set Fun3_Rx6E[5] to 1b to support burst length. */ - pci_mod_config8(MCU, 0x6e, 0, 1 << 5); + pci_or_config8(MCU, 0x6e, 1 << 5); /* Step 02 - Set Fun3_RX69[0] to 0b (Disable Multiple Page Mode). */ - pci_mod_config8(MCU, 0x69, (1 << 0), 0x00); + pci_update_config8(MCU, 0x69, ~(1 << 0), 0x00); /* And set [7:6] to 10b ? */ pci_write_config8(MCU, 0x69, 0x87); @@ -887,7 +887,7 @@ pci_write_config8(MCU, 0x50, 0xd8); /* Step 05 - Set Fun3_RX6B[5] to 1b to de-assert RESET# and wait for at * least 500 us. */ - pci_mod_config8(MCU, 0x6b, 0x00, (1 << 5)); + pci_or_config8(MCU, 0x6b, (1 << 5)); udelay(500); /* Step 6 -> 15 - Set the target physical rank to virtual rank 0 and @@ -903,9 +903,9 @@ vx900_map_pr_vr(i, 0); /* FIXME: Is this needed on HW init? */ - pci_mod_config8(MCU, 0x6b, 0x07, 0x01); /* Enable NOP */ + pci_update_config8(MCU, 0x6b, ~0x07, 0x01); /* Enable NOP */ volatile_read(0x0); /* Do NOP */ - pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ + pci_update_config8(MCU, 0x6b, ~0x07, 0x03); /* MSR Enable */ /* See init_dram_by_rank.c and get_basic_information.c * in the VIA provided code */ @@ -934,20 +934,20 @@ 0, 0); /* Normal SDRAM Mode */ - pci_mod_config8(MCU, 0x6b, 0x07, 0x00); + pci_update_config8(MCU, 0x6b, ~0x07, 0x00); /* Step 15, set the rank to virtual rank 3 */ vx900_map_pr_vr(i, 3); } /* Step 16 - Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ - pci_mod_config8(MCU, 0x6b, 0x07, 0x00); + pci_update_config8(MCU, 0x6b, ~0x07, 0x00); /* Set BA[0/1/2] to [A13/14/15] */ vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); /* Step 17 - Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */ - pci_mod_config8(MCU, 0x69, 0x00, (1 << 0)); + pci_or_config8(MCU, 0x69, (1 << 0)); printram("DIMM initialization sequence complete\n"); } @@ -961,7 +961,7 @@ { u32 addr; /* Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ - pci_mod_config8(MCU, 0x6b, 0x07, (3 << 0)); + pci_update_config8(MCU, 0x6b, ~0x07, (3 << 0)); /* Is this a funky rank with Address pins swapped? */ if (pin_swap) cmd = ddr3_mrs_mirror_pins(cmd); @@ -970,18 +970,18 @@ /* Execute the MRS */ volatile_read(addr); /* Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ - pci_mod_config8(MCU, 0x6b, 0x07, 0x00); + pci_update_config8(MCU, 0x6b, ~0x07, 0x00); } static void vx900_dram_enter_read_leveling(u8 pinswap) { /* Precharge all before issuing read leveling MRS to DRAM */ - pci_mod_config8(MCU, 0x06b, 0x07, 0x02); + pci_update_config8(MCU, 0x06b, ~0x07, 0x02); volatile_read(0x0); udelay(1000); /* Enable read leveling: Set D0F3Rx71[7]=1 */ - pci_mod_config8(MCU, 0x71, 0, (1 << 7)); + pci_or_config8(MCU, 0x71, (1 << 7)); /* Put DRAM in read leveling mode */ mrs_cmd_t cmd = ddr3_get_mr3(1); @@ -995,7 +995,7 @@ vx900_dram_send_soft_mrs(cmd, pinswap); /* Disable read leveling: Set D0F3Rx71[7]=0 */ - pci_mod_config8(MCU, 0x71, (1 << 7), 0); + pci_update_config8(MCU, 0x71, (u8)~(1 << 7), 0); } /* @@ -1096,7 +1096,7 @@ const u32 cal_addr = 0x20; /* Set IO calibration address */ - pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); + pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0)); /* Data pattern must be 0x00 for this calibration * See paragraph describing Rx8e */ pci_write_config8(MCU, 0x8e, 0x00); @@ -1128,7 +1128,7 @@ const u8 ref_cnt = pci_read_config8(MCU, 0xc7); pci_write_config8(MCU, 0xc7, 0); /* Set IO calibration address */ - pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); + pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0)); /* Data pattern must be 0x00 for this calibration * See paragraph describing Rx8e */ pci_write_config8(MCU, 0x8e, 0x00); @@ -1138,10 +1138,10 @@ /* From VIA code; Undocumented * In theory this enables MODT[3:0] to be asserted */ - pci_mod_config8(MCU, 0x9e, 0, 0x80); + pci_or_config8(MCU, 0x9e, 0x80); /* Trigger calibration: Set D0F3Rx71[1:0]=10b */ - pci_mod_config8(MCU, 0x71, 0x03, 0x02); + pci_update_config8(MCU, 0x71, ~0x03, 0x02); /* Wait for calibration to complete */ while (pci_read_config8(MCU, 0x71) & 0x02); @@ -1159,7 +1159,7 @@ /* Data pattern for calibration */ pci_write_config8(MCU, 0x8e, pattern); /* Trigger calibration */ - pci_mod_config8(MCU, 0x75, 0, 0x20); + pci_or_config8(MCU, 0x75, 0x20); /* Wait for calibration */ while (pci_read_config8(MCU, 0x75) & 0x20); } @@ -1171,9 +1171,9 @@ { const u32 cal_addr = 0x00; /* Set IO calibration address */ - pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); + pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0)); /* Set circuit to use calibration results - Clear Rx75[0] */ - pci_mod_config8(MCU, 0x75, 0x01, 0); + pci_update_config8(MCU, 0x75, ~0x01, 0); /* Run calibration with first data pattern */ vx900_tx_dqs_trigger_calib(0x5a); /* Run again with different pattern */ @@ -1188,7 +1188,7 @@ /* Data pattern for calibration */ pci_write_config8(MCU, 0x8e, 0x5a); /* Trigger calibration */ - pci_mod_config8(MCU, 0x75, 0, 0x02); + pci_or_config8(MCU, 0x75, 0x02); /* Wait for calibration */ while (pci_read_config8(MCU, 0x75) & 0x02); } @@ -1217,7 +1217,7 @@ } /* Put Rx DQS delay into manual mode (Set Rx[2,0] to 01) */ - pci_mod_config8(MCU, 0x71, 0x05, 0x01); + pci_update_config8(MCU, 0x71, ~0x05, 0x01); /* Now write the new settings */ vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); vx900_write_0x78_0x7f(dly->avg); @@ -1261,7 +1261,7 @@ dump_delay(rx_dq_cr->avg); } /* We need to put the setting on manual mode */ - pci_mod_config8(MCU, 0x71, 0, 1 << 4); + pci_or_config8(MCU, 0x71, 1 << 4); vx900_delay_calib_mode_select(CALIB_RxDQ_CR, CALIB_MANUAL); vx900_write_0x78_0x7f(rx_dq_cr->avg); @@ -1276,7 +1276,7 @@ /* We're good to go. Switch to manual and write the manual * setting */ - pci_mod_config8(MCU, 0x71, 0, 1 << 0); + pci_or_config8(MCU, 0x71, 1 << 0); vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); vx900_write_0x78_0x7f(rx_dqs->avg); break; @@ -1316,7 +1316,7 @@ /************* TxDQ *************/ /* FIXME: not sure if multiple page mode should be enabled here * Vendor BIOS does it */ - pci_mod_config8(MCU, 0x69, 0, 0x01); + pci_or_config8(MCU, 0x69, 0x01); dq_tries++; vx900_tx_dq_delay_calib(); @@ -1375,10 +1375,10 @@ else val = 0; val++; /* FIXME: vendor BIOS sets this to 3 */ - pci_mod_config8(MCU, 0x74, (0x03 << 1), ((val & 0x03) << 1)); + pci_update_config8(MCU, 0x74, ~(0x03 << 1), ((val & 0x03) << 1)); /* FIXME: The vendor BIOS increases the MD input delay - WHY ? */ - pci_mod_config8(MCU, 0xef, (3 << 4), 3 << 4); + pci_update_config8(MCU, 0xef, ~(3 << 4), 3 << 4); /**** Write delay control ****/ /* FIXME: The vendor BIOS does this, but WHY? @@ -1386,14 +1386,14 @@ * to depend on the DRAM frequency. */ /* Early DQ/DQS for write cycles */ - pci_mod_config8(MCU, 0x76, (3 << 2), 2 << 2); + pci_update_config8(MCU, 0x76, ~(3 << 2), 2 << 2); /* FIXME: The vendor BIOS does this - Output preamble ? */ pci_write_config8(MCU, 0x77, 0x10); /* Set BA[0/1/2] to [A17/18/19] */ vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP); /* Disable Multiple Page Mode - Set Rx69[0] to 0 */ - pci_mod_config8(MCU, 0x69, (1 << 0), 0x00); + pci_update_config8(MCU, 0x69, ~(1 << 0), 0x00); /* It's very important that we keep all ranks which are not calibrated * mapped to VR3. Even if we disable them, if they are mapped to VR0 @@ -1422,7 +1422,7 @@ dump_delay_range(delay_cal.rx_dqs); /* Enable multiple page mode for when calibrating transmit delays */ - pci_mod_config8(MCU, 0x69, 0, 1 << 1); + pci_or_config8(MCU, 0x69, 1 << 1); /* * Unlike the receive delays, we need to run the transmit calibration @@ -1464,7 +1464,7 @@ dump_delay(delay_cal.tx_dq[0].avg); } /* Write manual settings */ - pci_mod_config8(MCU, 0x75, 0, 0x01); + pci_or_config8(MCU, 0x75, 0x01); vx900_delay_calib_mode_select(CALIB_TxDQS, CALIB_MANUAL); vx900_write_0x78_0x7f(delay_cal.tx_dqs[0].avg); vx900_delay_calib_mode_select(CALIB_TxDQ, CALIB_MANUAL); @@ -1538,7 +1538,7 @@ * all devices and know pci_tolm. */ tolm_mb = MIN(ramsize_mb, TOLM_3_5G >> 20); u16 reg_tolm = (tolm_mb << 4) & 0xfff0; - pci_mod_config16(MCU, 0x84, 0xfff0, reg_tolm); + pci_update_config16(MCU, 0x84, (u16)~0xfff0, reg_tolm); printram("Initialized %u virtual ranks, with a total size of %u MB\n", (int)vrank, ramsize_mb); @@ -1609,10 +1609,10 @@ /* FIXME: Why are we doing this? */ /* Tri-state MCSi# when rank is in self-refresh */ - pci_mod_config8(MCU, 0x99, 0, 0x0f); + pci_or_config8(MCU, 0x99, 0x0f); /* Enable paging mode and 8 page registers */ - pci_mod_config8(MCU, 0x69, 0, 0xe5); + pci_or_config8(MCU, 0x69, 0xe5); /* Enable automatic triggering of short ZQ calibration */ pci_write_config8(MCU, 0xc8, 0x80); diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 4df0053..d6f4c83 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -178,11 +178,11 @@ static void vx900_native_ide_mode(struct device *dev) { /* Disable subclass write protect */ - pci_mod_config8(dev, 0x45, 1 << 7, 0); + pci_update_config8(dev, 0x45, (u8)~(1 << 7), 0); /* Change the device class to IDE */ pci_write_config16(dev, PCI_CLASS_DEVICE, PCI_CLASS_STORAGE_IDE); /* Re-enable subclass write protect */ - pci_mod_config8(dev, 0x45, 0, 1 << 7); + pci_or_config8(dev, 0x45, 1 << 7); /* Put it in native IDE mode */ pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); } @@ -190,20 +190,20 @@ static void vx900_sata_init(struct device *dev) { /* Enable SATA primary channel IO access */ - pci_mod_config8(dev, 0x40, 0, 1 << 1); + pci_or_config8(dev, 0x40, 1 << 1); /* Just SATA, so it makes sense to be in native SATA mode */ vx900_native_ide_mode(dev); /* TP Layer Idle at least 20us before the Following Command */ - pci_mod_config8(dev, 0x53, 0, 1 << 7); + pci_or_config8(dev, 0x53, 1 << 7); /* Resend COMRESET When Recovering SATA Gen2 Device Error */ - pci_mod_config8(dev, 0x62, 1 << 1, 1 << 7); + pci_update_config8(dev, 0x62, ~(1 << 1), 1 << 7); /* Fix "PMP Device Can't Detect HDD Normally" (VIA Porting Guide) * SATA device detection will not work unless we clear these bits. * Without doing this, SeaBIOS (and potentially other payloads) will * timeout when detecting SATA devices */ - pci_mod_config8(dev, 0x89, (1 << 3) | (1 << 6), 0); + pci_update_config8(dev, 0x89, ~(1 << 3) | (1 << 6), 0); /* 12.7 Two Software Resets May Affect the System * When the software does the second reset before the first reset @@ -216,7 +216,7 @@ * second one anymore. The BSY bit of slave port would be always 1 after * the second software reset issues. BIOS should set the following * bit to avoid this issue. */ - pci_mod_config8(dev, 0x80, 0, 1 << 6); + pci_or_config8(dev, 0x80, 1 << 6); /* We need to set the EPHY values before doing anything with the link */ sata_phy_config ephy; @@ -243,7 +243,7 @@ pci_write_config32(dev, 0xac, 0xffffffff); /* Start OOB link negotiation sequence */ - pci_mod_config8(dev, 0xb9, 0, 3 << 4); + pci_or_config8(dev, 0xb9, 3 << 4); /* FIXME: From now on, we are just doing DEBUG stuff * Wait until PHY communication is enabled */ diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index c2b4a48..734defc 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -93,7 +93,7 @@ /* Second register of the base. * Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */ base_val = (((uintptr_t)config->base) >> 16) & 0xf; - pci_mod_config8(dev, 0x40, 0, base_val | (1 << 7) | (1 << 5)); + pci_or_config8(dev, 0x40, base_val | (1 << 7) | (1 << 5)); } /* diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index a2a360a..29fc472 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -43,20 +43,8 @@ #ifdef __SIMPLE_DEVICE__ void dump_pci_device(pci_devfn_t dev); -void pci_mod_config8(pci_devfn_t dev, unsigned int where, - uint8_t clr_mask, uint8_t set_mask); -void pci_mod_config16(pci_devfn_t dev, unsigned int where, - uint16_t clr_mask, uint16_t set_mask); -void pci_mod_config32(pci_devfn_t dev, unsigned int where, - uint32_t clr_mask, uint32_t set_mask); #else void dump_pci_device(struct device *dev); -void pci_mod_config8(struct device *dev, unsigned int where, - uint8_t clr_mask, uint8_t set_mask); -void pci_mod_config16(struct device *dev, unsigned int where, - uint16_t clr_mask, uint16_t set_mask); -void pci_mod_config32(struct device *dev, unsigned int where, - uint32_t clr_mask, uint32_t set_mask); #endif #endif /* __VX900_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae64e9b635b3759e4cffc4bbdf029411a4e0f42 Gerrit-Change-Number: 31272 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: arch/arm64: Add PCI config support in romstage
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31307 ) Change subject: arch/arm64: Add PCI config support in romstage ...................................................................... Patch Set 2: Patrick, can you do some simple PCI config register read test? -- To view, visit https://review.coreboot.org/c/coreboot/+/31307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133 Gerrit-Change-Number: 31307 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Feb 2019 18:17:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: arch/arm64: Make ARM64 specific options depend on select ARCH_ARM64
by Arthur Heymans (Code Review) 10 Feb '19

10 Feb '19

Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31315 to look at the new patch set (#2). Change subject: arch/arm64: Make ARM64 specific options depend on select ARCH_ARM64 ...................................................................... arch/arm64: Make ARM64 specific options depend on select ARCH_ARM64 Also don't define the default as this result in spurious lines in the .config. Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm64/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8183/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/rockchip/rk3399/Kconfig 7 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31315/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31 Gerrit-Change-Number: 31315 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/amd/common: Remove redundant ACPI S3 test
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27276 to look at the new patch set (#4). Change subject: soc/amd/common: Remove redundant ACPI S3 test ...................................................................... soc/amd/common: Remove redundant ACPI S3 test Possible allowance to do wakeup is already evaluated early in romstage, so these tests are redundant. Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/chip.c 3 files changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27276/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/27276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Gerrit-Change-Number: 27276 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27277 to look at the new patch set (#3). Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... soc/amd/common: Fix AmdLateRunApTask() Third parameter ConfigPtr of the callout is of type AP_EXE_PARAMS and needs to be passed back to AGESA with AmdLateRunApTask() call. Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/def_callouts.c 3 files changed, 6 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/27277/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/amd/common: Remove redundant ACPI S3 test
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27276 to look at the new patch set (#3). Change subject: soc/amd/common: Remove redundant ACPI S3 test ...................................................................... soc/amd/common: Remove redundant ACPI S3 test Possible allowance to do wakeup is already evaluated early in romstage, so these tests are redundant. To keep linker happy, always build in S3 support code. Besides, the condition of HAVE_ACPI_RESUME=y for this is incorrect to keep under common/ since non-volatile data storage is also part of fast raminit path utilising MRC CACHE. Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/chip.c 3 files changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27276/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/27276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Gerrit-Change-Number: 27276 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: src/mainboard/lenovo/g505s/Kconfig: disable DRIVERS_INTEL_WIFI by def...
by mikeb mikeb (Code Review) 10 Feb '19

10 Feb '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31225 to review the following change. Change subject: src/mainboard/lenovo/g505s/Kconfig: disable DRIVERS_INTEL_WIFI by default ...................................................................... src/mainboard/lenovo/g505s/Kconfig: disable DRIVERS_INTEL_WIFI by default There were no G505S shipped with pre-installed Intel PCI-e WiFi adapters, almost all such adapters (except Intel 135) could not be installed under proprietary UEFI because of a whitelist, and I am not aware of anyone who installed them after upgrading to coreboot - maybe because Atheros ath9k have a much better software freedom status and are the preferred choice. Disable DRIVERS_INTEL_WIFI option by default for this G505S laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I73c3c2587690dca653dd1b2a8d6ee9ff8b769ad4 --- M src/mainboard/lenovo/g505s/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31225/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..d0701a7 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -55,4 +55,8 @@ string default "1002,990b" +config DRIVERS_INTEL_WIFI + bool + default n + endif # BOARD_LENOVO_G505S -- To view, visit https://review.coreboot.org/c/coreboot/+/31225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c3c2587690dca653dd1b2a8d6ee9ff8b769ad4 Gerrit-Change-Number: 31225 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 16

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019