coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: soc/intel/icelake: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 10 Feb '19

10 Feb '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30515 ) Change subject: soc/intel/icelake: Don't use CAR_GLOBAL ...................................................................... Patch Set 4: > Patch Set 2: > > Arthur, can you send RFC on the mailing list about this. > > I would not mind starting to remove CAR_GLOBAL and all car_get/set_var() stuff, from the platform codes, starting with the latest Intel one so that these are no longer copied around further. my idea is to get rid of it in our tree. CAR_GLOBAL is an empty macro if CONFIG_NO_CAR_GLOBAL_MIGRATION is set, so in the platform code it should even result in identical binaries with BUILD_TIMELESS=1. On this platform it is the case. -- To view, visit https://review.coreboot.org/c/coreboot/+/30515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Gerrit-Change-Number: 30515 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Feb 2019 10:57:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: cpu/intel/car/*/cache_as_ram.S: Add brackets around operand
by Arthur Heymans (Code Review) 10 Feb '19

10 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31291 Change subject: cpu/intel/car/*/cache_as_ram.S: Add brackets around operand ...................................................................... cpu/intel/car/*/cache_as_ram.S: Add brackets around operand Change-Id: I644c38c9b8383db25a970dc7a5ec8765980298ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31291/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index f32b3dc..7788a2d 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -118,7 +118,7 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index f84e855..9d50582 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -304,7 +304,7 @@ /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx -- To view, visit https://review.coreboot.org/c/coreboot/+/31291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I644c38c9b8383db25a970dc7a5ec8765980298ed Gerrit-Change-Number: 31291 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: soc/intel/icelake: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 10 Feb '19

10 Feb '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30515 ) Change subject: soc/intel/icelake: Don't use CAR_GLOBAL ...................................................................... Patch Set 4: > Patch Set 2: > > Arthur, can you send RFC on the mailing list about this. > > I would not mind starting to remove CAR_GLOBAL and all car_get/set_var() stuff, from the platform codes, starting with the latest Intel one so that these are no longer copied around further. my idea is to get rid of it in our tree. CAR_GLOBAL is an empty macro if CONFIG_NO_CAR_GLOBAL_MIGRATION is set, so in the platform code it even results in identical binaries with BUILD_TIMELESS=1. -- To view, visit https://review.coreboot.org/c/coreboot/+/30515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Gerrit-Change-Number: 30515 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Feb 2019 10:51:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: sb/amd/sb800: Drop comments about pci_locate_device()
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31301 Change subject: sb/amd/sb800: Drop comments about pci_locate_device() ...................................................................... sb/amd/sb800: Drop comments about pci_locate_device() Change-Id: I28a32d5c6dee792b6882e7ff45be6339016ad6ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/sb800/early_setup.c M src/southbridge/amd/sb800/sata.c 2 files changed, 16 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31301/1 diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index c9b879a..d7a6b88 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -78,7 +78,7 @@ /* if (rev != 0) return rev; */ - dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); + dev = PCI_DEV(0, 0x14, 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\n"); @@ -124,8 +124,7 @@ u8 reg8; pci_devfn_t dev; - //dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ - dev = PCI_DEV(0, 0x14, 0); + dev = PCI_DEV(0, 0x14, 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! * This bit has no meaning if debug strap is not enabled. So if the * board keeps rebooting and the code fails to reach here, we could @@ -139,7 +138,7 @@ reg8 |= 1 << 0; pmio_write(0xEC, reg8); - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ /* Decode port 0x3f8-0x3ff (Serial 0) */ //#warning Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); @@ -168,7 +167,7 @@ pci_devfn_t dev; /* Find the device. */ - dev = PCI_DEV(bus, 0x14, 0);//pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); + dev = PCI_DEV(bus, 0x14, 0); return (dev >> 15) & 0x1f; } @@ -240,7 +239,7 @@ pci_devfn_t dev; /* P2P Bridge */ - dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); + dev = PCI_DEV(0, 0x14, 4); /* Chip Control: Enable subtractive decoding */ byte = pci_read_config8(dev, 0x40); @@ -272,7 +271,7 @@ pci_write_config8(dev, 0x04, byte); /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ @@ -351,7 +350,7 @@ pmio_write(0xEC, byte); /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); @@ -366,7 +365,7 @@ printk(BIOS_INFO, "sb800_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ printk(BIOS_INFO, "sb800_devices_por_init(): SMBus Device, BDF:0-20-0\n"); - dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); + dev = PCI_DEV(0, 0x14, 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\n"); @@ -434,7 +433,7 @@ /* IDE Device, BDF:0-20-1 */ printk(BIOS_INFO, "sb800_devices_por_init(): IDE Device, BDF:0-20-1\n"); - dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0); + dev = PCI_DEV(0, 0x14, 1); /* Disable prefetch */ byte = pci_read_config8(dev, 0x63); byte |= 0x1; @@ -442,7 +441,7 @@ /* LPC Device, BDF:0-20-3 */ printk(BIOS_INFO, "sb800_devices_por_init(): LPC Device, BDF:0-20-3\n"); - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3); /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); @@ -461,7 +460,7 @@ /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, */ printk(BIOS_INFO, "sb800_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); - dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); + dev = PCI_DEV(0, 0x14, 4); /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); @@ -478,7 +477,7 @@ /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ printk(BIOS_INFO, "sb800_devices_por_init(): SATA Device, BDF:0-18-0\n"); - dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0); + dev = PCI_DEV(0, 0x11, 0); /*PHY Global Control*/ pci_write_config16(dev, 0x86, 0x2C00); @@ -546,7 +545,7 @@ u8 byte; /* SMBus Device, BDF:0-20-0 */ - dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); + dev = PCI_DEV(0, 0x14, 0); /* Enable watchdog decode timer */ byte = pci_read_config8(dev, 0x41); byte |= (1 << 3); @@ -559,7 +558,7 @@ pmio_write(0xF0, byte); /* IDE Device, BDF:0-20-1 */ - dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0); + dev = PCI_DEV(0, 0x14, 1); /* Enable IDE Explicit prefetch, 0x63[0] clear */ byte = pci_read_config8(dev, 0x63); byte &= 0xfe; @@ -569,7 +568,7 @@ /* The code below is ported from old chipset. It is not * Mentioned in RPR. But I keep them. The registers and the * comments are compatible. */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + dev = PCI_DEV(0, 0x14, 3); /* Enabling LPC DMA function. */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); @@ -584,7 +583,7 @@ pci_write_config8(dev, 0x78, byte); /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0); + dev = PCI_DEV(0, 0x11, 0); /* rpr7.12 SATA MSI and D3 Power State Capability. */ byte = pci_read_config8(dev, 0x40); byte |= 1 << 0; diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index acb899f..9ac3794 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -87,7 +87,6 @@ struct device *sm_dev; /* SATA SMBus Disable */ - /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = pcidev_on_root(0x14, 0); /* get rev_id */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a32d5c6dee792b6882e7ff45be6339016ad6ef Gerrit-Change-Number: 31301 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: arch/x86: Drop some ROMCC remains
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31293 Change subject: arch/x86: Drop some ROMCC remains ...................................................................... arch/x86: Drop some ROMCC remains Change-Id: I62da8d0461774db8256e82deae0d5fe075f3faed Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/io.h 1 file changed, 0 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31293/1 diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 4050a47..f62dc6c 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -203,35 +203,6 @@ } #endif -/* Conflicts with definition in lib.h */ -#if defined(__ROMCC__) -static inline int log2(u32 value) -{ - unsigned int r = 0; - __asm__ volatile ( - "bsrl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; - -} - -static inline int __ffs(u32 value) -{ - unsigned int r = 0; - __asm__ volatile ( - "bsfl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; - -} -#endif - #ifdef __SIMPLE_DEVICE__ #define PCI_DEV(SEGBUS, DEV, FN) ( \ -- To view, visit https://review.coreboot.org/c/coreboot/+/31293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62da8d0461774db8256e82deae0d5fe075f3faed Gerrit-Change-Number: 31293 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: soc/intel/icelake: Don't use CAR_GLOBAL
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30515 ) Change subject: soc/intel/icelake: Don't use CAR_GLOBAL ...................................................................... Patch Set 4: Code-Review+1 Arthur, I think this change is worth posting RFC to mailing list. -- To view, visit https://review.coreboot.org/c/coreboot/+/30515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Gerrit-Change-Number: 30515 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Feb 2019 09:20:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/sandybridge: Use pcidev_on_root()
by Kyösti Mälkki (Code Review) 10 Feb '19

10 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31292 Change subject: nb/intel/sandybridge: Use pcidev_on_root() ...................................................................... nb/intel/sandybridge: Use pcidev_on_root() Change-Id: I959dfd1c10bc1ab85c6392e0090b022934468770 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/sandybridge/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/31292/1 diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 48be666..c274318 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -71,7 +71,7 @@ { const u32 base_mask = ~(u32)(MiB - 1); - struct device *const host = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *const host = pcidev_on_root(0, 0); if (!host) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I959dfd1c10bc1ab85c6392e0090b022934468770 Gerrit-Change-Number: 31292 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: soc/intel/icelake: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 10 Feb '19

10 Feb '19

Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30515 to look at the new patch set (#4). Change subject: soc/intel/icelake: Don't use CAR_GLOBAL ...................................................................... soc/intel/icelake: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/icelake/romstage/romstage.c 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30515/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Gerrit-Change-Number: 30515 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 10 Feb '19

10 Feb '19

Hello Aaron Durbin, Patrick Rudolph, Duncan Laurie, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30514 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Don't use CAR_GLOBAL ...................................................................... soc/intel/cannonlake: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/sarien/chromeos.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/cannonlake/romstage/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30514/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Gerrit-Change-Number: 30514 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: security/vboot: Add measured boot mode
by build bot (Jenkins) (Code Review) 10 Feb '19

10 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 47: (7 comments) https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c@98 PS47, Line 98: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c@1… PS47, Line 104: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c@2… PS47, Line 281: return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); line over 80 characters https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c@3… PS47, Line 308: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) line over 80 characters https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c@3… PS47, Line 319: if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && !(ctx.flags | VB2_CONTEXT_S3_RESUME)) { line over 80 characters https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c@3… PS47, Line 324: if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) line over 80 characters https://review.coreboot.org/#/c/29547/47/src/security/vboot/vboot_logic.c@3… PS47, Line 333: if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 47 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Feb 2019 00:12:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019