coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: mb/{asrock,intel,kontron}: Include missing <arch/acpi.h>
by HAOUAS Elyes (Code Review) 08 Feb '19

08 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31267 Change subject: mb/{asrock,intel,kontron}: Include missing <arch/acpi.h> ...................................................................... mb/{asrock,intel,kontron}: Include missing <arch/acpi.h> Also includes lines sorted Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/ktqm77/romstage.c 4 files changed, 34 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/31267/1 diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 0605ef1..ab6b1d8 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -15,17 +15,18 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> -#include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <superio/nuvoton/nct6776/nct6776.h> -#include <superio/winbond/w83627dhg/w83627dhg.h> -#include <superio/winbond/common/winbond.h> -#include <superio/nuvoton/common/nuvoton.h> +#include <cpu/x86/bist.h> #include <northbridge/intel/x4x/iomap.h> +#include <northbridge/intel/x4x/x4x.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index abe3b67..7f84b6a 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -15,18 +15,19 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> -#include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <superio/winbond/w83627dhg/w83627dhg.h> -#include <superio/winbond/common/winbond.h> -#include <northbridge/intel/x4x/iomap.h> -#include <halt.h> #include <cpu/intel/speedstep.h> +#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> +#include <northbridge/intel/x4x/iomap.h> +#include <northbridge/intel/x4x/x4x.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 7038538..2caf5ec 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -15,15 +15,16 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> -#include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <superio/winbond/w83627dhg/w83627dhg.h> -#include <superio/winbond/common/winbond.h> +#include <cpu/x86/bist.h> #include <northbridge/intel/x4x/iomap.h> +#include <northbridge/intel/x4x/x4x.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index cd6f3b9..c4d26d3 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -16,18 +16,20 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> #include <arch/acpi.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit.h> +#include <arch/io.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <halt.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <cpu/x86/msr.h> -#include <halt.h> #include <superio/winbond/common/winbond.h> +#include <timestamp.h> + void pch_enable_lpc(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729 Gerrit-Change-Number: 31267 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: drivers/gpio_keys: Remove redundant is_wakeup_source flag
by Karthik Ramasubramanian (Code Review) 08 Feb '19

08 Feb '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31258 to review the following change. Change subject: drivers/gpio_keys: Remove redundant is_wakeup_source flag ...................................................................... drivers/gpio_keys: Remove redundant is_wakeup_source flag "is_wakeup_source" flag is used to indicate if the concerned device can trigger a wakeup. This flag is redundant with the "wake" GPE event definition. So remove the redundant flag and use the "wake" GPE event to mark the wakeup source. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source in SSDT if wake GPE is configured. Ensure that the system can suspend and the device acts as a wakeup source Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/generic/gpio_keys/chip.h M src/drivers/generic/gpio_keys/gpio_keys.c M src/mainboard/google/octopus/variants/bobba/overridetree.cb 3 files changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31258/1 diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 9d33b4f..08acfeb 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -50,8 +50,6 @@ uint32_t linux_input_type; /* Descriptive name of the key */ const char *label; - /* Can this key wake-up the system? */ - bool is_wakeup_source; /* Wake GPE */ unsigned int wake; /* Trigger for Wakeup Event Action as defined in EV_ACT_* enum */ diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index f9869d6..6e18a8a 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -40,10 +40,8 @@ key->linux_input_type); if (key->label) acpi_dp_add_string(dsd, "label", key->label); - if (key->is_wakeup_source) - acpi_dp_add_integer(dsd, "wakeup-source", - key->is_wakeup_source); if (key->wake) { + acpi_dp_add_integer(dsd, "wakeup-source", 1); acpigen_write_PRW(key->wake, 3); acpi_dp_add_integer(dsd, "wakeup-event-action", key->wakeup_event_action); diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index cd26fab..0230a29 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -104,7 +104,6 @@ register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" register "key.label" = ""pen_eject"" - register "key.is_wakeup_source" = "1" register "key.wake" = "GPE0_DW2_04" register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" device generic 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/31258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa Gerrit-Change-Number: 31258 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mb/*/*/romstage: curly braces after the function definition
by Peter Lemenkov (Code Review) 08 Feb '19

08 Feb '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31268 Change subject: mb/*/*/romstage: curly braces after the function definition ...................................................................... mb/*/*/romstage: curly braces after the function definition See Documentation/coding_style.md, specifically "Placing Braces and Spaces" section. Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/x230/romstage.c 9 files changed, 24 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31268/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 543e765..dbb015d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -86,7 +86,8 @@ { 1, 5, 6 }, }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd (&spd[0], 0x50, id_only); read_spd (&spd[1], 0x51, id_only); read_spd (&spd[2], 0x52, id_only); diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 1ca6551..89f475e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -87,14 +87,16 @@ }; /* FIXME: This board only has two DIMM slots! */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd (&spd[0], 0x50, id_only); read_spd (&spd[1], 0x51, id_only); read_spd (&spd[2], 0x52, id_only); read_spd (&spd[3], 0x53, id_only); } -void mainboard_early_init(int s3resume) { +void mainboard_early_init(int s3resume) +{ } void mainboard_config_superio(void) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index bfee526..0166997 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -116,12 +116,14 @@ { 0, 0, -1 }, /* P13: Empty */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x52, id_only); } -void mainboard_early_init(int s3resume) { +void mainboard_early_init(int s3resume) +{ } void mainboard_config_superio(void) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index dab4995..91f8297 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -195,7 +195,8 @@ { 0, 0, -1 }, /* P13: Empty */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ memcpy(&spd[0], locate_spd(), 128); } diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index dd21dcd..186d16d 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -169,7 +169,8 @@ { 0, 0, -1 }, /* P13: Empty */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x52, id_only); } diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index d5b6174..b43a9b0 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -159,7 +159,8 @@ { 1, 0, 5 }, /* P13: Back port (OC5) */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x52, id_only); } diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index cd6f3b9..9083764 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -156,7 +156,8 @@ { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x52, id_only); } diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 49a9b4e..5754a6d 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -85,7 +85,8 @@ { 1, 1, -1 }, /* P13: camera (LCD), no OC */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index ba8baa8..6a47ac0 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -63,12 +63,14 @@ { 1, 1, -1 }, /* P13: webcam, no OC */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ read_spd (&spd[0], 0x50, id_only); read_spd (&spd[2], 0x51, id_only); } -void mainboard_early_init(int s3resume) { +void mainboard_early_init(int s3resume) +{ } void mainboard_config_superio(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113 Gerrit-Change-Number: 31268 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: drivers/keyboard: Fix spelling of *interface*
by Paul Menzel (Code Review) 08 Feb '19

08 Feb '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31286 Change subject: drivers/keyboard: Fix spelling of *interface* ...................................................................... drivers/keyboard: Fix spelling of *interface* `git grep iterface` shows that these are the only two occurrences. Change-Id: I838a60c95c5d0fc3dee902f0b72761dd60c36221 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/pc80/pc/keyboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31286/1 diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c index 415dbd1..3849e73 100644 --- a/src/drivers/pc80/pc/keyboard.c +++ b/src/drivers/pc80/pc/keyboard.c @@ -259,7 +259,7 @@ /* Run a keyboard controller self-test */ err = kbc_self_test(probe_aux, &aux_dev_detected); - /* Ignore iterface failure as it's non-fatal. */ + /* Ignore interface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) return 0; @@ -370,7 +370,7 @@ /* Run a keyboard controller self-test */ err = kbc_self_test(0, NULL); - /* Ignore iterface failure as it's non-fatal. */ + /* Ignore interface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/31286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I838a60c95c5d0fc3dee902f0b72761dd60c36221 Gerrit-Change-Number: 31286 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: cheza: configure gpios and gcc clocks for sound
by Paul Menzel (Code Review) 08 Feb '19

08 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31083 ) Change subject: cheza: configure gpios and gcc clocks for sound ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/#/c/31083/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@2 PS1, Line 2: RajendraBabu Add a space between the names? https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@7 PS1, Line 7: cheza: configure gpios and gcc clocks for sound Use the SoC name as prefix? https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@9 PS1, Line 9: Configure mi2s, codec reset gpios and enable : GCC LPASS clocks required for audio support. Please use the fully allowed text width. https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@11 PS1, Line 11: Tested how? https://review.coreboot.org/#/c/31083/1//COMMIT_MSG@14 PS1, Line 14: kumar Capital K? -- To view, visit https://review.coreboot.org/c/coreboot/+/31083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I130c4a0df88d0825debfa8e5c22a31f30be70df6 Gerrit-Change-Number: 31083 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 08 Feb 2019 09:55:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 08 Feb '19

08 Feb '19

1 0

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Frans Hendriks (Code Review) 08 Feb '19

08 Feb '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30414 to look at the new patch set (#14). Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... mainboard/facebook/fbg1701: Do initial mainboard commit Create Facebook FBG-1701 coreboot implementation coreboot implementation is prepared for Bootblock, measured boot and verified boot support. These features are default disabled. This Braswell implementation is based on Intel Strago. Additional modifiiciation included: - Move Winbond defines to include - Add SMBus support for Braswell BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A Documentation/mainboard/facebook/fbg1701.md M Documentation/mainboard/index.md A src/drivers/spi/spi_winbond.h M src/drivers/spi/winbond.c A src/mainboard/facebook/fbg1701/Kconfig A src/mainboard/facebook/fbg1701/Kconfig.name A src/mainboard/facebook/fbg1701/Makefile.inc A src/mainboard/facebook/fbg1701/acpi/dptf.asl A src/mainboard/facebook/fbg1701/acpi/ec.asl A src/mainboard/facebook/fbg1701/acpi/mainboard.asl A src/mainboard/facebook/fbg1701/acpi/sleepstates.asl A src/mainboard/facebook/fbg1701/acpi/superio.asl A src/mainboard/facebook/fbg1701/acpi_tables.c A src/mainboard/facebook/fbg1701/board_info.txt A src/mainboard/facebook/fbg1701/board_mboot.c A src/mainboard/facebook/fbg1701/board_verified_boot.c A src/mainboard/facebook/fbg1701/board_verified_boot.h A src/mainboard/facebook/fbg1701/bootblock.c A src/mainboard/facebook/fbg1701/cmos.layout A src/mainboard/facebook/fbg1701/com_init.c A src/mainboard/facebook/fbg1701/devicetree.cb A src/mainboard/facebook/fbg1701/dsdt.asl A src/mainboard/facebook/fbg1701/fadt.c A src/mainboard/facebook/fbg1701/fmap.fmd A src/mainboard/facebook/fbg1701/gpio.c A src/mainboard/facebook/fbg1701/hda_verb.c A src/mainboard/facebook/fbg1701/irqroute.c A src/mainboard/facebook/fbg1701/irqroute.h A src/mainboard/facebook/fbg1701/logo.c A src/mainboard/facebook/fbg1701/mainboard.c A src/mainboard/facebook/fbg1701/mainboard.h A src/mainboard/facebook/fbg1701/manifest.h A src/mainboard/facebook/fbg1701/onboard.h A src/mainboard/facebook/fbg1701/ramstage.c A src/mainboard/facebook/fbg1701/romstage.c A src/mainboard/facebook/fbg1701/smihandler.c A src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/facebook/fbg1701/w25q64.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/include/soc/pci_devs.h A src/soc/intel/braswell/include/soc/smbus.h A src/soc/intel/braswell/smbus.c 42 files changed, 3,057 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30414/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 14 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Add support to disable PCIe WLAN dynamically
by Maulik V Vaghela (Code Review) 08 Feb '19

08 Feb '19

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30611 Change subject: soc/intel/cannonlake: Add support to disable PCIe WLAN dynamically ...................................................................... soc/intel/cannonlake: Add support to disable PCIe WLAN dynamically Ideally we should disable PCIe WLAN if CNVi is enabled and out of reset. This code adds support to achieve this. SoC code will check if CNVi is up or not and if is enabled, it'll disable PCIe WLAN. PCI WLAN device and function are board dependent and mainboard must implement function which returns PCI_DEVFN for WLAN. BUG=none BRANCH=none TEST=none Change-Id: Ief1896b3d915018edca136c26f4e834e0c9003ac Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30611/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 8166dea..4225471 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -17,6 +17,8 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/xdci.h> @@ -25,6 +27,42 @@ #include <soc/ramstage.h> #include <string.h> +static bool is_cnvi_held_in_reset(void) +{ + struct device *dev = dev_find_slot(0, PCH_DEVFN_CNVI); + uint32_t reg = pci_read_config32(dev, PCI_VENDOR_ID); + + /* + * If vendor/device ID for CNVi reads as 0xffffffff, then it is safe to + * assume that it is being held in reset. + */ + if (reg == 0xffffffff) + return true; + + return false; +} + +/* + * Check if CNVi PCI device is released from reset. If yes, then the system is + * booting with CNVi module. In this case, the PCIe device for WiFi needs to + * be disabled. If CNVi device is held in reset, then disable it. + */ +static void wifi_device_update(void) +{ + struct device *dev; + unsigned int devfn; + + if (is_cnvi_held_in_reset()) + devfn = PCH_DEVFN_CNVI; + else + devfn = mainboard_get_wifi_device(); + + if (devfn != 0) { + dev = dev_find_slot(0, devfn); + dev->enabled = 0; + } +} + static void parse_devicetree(FSP_S_CONFIG *params) { struct device *dev = SA_DEV_ROOT; @@ -86,6 +124,7 @@ } mainboard_silicon_init_params(params); + wifi_device_update (); /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; @@ -236,3 +275,8 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +__weak uint32_t mainboard_get_wifi_device(void) +{ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1896b3d915018edca136c26f4e834e0c9003ac Gerrit-Change-Number: 30611 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
by Frans Hendriks (Code Review) 08 Feb '19

08 Feb '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig File src/soc/intel/braswell/Kconfig: https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig@137 PS5, Line 137: : config ENABLE_SERIRQ : bool "Enable Serial IRQ" : default n : help : Enable Serial IRQ : : config SERIRQ_CONTINUOUS_MODE : bool "Serial IRQ continuous mode" : default n : depends on ENABLE_SERIRQ : help : Enable Serial IRQ continuous mode > 'Actual boards' use the 'old' code which does not enable the serial IRQ. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Feb 2019 09:34:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 08 Feb '19

08 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 13: (5 comments) https://review.coreboot.org/#/c/30414/13/src/drivers/spi/spi_winbond.h File src/drivers/spi/spi_winbond.h: https://review.coreboot.org/#/c/30414/13/src/drivers/spi/spi_winbond.h@34 PS13, Line 34: #define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ line over 80 characters https://review.coreboot.org/#/c/30414/13/src/mainboard/facebook/fbg1701/irq… File src/mainboard/facebook/fbg1701/irqroute.h: https://review.coreboot.org/#/c/30414/13/src/mainboard/facebook/fbg1701/irq… PS13, Line 40: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/30414/13/src/mainboard/facebook/fbg1701/irq… PS13, Line 62: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/30414/13/src/mainboard/facebook/fbg1701/w25… File src/mainboard/facebook/fbg1701/w25q64.c: https://review.coreboot.org/#/c/30414/13/src/mainboard/facebook/fbg1701/w25… PS13, Line 28: #define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ please, no space before tabs https://review.coreboot.org/#/c/30414/13/src/mainboard/facebook/fbg1701/w25… PS13, Line 49: #define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 13 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 08 Feb 2019 09:26:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019