coreboot-gerrit February 2019

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 07 Feb '19

07 Feb '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@141 PS2, Line 141: .pcr_port_id = 0xc5, > Where can I find this id? I couldn't find it in the datasheets. Found it in pcr_ids.h. https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@239 PS2, Line 239: .pcr_port_id = 0xc4, > Same here. Done https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@303 PS2, Line 303: .pcr_port_id = 0xc0, > Same here. Done https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@371 PS2, Line 371: .pcr_port_id = 0xc7, > Same here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Feb 2019 12:23:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by build bot (Jenkins) (Code Review) 07 Feb '19

07 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 3: (24 comments) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@108 PS3, Line 108: "*GPIO_72", "GP_CAMERASB10","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@109 PS3, Line 109: "*GPIO_73", "GP_CAMERASB11","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@116 PS3, Line 116: "JTAGX" , "*JTAGX", "n/a", "n/a", "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@123 PS3, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@123 PS3, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@167 PS3, Line 167: "PMC_SPI_FS2", "*PMC_SPI_FS2", "FST_SPI_CS2_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@181 PS3, Line 181: "*GPIO_74", "AVS_I2S1_MCLK" , "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@186 PS3, Line 186: "*GPIO_79", "AVS_DMIC_CLK_A1", "AVS_I2S4_BCLK","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@187 PS3, Line 187: "*GPIO_80", "AVS_DMIC_CLK_B1", "AVS_I2S4_WS_SYNC","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@191 PS3, Line 191: "*GPIO_84", "AVS_I2S2_MCLK", "AVS_HDA_RST_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@319 PS3, Line 319: "*GPIO_134", "LPSS_I2C5_SDA","ISH_I2C0_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@320 PS3, Line 320: "*GPIO_135", "LPSS_I2C5_SCL","ISH_I2C0_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@321 PS3, Line 321: "*GPIO_136", "LPSS_I2C6_SDA","ISH_I2C1_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@322 PS3, Line 322: "*GPIO_137", "LPSS_I2C6_SCL","ISH_I2C1_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@323 PS3, Line 323: "*GPIO_138", "LPSS_I2C7_SDA","ISH_I2C2_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@324 PS3, Line 324: "*GPIO_139", "LPSS_I2C7_SCL","ISH_I2C2_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@335 PS3, Line 335: "GPIO_209", "*PCIE_CLKREQ0_N", "MODEM_CLK_REQ","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@339 PS3, Line 339: "OSC_CLK_OUT_0","*OSC_CLK_OUT_0", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@340 PS3, Line 340: "OSC_CLK_OUT_1","*OSC_CLK_OUT_1", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@341 PS3, Line 341: "OSC_CLK_OUT_2","*OSC_CLK_OUT_2", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@342 PS3, Line 342: "OSC_CLK_OUT_3","*OSC_CLK_OUT_3", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@343 PS3, Line 343: "OSC_CLK_OUT_4","*OSC_CLK_OUT_4", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@344 PS3, Line 344: "*PMU_AC_PRESENT","PMU_AC_PRESENT", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/3/util/inteltool/gpio_groups.c@353 PS3, Line 353: "*PMU_WAKE_B", "PMU_WAKE_B/EMMC_PWR_EN_N","n/a", "n/a", space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Feb 2019 12:10:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 07 Feb '19

07 Feb '19

Felix Singer has uploaded a new patch set (#3) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c 2 files changed, 353 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29897/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 07 Feb '19

07 Feb '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@141 PS2, Line 141: .pcr_port_id = 0xc5, Where can I find this id? I couldn't find it in the datasheets. https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@239 PS2, Line 239: .pcr_port_id = 0xc4, Same here. https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@303 PS2, Line 303: .pcr_port_id = 0xc0, Same here. https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@371 PS2, Line 371: .pcr_port_id = 0xc7, Same here. -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Feb 2019 12:07:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 07 Feb '19

07 Feb '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@119 PS2, Line 119: "CNV_BRI_DT", "*GPIO_216", "n/a", "n/a", "n/a", "n/a", How did you find out that this pad belongs to GPIO_216 from the GPIO multiplexing table (p. 50)? The pad name doesn't appear anywhere. https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@120 PS2, Line 120: "CNV_BRI_RSP", "*GPIO_217", "n/a", "n/a", "n/a", "n/a", Same here https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@121 PS2, Line 121: "CNV_RGI_DT", "*GPIO_218", "n/a", "n/a", "n/a", "n/a", Same here -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Feb 2019 10:50:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
by Frans Hendriks (Code Review) 07 Feb '19

07 Feb '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig File src/soc/intel/braswell/Kconfig: https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig@137 PS5, Line 137: : config ENABLE_SERIRQ : bool "Enable Serial IRQ" : default n : help : Enable Serial IRQ : : config SERIRQ_CONTINUOUS_MODE : bool "Serial IRQ continuous mode" : default n : depends on ENABLE_SERIRQ : help : Enable Serial IRQ continuous mode > are there boards which use this for which you'd want to disable it conditionally? If not, setting it […] 'Actual boards' use the 'old' code which does not enable the serial IRQ. I'm not sure if the serial IRQ is expected to be disabled or enabled for these board. -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Feb 2019 10:39:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/hda.c: Configure HDA codecs
by Frans Hendriks (Code Review) 07 Feb '19

07 Feb '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 ) Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs ...................................................................... Patch Set 8: > Patch Set 8: > > since LPE audio is the norm on braswell devices, might it be better to set a Kconfig for HDA audio and conditionally include hda_verb.c if set? That way you don't need to modify existing boards which don't use HDA audio. For sure Kconfig can be used. I'm not sure if the PCI configuration of the HDA will changefor boards which have 'HDA disabled' in Kconfig. It will remove the read/set/enable of the HDA controller. -- To view, visit https://review.coreboot.org/c/coreboot/+/29394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63 Gerrit-Change-Number: 29394 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Feb 2019 10:29:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Frans Hendriks (Code Review) 07 Feb '19

07 Feb '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 3: > Patch Set 3: > > is the default PCI mode? (since you're not explicitly setting it) > what are the consequences of not passing the correct mode to FSP? Default can be PCI or ACPI, depending on values devicetree.cb. The child devices need to operate ACPI mode when the LPSS is operating in ACPI mode. For this reason the patch is uploaded. FSP MR2 does a check for ACPI mode and change the device mode. Supplying incorrect configuration will be corrected by FSP, but to be futher proof supply correct configuration to FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Feb 2019 10:10:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by HAOUAS Elyes (Code Review) 07 Feb '19

07 Feb '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29986 ) Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... Abandoned not really useful ... -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 07 Feb '19

07 Feb '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... Patch Set 4: > Patch Set 4: > > wouldn't it be a lot easier to just set the LPE device's _STA method to return the correct status based on device presence? You could do it either dynamically based on PCI device 0:15.0 being enabled or present, or statically based on a gnvs set in the mainboard config. This just seems like an overly complicated solution to telling the OS that the LPE hardware isn't present. For sure _STA would be easier. Linux remains requesting status (_STA) of the LPE device, even when reporting disabled. This reduces the performance of the system. For this reason this patch has been implemented. -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Feb 2019 09:43:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019