coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform DDR init
by Julius Werner (Code Review) 07 Feb '19

07 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25208 ) Change subject: sdm845: Add QCLib to RomStage to perform DDR init ...................................................................... Patch Set 69: (6 comments) https://review.coreboot.org/#/c/25208/69/src/mainboard/google/cheza/chromeo… File src/mainboard/google/cheza/chromeos.fmd: https://review.coreboot.org/#/c/25208/69/src/mainboard/google/cheza/chromeo… PS69, Line 35: RW_NVRAM 16K Where did RW_LIMITS_CFG and RW_DDR_TRAINING go (the spaces we want to preserve just in case an update is needed later)? https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/qclib.h: https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/so… PS69, Line 52: #define QCLIB_GA_ENABLE_UART_LOGGING 0x00000001 This used to be 0x2, was it updated in QcLib when you decided to remove SOC_DEBUG_FLOW? (In the future, let's avoid changing these once they have a particular value so the interface is more stable between different versions of coreboot and QcLib. If we deprecate a flag, just keep that in this list as a comment to make clear that it has been used before and shouldn't be reused.) https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… File src/soc/qualcomm/sdm845/qclib_execute.c: https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 1: /* Please note that there are still many comments in CB:27360 that still apply here. https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 39: #define PBL_DATA_PTR 0x14810188 This happened, right? So let's remove this. https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 164: printk(BIOS_INFO, "Board Rev(0x%d)\n", board_id()); > Prefixing 0x with decimal output is defective This is already printed at the end of ramstage, I don't think it needs to be printed here. https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 240: prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); This is no longer used, right? Instead, please set &qclib_cb_if_table as argument here, and then use prog_run() to run it rather than doing that manually. -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 69 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 07 Feb 2019 02:21:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: sdm845: Add GPIO IRQ APIs
by Julius Werner (Code Review) 07 Feb '19

07 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30003 ) Change subject: sdm845: Add GPIO IRQ APIs ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/30003/11/src/soc/qualcomm/sdm845/gpio.c File src/soc/qualcomm/sdm845/gpio.c: https://review.coreboot.org/#/c/30003/11/src/soc/qualcomm/sdm845/gpio.c@90 PS11, Line 90: clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE Please combine into a single access: clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT | GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT); -- To view, visit https://review.coreboot.org/c/coreboot/+/30003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f34e7bba17d9baad1db2bf025ba2db4afdfb58 Gerrit-Change-Number: 30003 Gerrit-PatchSet: 11 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Feb 2019 02:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Add Whiskeylake SoC kconfig
by Furquan Shaikh (Code Review) 06 Feb '19

06 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add Whiskeylake SoC kconfig ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 18:37:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Makefile.inc: Create a default SMMSTORE region
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30421 Change subject: Makefile.inc: Create a default SMMSTORE region ...................................................................... Makefile.inc: Create a default SMMSTORE region Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/drivers/smmstore/Kconfig M util/cbfstool/default-x86.fmd 3 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30421/1 diff --git a/Makefile.inc b/Makefile.inc index 8af291f..7dee1d2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -869,11 +869,27 @@ endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) # +# X86 SMMSTORE FMAP region +# +# position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled +ifeq ($(CONFIG_SMMSTORE),y) +FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ + $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000) +FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE) +FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE) +else # ifeq ($(CONFIG_SMMSTORE),y) +FMAP_SMMSTORE_BASE := 0 +FMAP_SMMSTORE_SIZE := 0 +FMAP_SMMSTORE_ENTRY := +endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) + +# # X86 FMAP region # # # position, size -FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)) +FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \ + $(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE)) FMAP_FMAP_SIZE := 0x200 # @@ -947,6 +963,7 @@ -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ + -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 1ab3a5e..f2c97ab 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -37,4 +37,11 @@ string "SMM store file name" if SMMSTORE_IN_CBFS default "smm_store" +config SMMSTORE_SIZE + hex "size of the SMMSTORE FMAP region" + depends on !SMMSTORE_IN_CBFS + default 0x40000 + help + Set the size of the default SMMSTORE FMAP region. + endif diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 174db1f..f0143e9 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -11,6 +11,7 @@ BIOS@##BIOS_BASE## ##BIOS_SIZE## { ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + ##SMMSTORE_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } -- To view, visit https://review.coreboot.org/c/coreboot/+/30421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Gerrit-Change-Number: 30421 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: Makefile.inc: Make sure the BIOS region is 64K aligned
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30420 Change subject: Makefile.inc: Make sure the BIOS region is 64K aligned ...................................................................... Makefile.inc: Make sure the BIOS region is 64K aligned If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and CONSOLE could end up non aligned. Currently this is only possible if the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be safe than sorry. Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30420/1 diff --git a/Makefile.inc b/Makefile.inc index 85aa19e..8af291f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -146,6 +146,7 @@ int-gt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) \> $(call _toint,$(word 2,$1)))) int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1)))) int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + $ \( $$B - \( $$A % $$B $ \) % $$B \) ) +int-align-down=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A - $ $$A % $$B $ ) file-size=$(strip $(shell cat $1 | wc -c)) tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') @@ -835,8 +836,8 @@ FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) # entire "BIOS" region (everything directly of concern to the host system) # relative to ROM_BASE -FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) -FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) +FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000) +FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000) # position and size of flashmap, relative to BIOS_BASE # -- To view, visit https://review.coreboot.org/c/coreboot/+/30420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Gerrit-Change-Number: 30420 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: Makefile.inc: Optimize generating the default x86 fmap
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30419 Change subject: Makefile.inc: Optimize generating the default x86 fmap ...................................................................... Makefile.inc: Optimize generating the default x86 fmap Put the FMAP FMAP region right above the coreboot region. The other regions like RW_MRC_CACHE and CONSOLE might have alignment requirements so it makes sense to put those on top. This also simplifies the generation code a little. Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M util/cbfstool/default-x86.fmd 2 files changed, 12 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30419/1 diff --git a/Makefile.inc b/Makefile.inc index b25ac6b..85aa19e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -838,19 +838,16 @@ FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) # position and size of flashmap, relative to BIOS_BASE -FMAP_FMAP_BASE := 0 -FMAP_FMAP_SIZE := 0x200 # # X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled +FMAP_CONSOLE_BASE := 0 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := 0 FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) @@ -860,13 +857,8 @@ # # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ $(FMAP_CONSOLE_SIZE)), 0x10000) -else -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \ - $(FMAP_FMAP_SIZE)), 0x10000) -endif FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -876,14 +868,18 @@ endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) # +# X86 FMAP region +# +# +# position, size +FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)) +FMAP_FMAP_SIZE := 0x200 + +# # X86 COREBOOT default cbfs FMAP region # # position and size of CBFS, relative to BIOS_BASE -ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)) -else -FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE)) -endif +FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) else # ifeq ($(CONFIG_ARCH_X86),y) DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 1f1aa43..174db1f 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -9,9 +9,9 @@ FLASH@##ROM_BASE## ##ROM_SIZE## { BIOS@##BIOS_BASE## ##BIOS_SIZE## { - FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Gerrit-Change-Number: 30419 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by build bot (Jenkins) (Code Review) 06 Feb '19

06 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 2: (24 comments) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@108 PS2, Line 108: "*GPIO_72", "GP_CAMERASB10","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@109 PS2, Line 109: "*GPIO_73", "GP_CAMERASB11","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@116 PS2, Line 116: "JTAGX" , "*JTAGX", "n/a", "n/a", "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@123 PS2, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@123 PS2, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@167 PS2, Line 167: "PMC_SPI_FS2", "*PMC_SPI_FS2", "FST_SPI_CS2_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@181 PS2, Line 181: "*GPIO_74", "AVS_I2S1_MCLK" , "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@186 PS2, Line 186: "*GPIO_79", "AVS_DMIC_CLK_A1", "AVS_I2S4_BCLK","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@187 PS2, Line 187: "*GPIO_80", "AVS_DMIC_CLK_B1", "AVS_I2S4_WS_SYNC","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@191 PS2, Line 191: "*GPIO_84", "AVS_I2S2_MCLK", "AVS_HDA_RST_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@319 PS2, Line 319: "*GPIO_134", "LPSS_I2C5_SDA","ISH_I2C0_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@320 PS2, Line 320: "*GPIO_135", "LPSS_I2C5_SCL","ISH_I2C0_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@321 PS2, Line 321: "*GPIO_136", "LPSS_I2C6_SDA","ISH_I2C1_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@322 PS2, Line 322: "*GPIO_137", "LPSS_I2C6_SCL","ISH_I2C1_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@323 PS2, Line 323: "*GPIO_138", "LPSS_I2C7_SDA","ISH_I2C2_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@324 PS2, Line 324: "*GPIO_139", "LPSS_I2C7_SCL","ISH_I2C2_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@335 PS2, Line 335: "GPIO_209", "*PCIE_CLKREQ0_N", "MODEM_CLK_REQ","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@339 PS2, Line 339: "OSC_CLK_OUT_0","*OSC_CLK_OUT_0", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@340 PS2, Line 340: "OSC_CLK_OUT_1","*OSC_CLK_OUT_1", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@341 PS2, Line 341: "OSC_CLK_OUT_2","*OSC_CLK_OUT_2", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@342 PS2, Line 342: "OSC_CLK_OUT_3","*OSC_CLK_OUT_3", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@343 PS2, Line 343: "OSC_CLK_OUT_4","*OSC_CLK_OUT_4", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@344 PS2, Line 344: "*PMU_AC_PRESENT","PMU_AC_PRESENT", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@353 PS2, Line 353: "*PMU_WAKE_B", "PMU_WAKE_B/EMMC_PWR_EN_N","n/a", "n/a", space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 17:39:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 06 Feb '19

06 Feb '19

Felix Singer has uploaded a new patch set (#2) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c 2 files changed, 353 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29897/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mb/google/hatch: Configure I2C buses
by Furquan Shaikh (Code Review) 06 Feb '19

06 Feb '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31237 Change subject: mb/google/hatch: Configure I2C buses ...................................................................... mb/google/hatch: Configure I2C buses This change enables I2C bus 2, 3 and 4 in devicetree and configures GPIO pads for the same. It also configures pads for I2C5 as no-connect. BUG=b:123711244 Change-Id: Ib4714a670d73228332115415e4393f82802c6475 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31237/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 511c2d6..eb528f2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -214,8 +214,8 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -223,7 +223,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 + device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a078997..f8d5d7d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -144,6 +144,23 @@ /* SD_WP => NC */ PAD_NC(GPP_G7, DN_20K), + /* PCH_I2C_PEN_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* PCH_I2C_PEN_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* PCH_I2C_SAR0_MST_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* PCH_I2C_SAR0_MST_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* PCH_I2C_M2_AUDIO_SAR1_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* PCH_I2C_M2_AUDIO_SAR1_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* PCH_I2C_TRACKPAD_SDA */ + PAD_NC(GPP_H10, NONE), + /* PCH_I2C_TRACKPAD_SCL */ + PAD_NC(GPP_H11, NONE), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4714a670d73228332115415e4393f82802c6475 Gerrit-Change-Number: 31237 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Remove the unused section of reef RO flash and give it to coreboot.
by Mathew King (Code Review) 06 Feb '19

06 Feb '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31230 Change subject: Remove the unused section of reef RO flash and give it to coreboot. ...................................................................... Remove the unused section of reef RO flash and give it to coreboot. BUG=chromium:903833,b:120086021 TEST=emerge-reef coreboot Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/reef/chromeos.fmd 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/31230/1 diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 768d322..f601adc 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -7,9 +7,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x17b000 - GBB@0x17c000 0x40000 - RO_UNUSED@0x1bc000 0x40000 + COREBOOT(CBFS)@0x1000 0x1bb000 + GBB@0x1bc000 0x40000 } } MISC_RW@0x400000 0x30000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/31230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67 Gerrit-Change-Number: 31230 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

5 9

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019