February 2019 - coreboot-gerrit

Change in ...coreboot[master]: soc/intel/cannonlake: Add Whiskeylake SoC kconfig
by Aamir Bohra (Code Review) Feb. 6, 2019

Feb. 6, 2019

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add Whiskeylake SoC kconfig ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 11:03:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add Whiskeylake SoC kconfig
by Aamir Bohra (Code Review) Feb. 6, 2019

Feb. 6, 2019

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add Whiskeylake SoC kconfig ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/31133/8/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/31133/8/src/soc/intel/cannonlake/Kconfig@267 PS8, Line 267: SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE > yes check comment here […] Ok. -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 11:03:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Use a common romstage
by Arthur Heymans (Code Review) Feb. 6, 2019

Feb. 6, 2019

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/gm45: Use a common romstage ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31190/4/src/mainboard/roda/rk9/romstage.c File src/mainboard/roda/rk9/romstage.c: https://review.coreboot.org/#/c/31190/4/src/mainboard/roda/rk9/romstage.c@86 PS4, Line 86: 0x50 > It would be great to place those values in devicetree, but that's out of scope of this patch. I think ideally you have a function pointer for the SPD. that way you can also provide them via cbfsfiles if soldered. Given that no board needs it, it is overkill atm. -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 10:55:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: Add Project Ideas document
by Patrick Georgi (Code Review) Feb. 6, 2019

Feb. 6, 2019

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30972 Change subject: Documentation: Add Project Ideas document ...................................................................... Documentation: Add Project Ideas document This is unfinished and we should collect ideas in this commit while it's under review on Gerrit until things settled. This will provide less churn and conflicts than multiple commits trying to edit the same file. Change-Id: Idd68f845930bd37a2293969b9a153cf584d6d15f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A Documentation/contributing/project_ideas.md 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30972/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md new file mode 100644 index 0000000..2e89dea --- /dev/null +++ b/Documentation/contributing/project_ideas.md @@ -0,0 +1,34 @@ +# Project Ideas + +This section collects ideas to improve coreboot and related projects and +should serve as a pool of ideas for people who want to enter the field of +firmware development but need some guidance what to work on. + +These tasks can be adopted as part of programs like Google Summer of Code or +by motivated individuals outside such programs. + +Each entry should outline what would be done, the benefit it brings to the +project, the pre-requisites, both in knowledge and parts. They should also +list people interested in supporting people who want to work on them - since +we started building this list for Google Summer of Code, we'll adopt its term +for those people and call them mentors. + +## Provide toolchain binaries +Our crossgcc subproject provides a uniform compiler environment for working on +coreboot and related projects. Sadly, building it takes hours, which is a bad +experience when trying to build coreboot the first time. + +Provide packages/installers of our compiler toolchain for Linux distros, +Windows, Mac OS. For Windows, this should also include the environment (shell, +make, ...). + +## Requirements + +* coreboot knowledge: little +* other knowledge: should know how packages or installers for their target OS + work. Knowledge of the GCC build system is a big plus +* hardware requirements: nothing special + +## Mentors +* Patrick Georgi <patrick(a)georgi.software> + -- To view, visit https://review.coreboot.org/c/coreboot/+/30972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd68f845930bd37a2293969b9a153cf584d6d15f Gerrit-Change-Number: 30972 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add Whiskeylake SoC kconfig
by Subrata Banik (Code Review) Feb. 6, 2019

Feb. 6, 2019

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add Whiskeylake SoC kconfig ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/31133/8/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/31133/8/src/soc/intel/cannonlake/Kconfig@267 PS8, Line 267: SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE > SOC_INTEL_COMMON_CANNONLAKE_BASE? […] yes check comment here https://review.coreboot.org/#/c/31133/7..8/src/soc/intel/cannonlake/Kconfig Furquan Shaikh 12:52 AM Have to be careful about this. If SOC_INTEL_COMMON_CANNONLAKE_BASE is expected to be selected by all new SoCs using CNL PCH, then you need to ensure that they use the right FSP headers and paths. Subrata Banik 12:56 AM this may not holds true for CML because that will have CML FSP package, so i have to add CFL and WHL Kconfig specifically here -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 08:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add Whiskeylake SoC kconfig
by Aamir Bohra (Code Review) Feb. 6, 2019

Feb. 6, 2019

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add Whiskeylake SoC kconfig ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/31133/8/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/31133/8/src/soc/intel/cannonlake/Kconfig@267 PS8, Line 267: SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE SOC_INTEL_COMMON_CANNONLAKE_BASE? or this to accommodate for future platforms not using intel fsp git and still selects SOC_INTEL_COMMON_CANNONLAKE_BASE? -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 08:17:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Use a common romstage
by Patrick Rudolph (Code Review) Feb. 6, 2019

Feb. 6, 2019

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/gm45: Use a common romstage ...................................................................... Patch Set 4: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/31190/4/src/mainboard/roda/rk9/romstage.c File src/mainboard/roda/rk9/romstage.c: https://review.coreboot.org/#/c/31190/4/src/mainboard/roda/rk9/romstage.c@86 PS4, Line 86: 0x50 It would be great to place those values in devicetree, but that's out of scope of this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Feb 2019 07:16:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Duncan Laurie (Code Review) Feb. 6, 2019

Feb. 6, 2019

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 ) Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Feb 2019 01:32:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Furquan Shaikh (Code Review) Feb. 6, 2019

Feb. 6, 2019

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 ) Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31250/3/src/soc/intel/cannonlake/chip.c File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/#/c/31250/3/src/soc/intel/cannonlake/chip.c@159 PS3, Line 159: PCH_H > I see you said it isn't needed, but is there a downside to enabling? Actually, gpio.c is kind of separate for PCH-H and I did not want to duplicate the code (in the hope that FSP will get fixed pretty soon). But, since we are not sure of the timeline, its probably better to just do it unconditionally. I have moved cnl_configure_pads to chip.c. -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Feb 2019 01:22:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Furquan Shaikh (Code Review) Feb. 6, 2019

Feb. 6, 2019

Hello Aaron Durbin, Patrick Rudolph, Duncan Laurie, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31250 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... soc/intel/cannonlake: Configure GPIOs again after FSP-S is done FSP-S is currently configuring GPIOs that it should not. This results in issues where mainboard devices don't behave as expected e.g. host unable to receive TPM interrupts as the pad for the interrupt is re-configured as something else. Until FSP-S is fixed, this change adds a workaround by reconfiguring GPIOs after FSP-S is run. All mainboards need to call cnl_configure_pads instead of gpio_configure_pads so that SoC code can maintain a reference to the GPIO table and use that to re-configure GPIOs after FSP-S is run. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/include/soc/gpio.h 2 files changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31250/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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