coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
by Duncan Laurie (Code Review) 06 Feb '19

06 Feb '19

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Duncan Laurie (Code Review) 06 Feb '19

06 Feb '19

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 ) Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... Patch Set 3: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/31250/3/src/soc/intel/cannonlake/chip.c File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/#/c/31250/3/src/soc/intel/cannonlake/chip.c@159 PS3, Line 159: PCH_H I see you said it isn't needed, but is there a downside to enabling? -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Feb 2019 01:16:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Furquan Shaikh (Code Review) 06 Feb '19

06 Feb '19

Hello Aaron Durbin, Patrick Rudolph, Duncan Laurie, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31250 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... soc/intel/cannonlake: Configure GPIOs again after FSP-S is done FSP-S is currently configuring GPIOs that it should not. This results in issues where mainboard devices don't behave as expected e.g. host unable to receive TPM interrupts as the pad for the interrupt is re-configured as something else. Until FSP-S is fixed, this change adds a workaround by reconfiguring GPIOs after FSP-S is run. All mainboards need to call cnl_configure_pads instead of gpio_configure_pads so that SoC code can maintain a reference to the GPIO table and use that to re-configure GPIOs after FSP-S is run. This change is currently not made for CNL-PCH-H since I do not see any boards with PCH-H that care about this. If required, the change can be easily extended to enable the same logic. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/include/soc/gpio.h 3 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31250/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
by Aaron Durbin (Code Review) 06 Feb '19

06 Feb '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31251 ) Change subject: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Gerrit-Change-Number: 31251 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Feb 2019 00:57:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Aaron Durbin (Code Review) 06 Feb '19

06 Feb '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 ) Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Feb 2019 00:55:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/coffeelake_rvp: Select CHROMEOS for CFL-U and WHL-U RVP
by Subrata Banik (Code Review) 05 Feb '19

05 Feb '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31214 Change subject: mb/intel/coffeelake_rvp: Select CHROMEOS for CFL-U and WHL-U RVP ...................................................................... mb/intel/coffeelake_rvp: Select CHROMEOS for CFL-U and WHL-U RVP This patch ensures to select chromeos kconfig only for required CFL-U and WHL-U RVPs supported by Intel Client team. TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected for CFL-U and WHL-U boards. Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31214/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 1019805..fbfcc0f 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -44,6 +44,12 @@ default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP default "Intel_cflrvp" +config CHROMEOS + bool + default n if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + default y + select GBB_FLAG_FORCE_MANUAL_RECOVERY + config MAX_CPUS int default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 -- To view, visit https://review.coreboot.org/c/coreboot/+/31214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d Gerrit-Change-Number: 31214 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: describe coreboot on the dev site's landing page
by Patrick Georgi (Code Review) 05 Feb '19

05 Feb '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31127 Change subject: Documentation: describe coreboot on the dev site's landing page ...................................................................... Documentation: describe coreboot on the dev site's landing page Get some content on the documentation site's front page. Some links still need to be filled in with content yet to be written, but we need to start somewhere. Change-Id: I7f36234ef783e041a44590858bb75a69b96ee668 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/index.md 1 file changed, 134 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31127/1 diff --git a/Documentation/index.md b/Documentation/index.md index 9fdb0dc..7498caa 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -5,6 +5,140 @@ [Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documenta… directory in the source code. +## Purpose of coreboot + +coreboot is a project to develop open source firmware for various +architectures. Its design philosophy is to do the bare minimum necessary to +ensure that hardware is usable and then pass control to a different program +that called the _payload_. + +### Separation of concerns + +The payload can then provide user interfaces, file system drivers, +various policies etc. to load the OS. Through this separation of concerns +coreboot maximizes reusability of the complicated and fundamental hardware +initialization routines across many different use cases, no matter if +they provide standard interfaces or entirely custom boot flows. + +Popular [payloads]() in use with coreboot are SeaBIOS, which provides PCBIOS +services, Tianocore, which provides UEFI services, GRUB2, the bootloader +used by many Linux distributions, or depthcharge, a custom boot loader +on Chromebooks. + +### No resident services (if possible) + +Ideally coreboot completely hands over control to the payload with no +piece of coreboot remaining resident in the system, or even available +for callback. Given the reality of contemporary computer design, +there's often a small piece that survives for the whole runtime of +the computer. It runs in a highly privileged CPU mode (eg SMM on x86) +and provides some limited amount of services to the OS. But here, too, +coreboot aims to keep everything at the minimum possible, both in scope +(eg. services provided) and code size. + +### No specification of its own + +coreboot uses a very minimal interface to the payload, and otherwise +doesn't impose any standards on the ecosystem. This is made possible by +separating out concerns (interfaces and resident services are delegated +to the payload), but it's also a value that is deeply ingrained in the +project. We fearlessly rip out parts of the architecture and remodel it +when a better way of doing the same was identified. + +### One tree for everything + +Another difference to various other firmware projects is that we try +to avoid fragmentation: the traditional development model of firmware +is one of "set and forget" in which some code base is copied, adapted +for the purpose at hands, shipped and only touched again if there's an +important fix to do. + +All newer development happens on another copy of some code base without +flowing back to any older copy, and so normally there's a huge amount +of fragmentation. + +In coreboot, we try to keep everything in a single source tree, and +lift up older devices when we change something fundamentally. That way, +new and old devices benefit alike from new development in the common parts. + +There's a downside to that: Some devices might have no maintainer anymore +who could ensure that coreboot is still functional for them after a big +rework, or maybe a rework even requires knowledge that doesn't exist +anymore within the project (for example because the developer moved on +to do something else). + +In this case, we announce the deprecation of the device and defer the big +rework until the deprecation period passed, typically 6-12 months. This +gives interested developers a chance to step in and bring devices up to +latest standards. + +While without this deprecation mechanism we could inflate the number +of supported devices (probably 300+), only a tiny fraction of them +would even work, which helps nobody. + +## Scope of the coreboot project + +coreboot as a project is closer to the Linux kernel than to most +user level programs. One place where this becomes apparent is the +distribution mechanism: The project itself only provides source code +(plus redistributable binaries for parts that we haven't managed to open +up) and does not ship ready-to-install coreboot-based firmware binaries. + +There are various [distributions](), some shipping coreboot with their hardware +(eg. Purism or Chromebooks), others providing after-market images for +various devices (eg. Libreboot, MrChromebox). + +If you want to use coreboot on your system, that's great! + +Please note that the infrastructure around coreboot.org is built for +development purposes. We gladly help out users through our communication +channels, but we also expect a "firmware developer mindset": If compiling +your own firmware and, at some point, recovering from a bad flash by +hooking wires onto chips in your computer sounds scary to you, you're +right, as it is. + +If that's _way_ beyond your comfort zone, consider looking into the +various distributions, as they typically provide pre-tested binaries +which massively reduces the risk that the binary you write to flash is +one that won't boot the system (with the consequence that to get it to work +again, you'll need to attach various tools to various chips) + +## The coreboot community + +If you're interested in getting your hands dirty (incl. potentially wiring +up an external flasher to your computer), you've come to the right place! + +We have various [virtual sites]() where we discuss and coordinate +our activities, review patches, and help out each other. To +help promote a positive atmosphere, we established a [Code of +Conduct](code_of_conduct.md). We invested a lot of time to balance it out, +so please keep it in mind when engaging with the coreboot community. + +Every now and then, coreboot is present in one way or another at +[conferences](). If you're around, come and say hello! + +## Getting the source code + +coreboot is primarily developed in the +[git](https://review.coreboot.org/cgit/coreboot.git) DSCM, using +[Gerrit](https://review.coreboot.org) to manage contributions and +code review. + +In general we try to keep the `master` branch in the repository functional +for all hardware we support. So far, the only guarantee we can make is +that the master branch will (nearly) always build for all boards in a +standard configuration. + +However we're continually working on improvements to our infrastructure to +get better in that respect, eg by setting up boot testing facilities. This +is obviously more complex than regular integration testing, so progress +is slow. + +We also schedule two source code releases every year, around April and +October. These releases see some very limited testing and mostly serve +as synchronization points for deprecation notices and for other projects +such as external distributions. + Contents: * [Getting Started](getting_started/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/31127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f36234ef783e041a44590858bb75a69b96ee668 Gerrit-Change-Number: 31127 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
by Furquan Shaikh (Code Review) 05 Feb '19

05 Feb '19

Hello Aaron Durbin, Duncan Laurie, Shelley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31251 to look at the new patch set (#2). Change subject: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads ...................................................................... mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads This change uses cnl_configure_pads to configure GPIOs in ramstage so that cannonlake SoC code can re-configure the GPIOs after FSP-S is run. This is just adding a workaround until FSP-S is fixed. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/sarien/ramstage.c 2 files changed, 4 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31251/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Gerrit-Change-Number: 31251 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
by Furquan Shaikh (Code Review) 05 Feb '19

05 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31251 ) Change subject: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31251/1/src/mainboard/google/sarien/ramstag… File src/mainboard/google/sarien/ramstage.c: https://review.coreboot.org/#/c/31251/1/src/mainboard/google/sarien/ramstag… PS1, Line 31: /* Workaround FSP issue by reprogramming GPIOs after FSP-S */ : static void mainboard_init(struct device *dev) : { : const struct pad_config *gpio_table; : size_t num_gpios; : : gpio_table = variant_gpio_table(&num_gpios); : gpio_configure_pads(gpio_table, num_gpios); : } > Should be able to kill this now. Oops yeah. I had made the change, but never added it. -- To view, visit https://review.coreboot.org/c/coreboot/+/31251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Gerrit-Change-Number: 31251 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Tue, 05 Feb 2019 22:13:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
by Duncan Laurie (Code Review) 05 Feb '19

05 Feb '19

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31251 ) Change subject: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31251/1/src/mainboard/google/sarien/ramstag… File src/mainboard/google/sarien/ramstage.c: https://review.coreboot.org/#/c/31251/1/src/mainboard/google/sarien/ramstag… PS1, Line 31: /* Workaround FSP issue by reprogramming GPIOs after FSP-S */ : static void mainboard_init(struct device *dev) : { : const struct pad_config *gpio_table; : size_t num_gpios; : : gpio_table = variant_gpio_table(&num_gpios); : gpio_configure_pads(gpio_table, num_gpios); : } Should be able to kill this now. -- To view, visit https://review.coreboot.org/c/coreboot/+/31251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Gerrit-Change-Number: 31251 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Tue, 05 Feb 2019 22:12:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019