February 2019 - coreboot-gerrit

Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) Feb. 6, 2019

Feb. 6, 2019

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 12: (4 comments) https://review.coreboot.org/#/c/29968/12/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/12/src/soc/qualcomm/qcs405/spi.c@311 PS12, Line 311: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/12/src/soc/qualcomm/qcs405/spi.c@312 PS12, Line 312: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/12/src/soc/qualcomm/qcs405/spi.c@313 PS12, Line 313: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/12/src/soc/qualcomm/qcs405/spi.c@314 PS12, Line 314: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 05 Feb 2019 22:07:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) Feb. 6, 2019

Feb. 6, 2019

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 12: (2 comments) https://review.coreboot.org/#/c/29967/12/src/soc/qualcomm/qcs405/qclib_exec… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/12/src/soc/qualcomm/qcs405/qclib_exec… PS12, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/12/src/soc/qualcomm/qcs405/qclib_exec… PS12, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Feb 2019 22:07:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qualcomm/qcs405: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) Feb. 6, 2019

Feb. 6, 2019

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: qualcomm/qcs405: Add support for USB host mode for mistral platform ...................................................................... Patch Set 11: (4 comments) https://review.coreboot.org/#/c/29966/11/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/11/src/soc/qualcomm/qcs405/usb.c@137 PS11, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/11/src/soc/qualcomm/qcs405/usb.c@138 PS11, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/11/src/soc/qualcomm/qcs405/usb.c@139 PS11, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/11/src/soc/qualcomm/qcs405/usb.c@140 PS11, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 11 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 05 Feb 2019 22:07:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) Feb. 6, 2019

Feb. 6, 2019

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 11: (4 comments) https://review.coreboot.org/#/c/29968/11/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/11/src/soc/qualcomm/qcs405/spi.c@311 PS11, Line 311: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/11/src/soc/qualcomm/qcs405/spi.c@312 PS11, Line 312: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/11/src/soc/qualcomm/qcs405/spi.c@313 PS11, Line 313: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/11/src/soc/qualcomm/qcs405/spi.c@314 PS11, Line 314: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 11 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 05 Feb 2019 21:47:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) Feb. 6, 2019

Feb. 6, 2019

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/#/c/29967/11/src/soc/qualcomm/qcs405/qclib_exec… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/11/src/soc/qualcomm/qcs405/qclib_exec… PS11, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/11/src/soc/qualcomm/qcs405/qclib_exec… PS11, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 11 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Feb 2019 21:47:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qualcomm/qcs405: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) Feb. 6, 2019

Feb. 6, 2019

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: qualcomm/qcs405: Add support for USB host mode for mistral platform ...................................................................... Patch Set 10: (4 comments) https://review.coreboot.org/#/c/29966/10/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/10/src/soc/qualcomm/qcs405/usb.c@137 PS10, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/10/src/soc/qualcomm/qcs405/usb.c@138 PS10, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/10/src/soc/qualcomm/qcs405/usb.c@139 PS10, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/10/src/soc/qualcomm/qcs405/usb.c@140 PS10, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 10 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 05 Feb 2019 21:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Documentation: Describe our ecosystem
by Patrick Georgi (Code Review) Feb. 6, 2019

Feb. 6, 2019

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31180 Change subject: Documentation: Describe our ecosystem ...................................................................... Documentation: Describe our ecosystem Neither payloads nor distributors are an integral part of the coreboot source tree, but they're very important parts of the coreboot ecosystems, so add some descriptions. Change-Id: Id64744c252b6b78c4811fbded48c441ef486ad94 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A Documentation/distributions.md M Documentation/index.md A Documentation/payloads.md 3 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31180/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md new file mode 100644 index 0000000..788e808 --- /dev/null +++ b/Documentation/distributions.md @@ -0,0 +1,46 @@ +# Distributions + +coreboot doesn't provide binaries but provides a toolbox that others can use +to build boot firmware for all kinds of purposes. These third-parties can be +broadly separated in two groups: Those shipping coreboot on their hardware, +and those providing after-market firmware to extend the usefulness of devices. + +## Shipping coreboot on hardware + +### Purism + +[Purism](https://www.puri.sm) sells laptops with a focus on privacy and +part of that is their push to remove as much unaccounted code (that is, +binary only) from their devices as possible. + +### Chromebooks + +All Chromebooks (and related devices) that hit the market after 2013 are +using coreboot as their main firmware. And even the Embedded Controller, +a small microcontroller to support various periphery (like battery +management or the keyboard) is running open source firmware. + + +## After-market firmware + +### Libreboot + +[Libreboot](https://libreboot.org) is a project that provides ready-made +binaries for platforms where those can be built entirely from source +code. Their copy of the coreboot repository is therefore stripped of +all devices that require binary components to boot. + +### John Lewis + +[John Lewis](https://johnlewis.ie/custom-chromebook-firmware) provides +replacement firmware for some Chromebooks. Why replace coreboot with +coreboot? You might want to do different things than what the Google +engineers prepared for the mass market, that's why. This firmware is +"with training wheels off". + +### Mr. Chromebox + +[Matt Devo](https://mrchromebox.tech/) also provides replacements for +Chromebook firmware, for the same reasons as John Lewis. It's a somewhat +different set of devices, and with different configurations, so check +out both if Chromebooks are what you're dealing with. diff --git a/Documentation/index.md b/Documentation/index.md index af3886e..c5bfa9b 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -13,6 +13,8 @@ * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) * [coreboot at conferences](community/conferences.md) +* [Payloads](payloads.md) +* [Distributions](distributions.md) * [Timestamps](timestamp.md) * [Intel IFD Binary Extraction](Binary_Extraction.md) * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) diff --git a/Documentation/payloads.md b/Documentation/payloads.md new file mode 100644 index 0000000..b1eae61 --- /dev/null +++ b/Documentation/payloads.md @@ -0,0 +1,42 @@ +# Payloads + +coreboot doesn't try to mandate how the boot process should look, it merely +does hardware init and then passes on control to another piece of software +that we carry along in firmware storage, the _payload_. + +There is various software in that space that is either explicitly written as +payload or can be made to work as one. + +## SeaBIOS + +[SeaBIOS](https://www.seabios.org) is an open source implementation of +the PCBIOS API that exists since the original IBM PC and was extended +since. While originally written for emulators such as QEMU, it can be made +to work as a coreboot payload and all the necessary code is in SeaBIOS' +mainline code. + +## Tianocore + +[Tianocore](https://www.tianocore.org) is the open source reference +implementation of the UEFI Specifications that modern firmware for PCs is +based on. There were various projects in the past to make it suitable as a +coreboot payload, but these days this function is available directly in the +CorebootPayloadPkg part of its source tree. + +## GRUB2 + +GRUB2 was originally written as a bootloader and that's its most popular +purpose, but it can also be compiled as a coreboot payload. + +## Linux + +There are several projects using Linux as a payload (which was the +configuration that gave coreboot its original name, LinuxBIOS). That kernel is +often rather small and serves to load a current kernel from somewhere, e.g. +disk or network, and run that through the kexec mechanism. + +Two aspects emphasized by proponents of Linux-as-a-payload are the +availability of well-tested, battle-hardened drivers (as compared to +firmware project drivers that often reinvent the wheel) and the ability to +define boot policy with familiar tools, no matter if those are shell scripts +or compiled userland programs written in C, Go or other programming languages. -- To view, visit https://review.coreboot.org/c/coreboot/+/31180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id64744c252b6b78c4811fbded48c441ef486ad94 Gerrit-Change-Number: 31180 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: Documentation: Allow passing arguments into make livesphinx
by Patrick Georgi (Code Review) Feb. 6, 2019

Feb. 6, 2019

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31128 Change subject: Documentation: Allow passing arguments into make livesphinx ...................................................................... Documentation: Allow passing arguments into make livesphinx It's what the doc.coreboot.org docker container is running and when using its livehtml feature, it listens at localhost, which isn't always desirable. With `docker run -e SPHINXOPTS="-H $localip" ...` it now listens at localip, which is more flexible. Change-Id: Ia0614e57458c32169f6d614783366025e9c814b3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/31128/1 diff --git a/Documentation/Makefile b/Documentation/Makefile index ed08936..b4fe8df 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -52,4 +52,4 @@ rm -f corebootPortingGuide.pdf livesphinx: - $(MAKE) -f Makefile.sphinx livehtml + $(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0614e57458c32169f6d614783366025e9c814b3 Gerrit-Change-Number: 31128 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary
by Julius Werner (Code Review) Feb. 6, 2019

Feb. 6, 2019

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29916 ) Change subject: Fix coreboot table record alignment to 8-byte boundary ...................................................................... Patch Set 5: > Yes, this patch can solve the problem under the RISC-V platform, but if you add a 128-bit new platform, you need to modify a lot of code. We don't need to double the alignment for long-time stable data structures every time we want to support a new architecture, especially with a change that will affect all architectures at once. There are ways to access unaligned data... if RISC-V can't do it implicitly, just add the code for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/29916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846be0e26ab3c81858d8cf727517e1462035e64 Gerrit-Change-Number: 29916 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Feb 2019 20:50:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/denverton_ns: Lock SPIBAR
by Vanessa Eusebio (Code Review) Feb. 6, 2019

Feb. 6, 2019

Vanessa Eusebio has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25441 ) Change subject: soc/intel/denverton_ns: Lock SPIBAR ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/25441/10/src/soc/intel/denverton_ns/lpc.c File src/soc/intel/denverton_ns/lpc.c: https://review.coreboot.org/#/c/25441/10/src/soc/intel/denverton_ns/lpc.c@3… PS10, Line 334: static void spi_lock_bar(bool relax_security) Not sure if this should be in LPC since this is SPI -- To view, visit https://review.coreboot.org/c/coreboot/+/25441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Gerrit-Change-Number: 25441 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 05 Feb 2019 20:22:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0