February 2019 - coreboot-gerrit

Change in ...coreboot[master]: libpayload/libc/libgcc: Fix left shift
by HAOUAS Elyes (Code Review) Feb. 6, 2019

Feb. 6, 2019

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23375 ) Change subject: libpayload/libc/libgcc: Fix left shift ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/23375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55d50c264d669e39bc6afbe55004b0be1b3f6e1 Gerrit-Change-Number: 23375 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Feb 2019 15:34:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: update/improve distribution listing
by Matt DeVillier (Code Review) Feb. 6, 2019

Feb. 6, 2019

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31252 Change subject: Documentation: update/improve distribution listing ...................................................................... Documentation: update/improve distribution listing - improve descriptions of Purism and ChromeOS hardware - add entry for Libretrend Librebox - improve description of Mr Chromebox and John Lewis' 3rd party ChromeOS firmware offerings Change-Id: I66bd1a3701091e499d88738a7c06126de66e58ff Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M Documentation/distributions.md 1 file changed, 37 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31252/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 837a744..b89e295 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -5,42 +5,57 @@ broadly separated in two groups: Those shipping coreboot on their hardware, and those providing after-market firmware to extend the usefulness of devices. -## Shipping coreboot on hardware + +## Hardware shipping with coreboot ### Purism -[Purism](https://www.puri.sm) sells laptops with a focus on privacy and -part of that is their push to remove as much unaccounted code (that is, -binary only) from their devices as possible. +[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and +security; part of that effort is to minimize the amount of proprietary and/or +binary code. Their laptops ship with a blob-free OS and coreboot firmware +with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. -### Chromebooks +### ChromeOS Devices -All Chromebooks (and related devices) that hit the market after 2013 are -using coreboot as their main firmware. And even the Embedded Controller, -a small microcontroller to support various peripherals (like battery -management or the keyboard) is running open source firmware. +All ChromeOS devices (Chromebooks, Chromeboxes, Chromebit, etc) released from +2012 on use coreboot for their main system firmware. Additionally, starting with +the 2013 Chromebook Pixel, the firmware running the Embedded Controller (EC - +a small microcontroller which provides functions like battery management, keyboard +support, and sensor interfacing) is open source as well. + +### Libretrend + +[Libretrend](https://libretrend.com) sells the Librebox, a NUC-like PC +which chips with coreboot firmware. ## After-market firmware ### Libreboot -[Libreboot](https://libreboot.org) is a project that provides ready-made -binaries for platforms where those can be built entirely from source -code. Their copy of the coreboot repository is therefore stripped of -all devices that require binary components to boot. +[Libreboot](https://libreboot.org) is a downstream coreboot distribution that +provides ready-made binaries for supported devices/platforms, where those can +be built entirely from source code. Their copy of the coreboot repository is +therefore stripped of all devices that require binary components to boot. ### Mr. Chromebox -[Matt Devo](https://mrchromebox.tech/) provides replacement firmware for -various Chromebooks. Why replace coreboot with coreboot? You might want -to do different things than what the Google engineers prepared for the -mass market, that's why. This firmware is "with training wheels off". +[Mr Chromebox](https://mrchromebox.tech/) provides upstream coreboot +firmware images for the vast majority of x86-based Chromebooks and Chromeboxes, + using Tianocore as the payload to provide a modern UEFI bootloader. Why +replace coreboot with coreboot? Mr Chromebox's images are built using upstream +coreboot, include many features and fixes not found in the stock firmware, and +offer much broader OS compatibility (i.e,, they run Windows as well as Linux). +They also offer updated CPU microcode, as well as firmware updates for the +device's embedded controller (EC). +This firmware "takes the training wheels off" your ChromeOS device :) ### John Lewis -[John Lewis](https://johnlewis.ie/custom-chromebook-firmware) also -provides replacements for Chromebook firmware, for the same reasons -as Mr. Chromebox. It's a somewhat different set of devices, and with -different configurations, so check out both if Chromebooks are what -you're dealing with. +[John Lewis](https://johnlewis.ie/custom-chromebook-firmware) also provides +replacement firmware for ChromeOS devices, for the express purpose of +running Linux on Chromebooks. John Lewis' firmware supports a much smaller +set of devices, and uses SeaBIOS as the payload to support Legacy BIOS booting. +His firmware images are a good deal older, and not actively maintained or +supported, but worth a look if you need Legacy Boot support and is not +available via Mr Chromebox's firmware. -- To view, visit https://review.coreboot.org/c/coreboot/+/31252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66bd1a3701091e499d88738a7c06126de66e58ff Gerrit-Change-Number: 31252 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x60: Use big enough type for left-shift
by Paul Menzel (Code Review) Feb. 6, 2019

Feb. 6, 2019

Hello HAOUAS Elyes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/23376 to look at the new patch set (#3). Change subject: mb/lenovo/x60: Use big enough type for left-shift ...................................................................... mb/lenovo/x60: Use big enough type for left-shift ``` src/mainboard/lenovo/x60/romstage.c: In function 'early_ich7_init': src/mainboard/lenovo/x60/romstage.c:138:14: error: result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] reg32 |= (1 << 31) | (1 << 27); ^~ ``` Change-Id: Ieee2f7cc121909103e68f1083bf9b78aae961088 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/lenovo/x60/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/23376/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/23376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieee2f7cc121909103e68f1083bf9b78aae961088 Gerrit-Change-Number: 23376 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/lenovo/x60: Use big enough type for left-shift
by Nico Huber (Code Review) Feb. 6, 2019

Feb. 6, 2019

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23376 ) Change subject: mb/lenovo/x60: Use big enough type for left-shift ...................................................................... Patch Set 2: 1u is not guaranteed to be 32-bit either. 1ul would be. -- To view, visit https://review.coreboot.org/c/coreboot/+/23376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieee2f7cc121909103e68f1083bf9b78aae961088 Gerrit-Change-Number: 23376 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 06 Feb 2019 12:51:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/x60: Use big enough type for left-shift
by HAOUAS Elyes (Code Review) Feb. 6, 2019

Feb. 6, 2019

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23376 ) Change subject: mb/lenovo/x60: Use big enough type for left-shift ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/23376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieee2f7cc121909103e68f1083bf9b78aae961088 Gerrit-Change-Number: 23376 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Feb 2019 12:38:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Use a common romstage
by Patrick Georgi (Code Review) Feb. 6, 2019

Feb. 6, 2019

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/gm45: Use a common romstage ...................................................................... nb/intel/gm45: Use a common romstage This moves a lot of the common romstage boilerplate code to a common location, while adding a few mainboard specific hooks. Another difference is that the settings for enable_igd and enable_peg are now based on the static devicetree settings. Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31190 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/roda/rk9/romstage.c M src/northbridge/intel/gm45/Makefile.inc M src/northbridge/intel/gm45/gm45.h A src/northbridge/intel/gm45/romstage.c 6 files changed, 181 insertions(+), 267 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 44f560b..9f8993c 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -16,15 +16,7 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. -#include <stdint.h> -#include <string.h> #include <arch/io.h> -#include <arch/acpi.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/tsc.h> -#include <cpu/intel/romstage.h> -#include <cbmem.h> -#include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/gpio.h> @@ -33,7 +25,6 @@ #include "dock.h" #define LPC_DEV PCI_DEV(0, 0x1f, 0) -#define MCH_DEV PCI_DEV(0, 0, 0) static void hybrid_graphics_init(sysinfo_t *sysinfo) { @@ -45,7 +36,9 @@ sysinfo->enable_peg = peg; } -static void early_lpc_setup(void) +static int dock_err; + +void mb_setup_lpc(void) { /* Set up SuperIO LPC forwards */ @@ -59,99 +52,35 @@ pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); } -void mainboard_romstage_entry(unsigned long bist) +void mb_setup_superio(void) { - sysinfo_t sysinfo; - int s3resume = 0; - int cbmem_initted; - int err; - u16 reg16; - - /* basic northbridge setup, including MMCONF BAR */ - gm45_early_init(); - - if (bist == 0) - enable_lapic(); - - /* First, run everything needed for console output. */ - i82801ix_early_init(); - early_lpc_setup(); - /* Minimal setup to detect dock */ - err = pc87382_early(); - if (err == 0) + dock_err = pc87382_early(); + if (dock_err == 0) dock_connect(); +} - console_init(); - printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist); +void get_mb_spd_addrmap(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x51; +} - /* Print dock info */ - if (err) +void mb_pre_raminit_setup(sysinfo_t *sysinfo) +{ + /* Console is not yet initialized in mb_setup_superio, so we print + the dock information here */ + if (dock_err) printk(BIOS_ERR, "DOCK: Failed to init pc87382\n"); else dock_info(); - reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); - pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); - if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - gm45_early_reset(); - } + hybrid_graphics_init(sysinfo); +} - setup_pch_gpios(&mainboard_gpio_map); - - /* ASPM related setting, set early by original BIOS. */ - DMIBAR16(0x204) &= ~(3 << 10); - - /* Check for S3 resume. */ - const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); - if (((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } - - /* RAM initialization */ - enter_raminit_or_reset(); - memset(&sysinfo, 0, sizeof(sysinfo)); - sysinfo.spd_map[0] = 0x50; - sysinfo.spd_map[2] = 0x51; - get_gmch_info(&sysinfo); - - /* Configure graphic GPIOs. - * Make sure there's a little delay between - * setup_pch_gpios() and this call ! */ - hybrid_graphics_init(&sysinfo); - - raminit(&sysinfo, s3resume); - - const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); - /* Disable D4F0 (unknown signal controller). */ - pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); - - init_pm(&sysinfo, 0); - - i82801ix_dmi_setup(); - gm45_late_init(sysinfo.stepping); - i82801ix_dmi_poll_vc1(); - - MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; - - init_iommu(); - - /* FIXME: make a proper SMBUS mux support. */ +void mb_post_raminit_setup(void) +{ + /* FIXME: make a proper SMBUS mux support. */ + /* Set the SMBUS mux to the eeprom */ set_gpio(42, GPIO_LEVEL_LOW); - - cbmem_initted = !cbmem_recovery(s3resume); - - romstage_handoff_init(cbmem_initted && s3resume); - - printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index c011356..e8bbfb0 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -16,27 +16,15 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. -#include <stdint.h> -#include <string.h> #include <arch/io.h> -#include <arch/acpi.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/tsc.h> -#include <cpu/intel/romstage.h> -#include <cbmem.h> -#include <romstage_handoff.h> -#include <console/console.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) -#define MCH_DEV PCI_DEV(0, 0, 0) -static void early_lpc_setup(void) +void mb_setup_lpc(void) { - /* Set up SuperIO LPC forwards */ - /* Configure serial IRQs.*/ pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); /* Map COMa on 0x3f8, COMb on 0x2f8. */ @@ -47,82 +35,15 @@ pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); } -void mainboard_romstage_entry(unsigned long bist) +void get_mb_spd_addrmap(u8 *spd_addrmap) { - sysinfo_t sysinfo; - int s3resume = 0; - int cbmem_initted; - u16 reg16; + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x51; +} - /* basic northbridge setup, including MMCONF BAR */ - gm45_early_init(); - - if (bist == 0) - enable_lapic(); - - /* First, run everything needed for console output. */ - i82801ix_early_init(); - early_lpc_setup(); - console_init(); - printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist); - - reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); - pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); - if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - gm45_early_reset(); - } - - setup_pch_gpios(&mainboard_gpio_map); - - /* ASPM related setting, set early by original BIOS. */ - DMIBAR16(0x204) &= ~(3 << 10); - - /* Check for S3 resume. */ - const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); - if (((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } - - /* RAM initialization */ - enter_raminit_or_reset(); - memset(&sysinfo, 0, sizeof(sysinfo)); - sysinfo.spd_map[0] = 0x50; - sysinfo.spd_map[2] = 0x51; - sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; - get_gmch_info(&sysinfo); - raminit(&sysinfo, s3resume); - - const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); - /* Disable D4F0 (unknown signal controller). */ - pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); - - init_pm(&sysinfo, 0); - - i82801ix_dmi_setup(); - gm45_late_init(sysinfo.stepping); - i82801ix_dmi_poll_vc1(); - - MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; - - init_iommu(); - +void mb_post_raminit_setup(void) +{ /* FIXME: make a proper SMBUS mux support. */ + /* Set the SMBUS mux to the eeprom */ set_gpio(42, GPIO_LEVEL_LOW); - - cbmem_initted = !cbmem_recovery(s3resume); - - romstage_handoff_init(cbmem_initted && s3resume); - - printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index ff8bc87..742e2ee 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -16,17 +16,7 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ -#include <stdint.h> -#include <string.h> #include <arch/io.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include <cpu/intel/romstage.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include <romstage_handoff.h> -#include <console/console.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> @@ -35,7 +25,7 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) -static void early_lpc_setup(void) +void mb_setup_lpc(void) { /* Set up SuperIO LPC forwards */ @@ -47,7 +37,7 @@ pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03); } -static void default_superio_gpio_setup(void) +void mb_setup_superio(void) { /* Original settings: idx 30 31 32 33 34 35 36 37 38 39 @@ -87,81 +77,12 @@ /* Set GPIO output values: */ outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */ outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ + + lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -void mainboard_romstage_entry(unsigned long bist) +void get_mb_spd_addrmap(u8 *spd_addrmap) { - sysinfo_t sysinfo; - int s3resume = 0; - int cbmem_initted; - u16 reg16; - - /* basic northbridge setup, including MMCONF BAR */ - gm45_early_init(); - - if (bist == 0) - enable_lapic(); - - /* First, run everything needed for console output. */ - i82801ix_early_init(); - early_lpc_setup(); - default_superio_gpio_setup(); - lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist); - - reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); - pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); - if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - gm45_early_reset(); - } - - setup_pch_gpios(&mainboard_gpio_map); - - /* ASPM related setting, set early by original BIOS. */ - DMIBAR16(0x204) &= ~(3 << 10); - - /* Check for S3 resume. */ - const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); - if (((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } - - /* RAM initialization */ - enter_raminit_or_reset(); - memset(&sysinfo, 0, sizeof(sysinfo)); - get_gmch_info(&sysinfo); - sysinfo.spd_map[0] = 0x50; - sysinfo.spd_map[1] = 0; - sysinfo.spd_map[2] = 0x52; - sysinfo.spd_map[3] = 0; - sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; - raminit(&sysinfo, s3resume); - - init_pm(&sysinfo, 1); - - i82801ix_dmi_setup(); - gm45_late_init(sysinfo.stepping); - i82801ix_dmi_poll_vc1(); - - MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; - - init_iommu(); - - cbmem_initted = !cbmem_recovery(s3resume); - - romstage_handoff_init(cbmem_initted && s3resume); - - printk(BIOS_SPEW, "exit main()\n"); + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; } diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 95b360c..16a9ddb 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += pm.c romstage-y += ram_calc.c romstage-y += iommu.c +romstage-y += romstage.c ramstage-y += acpi.c diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 736d6af..0096793 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -436,6 +436,13 @@ void init_iommu(void); +/* romstage mainboard hookups */ +void mb_setup_lpc(void); +void mb_setup_superio(void); /* optional */ +void get_mb_spd_addrmap(u8 spd_addrmap[4]); +void mb_pre_raminit_setup(sysinfo_t *); /* optional */ +void mb_post_raminit_setup(void); /* optional */ + struct blc_pwm_t { char ascii_string[13]; int pwm_freq; /* In Hz */ diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c new file mode 100644 index 0000000..6d652bb --- /dev/null +++ b/src/northbridge/intel/gm45/romstage.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <romstage_handoff.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <northbridge/intel/gm45/gm45.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <southbridge/intel/common/gpio.h> + +#define LPC_DEV PCI_DEV(0, 0x1f, 0) +#define MCH_DEV PCI_DEV(0, 0, 0) + +void __weak mb_setup_superio(void) +{ +} + +void __weak mb_pre_raminit_setup(sysinfo_t *sysinfo) +{ +} + +void __weak mb_post_raminit_setup(void) +{ +} + +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ +void mainboard_romstage_entry(unsigned long bist) +{ + sysinfo_t sysinfo; + int s3resume = 0; + int cbmem_initted; + u16 reg16; + + /* basic northbridge setup, including MMCONF BAR */ + gm45_early_init(); + + if (bist == 0) + enable_lapic(); + + /* First, run everything needed for console output. */ + i82801ix_early_init(); + setup_pch_gpios(&mainboard_gpio_map); + + mb_setup_lpc(); + + mb_setup_superio(); + + console_init(); + report_bist_failure(bist); + + reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); + pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); + if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + gm45_early_reset(); + } + + /* ASPM related setting, set early by original BIOS. */ + DMIBAR16(0x204) &= ~(3 << 10); + + /* Check for S3 resume. */ + const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); + if (((pm1_cnt >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + + /* RAM initialization */ + enter_raminit_or_reset(); + memset(&sysinfo, 0, sizeof(sysinfo)); + get_mb_spd_addrmap(sysinfo.spd_map); + const struct device *dev; + dev = pcidev_on_root(2, 0); + if (dev) + sysinfo.enable_igd = dev->enabled; + dev = pcidev_on_root(1, 0); + if (dev) + sysinfo.enable_peg = dev->enabled; + get_gmch_info(&sysinfo); + + mb_pre_raminit_setup(&sysinfo); + + raminit(&sysinfo, s3resume); + + mb_post_raminit_setup(); + + const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); + /* Disable D4F0 (unknown signal controller). */ + pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); + + init_pm(&sysinfo, 0); + + i82801ix_dmi_setup(); + gm45_late_init(sysinfo.stepping); + i82801ix_dmi_poll_vc1(); + + MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; + + init_iommu(); + + cbmem_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_initted && s3resume); + + printk(BIOS_SPEW, "exit main()\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/lenovo/x200/gpio.c: Unclutter the code
by Arthur Heymans (Code Review) Feb. 6, 2019

Feb. 6, 2019

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31187 Change subject: mb/lenovo/x200/gpio.c: Unclutter the code ...................................................................... mb/lenovo/x200/gpio.c: Unclutter the code Some settings don't make sense like specifying input/output on native ports or direction on input ports. Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/gpio.c 1 file changed, 5 insertions(+), 186 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31187/1 diff --git a/src/mainboard/lenovo/x200/gpio.c b/src/mainboard/lenovo/x200/gpio.c index 5906fc3..2da4097 100644 --- a/src/mainboard/lenovo/x200/gpio.c +++ b/src/mainboard/lenovo/x200/gpio.c @@ -14,7 +14,6 @@ #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NATIVE, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -24,32 +23,19 @@ .gpio7 = GPIO_MODE_GPIO, .gpio8 = GPIO_MODE_GPIO, .gpio9 = GPIO_MODE_GPIO, - .gpio10 = GPIO_MODE_NATIVE, - .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_NATIVE, .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_NATIVE, - .gpio16 = GPIO_MODE_NATIVE, .gpio17 = GPIO_MODE_GPIO, .gpio18 = GPIO_MODE_GPIO, .gpio19 = GPIO_MODE_GPIO, .gpio20 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_GPIO, .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_NATIVE, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_NATIVE, }; const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, @@ -59,238 +45,71 @@ .gpio7 = GPIO_DIR_INPUT, .gpio8 = GPIO_DIR_INPUT, .gpio9 = GPIO_DIR_OUTPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_OUTPUT, .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_OUTPUT, - .gpio16 = GPIO_DIR_OUTPUT, .gpio17 = GPIO_DIR_INPUT, .gpio18 = GPIO_DIR_INPUT, .gpio19 = GPIO_DIR_OUTPUT, .gpio20 = GPIO_DIR_OUTPUT, .gpio21 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_OUTPUT, - .gpio26 = GPIO_DIR_OUTPUT, .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, }; const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_HIGH, .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_HIGH, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_HIGH, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_LOW, .gpio19 = GPIO_LEVEL_HIGH, .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_blink = { - .gpio0 = GPIO_NO_BLINK, - .gpio1 = GPIO_NO_BLINK, - .gpio2 = GPIO_NO_BLINK, - .gpio3 = GPIO_NO_BLINK, - .gpio4 = GPIO_NO_BLINK, - .gpio5 = GPIO_NO_BLINK, - .gpio6 = GPIO_NO_BLINK, - .gpio7 = GPIO_NO_BLINK, - .gpio8 = GPIO_NO_BLINK, - .gpio9 = GPIO_NO_BLINK, - .gpio10 = GPIO_NO_BLINK, - .gpio11 = GPIO_NO_BLINK, - .gpio12 = GPIO_NO_BLINK, - .gpio13 = GPIO_NO_BLINK, - .gpio14 = GPIO_NO_BLINK, - .gpio15 = GPIO_NO_BLINK, - .gpio16 = GPIO_NO_BLINK, - .gpio17 = GPIO_NO_BLINK, - .gpio18 = GPIO_NO_BLINK, - .gpio19 = GPIO_NO_BLINK, - .gpio20 = GPIO_NO_BLINK, - .gpio21 = GPIO_NO_BLINK, - .gpio22 = GPIO_NO_BLINK, - .gpio23 = GPIO_NO_BLINK, - .gpio24 = GPIO_NO_BLINK, - .gpio25 = GPIO_NO_BLINK, - .gpio26 = GPIO_NO_BLINK, - .gpio27 = GPIO_NO_BLINK, - .gpio28 = GPIO_NO_BLINK, - .gpio29 = GPIO_NO_BLINK, - .gpio30 = GPIO_NO_BLINK, - .gpio31 = GPIO_NO_BLINK, }; const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_NO_INVERT, - .gpio1 = GPIO_INVERT, - .gpio2 = GPIO_NO_INVERT, - .gpio3 = GPIO_NO_INVERT, - .gpio4 = GPIO_NO_INVERT, - .gpio5 = GPIO_NO_INVERT, - .gpio6 = GPIO_NO_INVERT, - .gpio7 = GPIO_NO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio9 = GPIO_NO_INVERT, - .gpio10 = GPIO_NO_INVERT, - .gpio11 = GPIO_NO_INVERT, - .gpio12 = GPIO_NO_INVERT, - .gpio13 = GPIO_NO_INVERT, - .gpio14 = GPIO_NO_INVERT, - .gpio15 = GPIO_NO_INVERT, - .gpio16 = GPIO_NO_INVERT, - .gpio17 = GPIO_NO_INVERT, - .gpio18 = GPIO_NO_INVERT, - .gpio19 = GPIO_NO_INVERT, - .gpio20 = GPIO_NO_INVERT, - .gpio21 = GPIO_NO_INVERT, - .gpio22 = GPIO_NO_INVERT, - .gpio23 = GPIO_NO_INVERT, - .gpio24 = GPIO_NO_INVERT, - .gpio25 = GPIO_NO_INVERT, - .gpio26 = GPIO_NO_INVERT, - .gpio27 = GPIO_NO_INVERT, - .gpio28 = GPIO_NO_INVERT, - .gpio29 = GPIO_NO_INVERT, - .gpio30 = GPIO_NO_INVERT, - .gpio31 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { }; const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_NATIVE, .gpio36 = GPIO_MODE_GPIO, .gpio37 = GPIO_MODE_GPIO, .gpio38 = GPIO_MODE_GPIO, .gpio39 = GPIO_MODE_GPIO, - .gpio40 = GPIO_MODE_NATIVE, .gpio41 = GPIO_MODE_GPIO, .gpio42 = GPIO_MODE_GPIO, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_NATIVE, - .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_NATIVE, - .gpio47 = GPIO_MODE_NATIVE, .gpio48 = GPIO_MODE_GPIO, .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_NATIVE, - .gpio51 = GPIO_MODE_NATIVE, - .gpio52 = GPIO_MODE_NATIVE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NATIVE, - .gpio55 = GPIO_MODE_NATIVE, .gpio56 = GPIO_MODE_GPIO, .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_NATIVE, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, }; const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, .gpio38 = GPIO_DIR_INPUT, .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, .gpio41 = GPIO_DIR_OUTPUT, .gpio42 = GPIO_DIR_OUTPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, .gpio48 = GPIO_DIR_INPUT, .gpio49 = GPIO_DIR_OUTPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_OUTPUT, .gpio56 = GPIO_DIR_INPUT, .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_OUTPUT, - .gpio62 = GPIO_DIR_OUTPUT, - .gpio63 = GPIO_DIR_OUTPUT, }; const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_HIGH, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, .gpio41 = GPIO_LEVEL_HIGH, .gpio42 = GPIO_LEVEL_HIGH, - .gpio43 = GPIO_LEVEL_HIGH, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_HIGH, - .gpio48 = GPIO_LEVEL_HIGH, .gpio49 = GPIO_LEVEL_HIGH, - .gpio50 = GPIO_LEVEL_HIGH, - .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_HIGH, - .gpio55 = GPIO_LEVEL_HIGH, - .gpio56 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_HIGH, - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, }; const struct pch_gpio_map mainboard_gpio_map = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b Gerrit-Change-Number: 31187 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/roda/rk9: Use common code to set up southbridge GPIO's
by Arthur Heymans (Code Review) Feb. 6, 2019

Feb. 6, 2019

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31186 Change subject: mb/roda/rk9: Use common code to set up southbridge GPIO's ...................................................................... mb/roda/rk9: Use common code to set up southbridge GPIO's Change-Id: I2057bf66435fd9113cdb1eef4c273f66b07a5a79 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/roda/rk9/Makefile.inc A src/mainboard/roda/rk9/gpio.c M src/mainboard/roda/rk9/romstage.c 3 files changed, 144 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31186/1 diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index f92382ee..7ff1588 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y = gpio.c + ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c ramstage-y += cstates.c ramstage-y += blc.c diff --git a/src/mainboard/roda/rk9/gpio.c b/src/mainboard/roda/rk9/gpio.c new file mode 100644 index 0000000..4e1ebe3 --- /dev/null +++ b/src/mainboard/roda/rk9/gpio.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index b88671c..ff8bc87 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <romstage_handoff.h> #include <console/console.h> +#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> #include <superio/smsc/lpc47n227/lpc47n227.h> @@ -34,32 +35,6 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) -static void default_southbridge_gpio_setup(void) -{ - /* Enable GPIOs [31:0]. */ - outl(0x197e7dfe, DEFAULT_GPIOBASE + 0x00); - /* Set input/output mode [31:0] (0 == out, 1 == in). */ - outl(0xe0ea43fe, DEFAULT_GPIOBASE + 0x04); - /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT, - WLAN, ~ANTMUX, ~GPIO12, - ~SUSPWR, SMBALERT) */ - outl(0x00000800, DEFAULT_GPIOBASE + 0x0c); - - /* Disable blink [31:0]. */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); - /* Set input inversion [31:0]. */ - outl(0x00000182, DEFAULT_GPIOBASE + 0x2c); - - /* Enable GPIOs [60:32]. */ - outl(0x130300fe, DEFAULT_GPIOBASE + 0x30); - /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x0e55ffb0, DEFAULT_GPIOBASE + 0x34); - /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO, - DMITERM, TXT, ~CLKSATA, - GPS, AUDIO) */ - outl(0x10020042, DEFAULT_GPIOBASE + 0x38); -} - static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -142,7 +117,7 @@ gm45_early_reset(); } - default_southbridge_gpio_setup(); + setup_pch_gpios(&mainboard_gpio_map); /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); -- To view, visit https://review.coreboot.org/c/coreboot/+/31186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2057bf66435fd9113cdb1eef4c273f66b07a5a79 Gerrit-Change-Number: 31186 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions
by Patrick Georgi (Code Review) Feb. 6, 2019

Feb. 6, 2019

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31189 ) Change subject: mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions ...................................................................... mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions Change-Id: I1e9a165b722006557557058a14e9f5dac78d4538 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31189 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 5020c85..44f560b 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -147,7 +147,7 @@ init_iommu(); /* FIXME: make a proper SMBUS mux support. */ - outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); + set_gpio(42, GPIO_LEVEL_LOW); cbmem_initted = !cbmem_recovery(s3resume); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index a0a1ace..c011356 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -118,7 +118,7 @@ init_iommu(); /* FIXME: make a proper SMBUS mux support. */ - outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); + set_gpio(42, GPIO_LEVEL_LOW); cbmem_initted = !cbmem_recovery(s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/31189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e9a165b722006557557058a14e9f5dac78d4538 Gerrit-Change-Number: 31189 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/lenovo/t400: Remove RCBA replay
by Arthur Heymans (Code Review) Feb. 6, 2019

Feb. 6, 2019

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31188 Change subject: mb/lenovo/t400: Remove RCBA replay ...................................................................... mb/lenovo/t400: Remove RCBA replay his either sets unwanted or unnecessary settings. Also this RCBA replay did not even originate from the T400 as this code was copied from the Thinkpad x200 code on which this replay was already removed in 7bcd062 'mb/lenovo/x200: Remove RCBA replay' Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/romstage.c 1 file changed, 0 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31188/1 diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 1a708ae..5020c85 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -143,39 +143,6 @@ i82801ix_dmi_poll_vc1(); MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; - /* Enable ethernet. */ - RCBA32(0x3414) &= ~0x20; - - RCBA32(0x0238) = 0x00543210; - RCBA32(0x0240) = 0x009c0b02; - RCBA32(0x0244) = 0x00a20b1a; - RCBA32(0x0248) = 0x005402cb; - RCBA32(0x0254) = 0x00470966; - RCBA32(0x0258) = 0x00470473; - RCBA32(0x0260) = 0x00e90825; - RCBA32(0x0278) = 0x00bc0efb; - RCBA32(0x027c) = 0x00c00f0b; - RCBA32(0x0280) = 0x00670000; - RCBA32(0x0284) = 0x006d0000; - RCBA32(0x0288) = 0x00600b4e; - RCBA32(0x1e10) = 0x00020800; - RCBA32(0x1e18) = 0x36ea00a0; - RCBA32(0x1e80) = 0x000c0801; - RCBA32(0x1e84) = 0x000200f0; - RCBA32(0x2028) = 0x04c8f95e; - RCBA32(0x202c) = 0x055c095e; - RCBA32(0x204c) = 0x001ffc00; - RCBA32(0x2050) = 0x00100fff; - RCBA32(0x2090) = 0x37000000; - RCBA32(0x20b0) = 0x0c000000; - RCBA32(0x20d0) = 0x09000000; - RCBA32(0x20f0) = 0x05000000; - RCBA32(0x3400) = 0x0000001c; - RCBA32(0x3410) = 0x00100461; - RCBA32(0x3414) = 0x00000000; - RCBA32(0x341c) = 0xbf4f001f; - RCBA32(0x3420) = 0x00000000; - RCBA32(0x3430) = 0x00000001; init_iommu(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64 Gerrit-Change-Number: 31188 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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