coreboot-gerrit February 2019

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Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Frans Hendriks (Code Review) 08 Feb '19

08 Feb '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30414 to look at the new patch set (#13). Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... mainboard/facebook/fbg1701: Do initial mainboard commit Create Facebook FBG-1701 coreboot implementation coreboot implementation is prepared for Bootblock, measured boot and verified boot support. These features are default disabled. This Braswell implementation is based on Intel Strago. Additional modifiiciation included: - Move Winbond defines to include - Add SMBus support for Braswell BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A Documentation/mainboard/facebook/fbg1701.md M Documentation/mainboard/index.md A src/drivers/spi/spi_winbond.h M src/drivers/spi/winbond.c A src/mainboard/facebook/fbg1701/Kconfig A src/mainboard/facebook/fbg1701/Kconfig.name A src/mainboard/facebook/fbg1701/Makefile.inc A src/mainboard/facebook/fbg1701/acpi/dptf.asl A src/mainboard/facebook/fbg1701/acpi/ec.asl A src/mainboard/facebook/fbg1701/acpi/mainboard.asl A src/mainboard/facebook/fbg1701/acpi/sleepstates.asl A src/mainboard/facebook/fbg1701/acpi/superio.asl A src/mainboard/facebook/fbg1701/acpi_tables.c A src/mainboard/facebook/fbg1701/board_info.txt A src/mainboard/facebook/fbg1701/board_mboot.c A src/mainboard/facebook/fbg1701/board_verified_boot.c A src/mainboard/facebook/fbg1701/board_verified_boot.h A src/mainboard/facebook/fbg1701/bootblock.c A src/mainboard/facebook/fbg1701/cmos.layout A src/mainboard/facebook/fbg1701/com_init.c A src/mainboard/facebook/fbg1701/devicetree.cb A src/mainboard/facebook/fbg1701/dsdt.asl A src/mainboard/facebook/fbg1701/fadt.c A src/mainboard/facebook/fbg1701/fmap.fmd A src/mainboard/facebook/fbg1701/gpio.c A src/mainboard/facebook/fbg1701/hda_verb.c A src/mainboard/facebook/fbg1701/irqroute.c A src/mainboard/facebook/fbg1701/irqroute.h A src/mainboard/facebook/fbg1701/logo.c A src/mainboard/facebook/fbg1701/mainboard.c A src/mainboard/facebook/fbg1701/mainboard.h A src/mainboard/facebook/fbg1701/manifest.h A src/mainboard/facebook/fbg1701/onboard.h A src/mainboard/facebook/fbg1701/ramstage.c A src/mainboard/facebook/fbg1701/romstage.c A src/mainboard/facebook/fbg1701/smihandler.c A src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/facebook/fbg1701/w25q64.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/include/soc/pci_devs.h A src/soc/intel/braswell/include/soc/smbus.h A src/soc/intel/braswell/smbus.c 42 files changed, 3,057 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30414/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 13 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Frans Hendriks (Code Review) 08 Feb '19

08 Feb '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/30414/12/src/mainboard/facebook/fbg1701/boo… File src/mainboard/facebook/fbg1701/bootblock.c: https://review.coreboot.org/#/c/30414/12/src/mainboard/facebook/fbg1701/boo… PS12, Line 27: # > Will change using compiler in update. Changing now will result in build error, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 08 Feb 2019 08:47:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: add PC Engines to the list of distributors
by Martin Kepplinger (Code Review) 08 Feb '19

08 Feb '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31264 Change subject: Documentation: add PC Engines to the list of distributors ...................................................................... Documentation: add PC Engines to the list of distributors As suggested by Philipp, add PC Engines to the list. Change-Id: I2f5a3943d2ab8d79f338abb27eb805fd975e4afa Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M Documentation/distributions.md 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31264/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index b3b9dac..a926917 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -29,6 +29,11 @@ [Libretrend](https://libretrend.com) sells the Librebox, a NUC-like PC which ships with coreboot firmware. +### PC Engines + +[PC Engines](https://pcengines.ch/) develops and sells small, low power single +board computers for networking. They use coreboot as the main system firmware. + ## After-market firmware -- To view, visit https://review.coreboot.org/c/coreboot/+/31264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f5a3943d2ab8d79f338abb27eb805fd975e4afa Gerrit-Change-Number: 31264 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cheza: configure gpios and gcc clocks for sound
by Julius Werner (Code Review) 08 Feb '19

08 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31083 ) Change subject: cheza: configure gpios and gcc clocks for sound ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/bootblock.c File src/soc/qualcomm/sdm845/bootblock.c: https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/bootblock.c… PS1, Line 29: sdm845_sound_init(); Any specific reason this must be done in the bootblock? If not, please do it in ramstage (from mainboard.c, since it's board-specific whether we actually want it). https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/sound.c File src/soc/qualcomm/sdm845/sound.c: https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/sound.c@30 PS1, Line 30: GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT); Which I2S bus to use is board-specific, so this function has to go into mainboard.c. https://review.coreboot.org/#/c/31083/1/src/soc/qualcomm/sdm845/sound.c@46 PS1, Line 46: write32((void *)GCC_LPASS_Q6_AXI_CBCR, 0x80000001); This function should be implemented in clock.c and use the GCC register overlay from there. -- To view, visit https://review.coreboot.org/c/coreboot/+/31083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I130c4a0df88d0825debfa8e5c22a31f30be70df6 Gerrit-Change-Number: 31083 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Feb 2019 00:44:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: Mention PC Engines as ships-with-coreboot hardware
by Patrick Georgi (Code Review) 07 Feb '19

07 Feb '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31259 Change subject: Documentation: Mention PC Engines as ships-with-coreboot hardware ...................................................................... Documentation: Mention PC Engines as ships-with-coreboot hardware Change-Id: I9d57abcff9c2472cc58b7fbca00441cd38a7f1a1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/distributions.md 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31259/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index eaa61be..53fbf867 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -29,6 +29,13 @@ ships with coreboot firmware. +### PC Engines APUs + +[PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that +ships with coreboot and support upstream maintenance for the devices through a +third party, [3mdeb](https://3mdeb.com). They provide current and tested +firmware binaries on [GitHub](https://pcengines.github.io). + ## After-market firmware ### Libreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/31259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d57abcff9c2472cc58b7fbca00441cd38a7f1a1 Gerrit-Change-Number: 31259 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Add UART support
by Julius Werner (Code Review) 07 Feb '19

07 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25373 ) Change subject: sdm845: Add UART support ...................................................................... Patch Set 64: (8 comments) https://review.coreboot.org/#/c/25373/64/src/mainboard/google/cheza/Kconfig File src/mainboard/google/cheza/Kconfig: https://review.coreboot.org/#/c/25373/64/src/mainboard/google/cheza/Kconfig… PS64, Line 24: default 0x00A84000 Since this is used by the SoC code it should also be defined in sdm845/Kconfig, so that this definition here is just overriding the default for that definition there. You should also add a short help text there to explain what it is. I think it may be easier to just use an int Kconfig for the QUP number (1 through 15) rather than the base address, since you'll also need to call clock_enable_qup() in your init function (we want to get rid of CB:29489 at some point), and the base address doesn't really work from there. You can use the 'qup' structure defined in sdm845/qcom_qup_se.c (already used by the SPI and I2C stuff) to get the base address from the QUP number. https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c File src/soc/qualcomm/sdm845/uart.c: https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@120 PS64, Line 120: GENI_FW_REVISION_RO_REG This is still not using a struct overlay. Please use the QUP register struct overlay that was now added by the SPI/I2C code with the 'qup' structure in sdm845/qcom_qup_se.c and sdm845/include/soc/qcom_qup_se.h. https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@128 PS64, Line 128: * we are discussing with clock team */ How is this coming along? Ideally you should be using get_uart_baudrate() and approximate the clock rate there as best as you can with the divisors you have. https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@134 PS64, Line 134: write32((void *)0x00118148, 0x1); /* Update the clock */ These are all GCC registers, right? This driver shouldn't update them itself. It should make a call to some clock.c function that does that (probably clock_configure_qup()?). https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@142 PS64, Line 142: gpio_configure(GPIO(5), 1, GPIO_PULL_UP, GPIO_2MA, GPIO_INPUT); This needs to be dependent on the QUP you're actually using... the global 'qup' struct has the info for this, too (compare similar code for SPI and I2C drivers). https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@147 PS64, Line 147: * configuration Can we put this check at the top of this function? Presumably, if the previous stage has set up this it has probably also run all the other setup before this point. https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@213 PS64, Line 213: if (uart_initialized == false) { This should be unnecessary. You can rely on the framework calling uart_init() before the first call to uart_tx_byte(). https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@245 PS64, Line 245: } There's no need for all these wrapper functions. Just put the code from uart_qupv3_init() directly into the body of uart_init(), etc. -- To view, visit https://review.coreboot.org/c/coreboot/+/25373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1 Gerrit-Change-Number: 25373 Gerrit-PatchSet: 64 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Feb 2019 22:26:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Port I2C driver
by Julius Werner (Code Review) 07 Feb '19

07 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 24: (10 comments) https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… File src/mainboard/google/cheza/mainboard.c: https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… PS24, Line 42: i2c_init(12, 400 * KHz, 1); This should be an enum (QUP_WRAP1_S4 or something like that). Should probably pull the one from clock.h into qcom_qup_se.h and use it everywhere. https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c File src/soc/qualcomm/sdm845/i2c.c: https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@46 PS24, Line 46: unsigned int hz, unsigned int idx Let's not pass both Hz and an index. If you only want to use those three set operating points (I think for I2C that's fine since frequencies are very standardized there), just combine these into a single enum parameter (and name the enum values I2C_100KHZ, I2C_400KHZ, I2C_1MHZ or something like that). https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@101 PS24, Line 101: BITS_PER_WORD >> 4 How exactly does this work? When it says byte_granularity I would expect 1 means 1 byte, 2 means 2 bytes, etc... but 8 >> 4 is actually 0. Is that really what you wanted? And would this still work if BITS_PER_WORD was 16 (so this would become 1), 32 (this would become 2) or 64 (this would be 4)? https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@118 PS24, Line 118: setbits_le32(&regs->geni_s_irq_enable, S_CMD_DONE_EN); Why not combine this with the other write to that register above? https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@122 PS24, Line 122: static u32 wait_till_irq_set(unsigned int bus) This is the exact same function as in the SPI code, right? Let's put it in qup.c so both drivers can share it. https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@187 PS24, Line 187: static void i2c_handle_error(unsigned int bus) Actually... I think everything up to an including this function is 100% identical with SPI? Let's please merge all of that into single copies in qup.c. https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@228 PS24, Line 228: stopwatch_init_msecs_expire(&sw, 1000); ...and I think we can also factor out this loop (including the error checking) into a separate function that can be shared with the SPI code. https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@245 PS24, Line 245: (m_irq & M_CMD_DONE_EN) nit: Can remove this part of the check. !A || (A && B) is logically equivalent to just !A || B https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@247 PS24, Line 247: printk(BIOS_INFO, "%s:Error: Transfer failed\n", __func__); nit: Please write as "ERROR: %s failed\n". We like having ERROR: at the start of the line to make it easily noticeable. Also, printk level should probably be BIOS_ERR. https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@261 PS24, Line 261: /* Set stretch = 0 for the last transfer */ Please also explain what that bit does and why it needs to be set only for the last transfer. -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 24 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 07 Feb 2019 21:08:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] mb/google/hatch: Enable DPTF functionality
by Sumeet R Pawnikar (Code Review) 07 Feb '19

07 Feb '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31275 Change subject: [WIP] mb/google/hatch: Enable DPTF functionality ...................................................................... [WIP] mb/google/hatch: Enable DPTF functionality Enable DPTF functionality on hatch platform. Change-Id: Ibde1db06911074520bd8c641824305dee7dbbc43 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/baseboard/devicetree.cb A src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl 4 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31275/1 diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 93f7fc0..e6321ba 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -59,4 +59,15 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f2..aaef663 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -57,6 +57,11 @@ register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "44" + register "Device4Enable" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..5e3de83 --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +#endif +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/31275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibde1db06911074520bd8c641824305dee7dbbc43 Gerrit-Change-Number: 31275 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: fix tabs for Makefile
by Shelley Chen (Code Review) 07 Feb '19

07 Feb '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31273 Change subject: fix tabs for Makefile ...................................................................... fix tabs for Makefile Change-Id: Ia65fe3a89513464b18813f68b86caa3f1494c296 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31273/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc index e474ad2..074fc54 100644 --- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -13,12 +13,12 @@ ## GNU General Public License for more details. ## -SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES = 4G_2400 # 0b000 SPD_SOURCES += empty_ddr4 # 0b001 SPD_SOURCES += empty_ddr4 # 0b010 SPD_SOURCES += empty_ddr4 # 0b011 SPD_SOURCES += empty_ddr4 # 0b100 -SPD_SOURCES += 8G_2666 # 0b101 +SPD_SOURCES += 8G_2666 # 0b101 bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia65fe3a89513464b18813f68b86caa3f1494c296 Gerrit-Change-Number: 31273 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Nico Huber (Code Review) 07 Feb '19

07 Feb '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 3: Code-Review+1 (3 comments) +2 to Felix' changes https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@119 PS2, Line 119: "CNV_BRI_DT", "*GPIO_216", "n/a", "n/a", "n/a", "n/a", > How did you find out that this pad belongs to GPIO_216 from the GPIO multiplexing table (p. […] Table 2-34, Community Offset column https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@120 PS2, Line 120: "CNV_BRI_RSP", "*GPIO_217", "n/a", "n/a", "n/a", "n/a", > Same here Done https://review.coreboot.org/#/c/29897/2/util/inteltool/gpio_groups.c@121 PS2, Line 121: "CNV_RGI_DT", "*GPIO_218", "n/a", "n/a", "n/a", "n/a", > Same here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Feb 2019 14:34:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: comment

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coreboot-gerrit February 2019