coreboot-gerrit February 2019

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Julius Werner (Code Review) 12 Feb '19

12 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 49: I think this looks good now if you make it build and clean up the Jenkins stuff (at least the 80 chars... the BUG() warning is stupid and we should probably disable it or replace those with die() or something). (I still think it would be nice to factor out that stage measurement into a separate function, though.) -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 49 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Feb 2019 21:59:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Julius Werner (Code Review) 12 Feb '19

12 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 49: (2 comments) https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@3… PS49, Line 319: if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && !vboot_platform_is_resuming()) { I think it would be cleaner to just check the flag rather than calling platform_is_resuming() twice (since it's platform specific you don't know how expensive it might be). You just need to put the right boolean operators in the check. https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@3… PS49, Line 353: extend_pcrs(&ctx); /* ignore failures */ Why did you change all of these? I think the tab there was intentional to make it more readable. -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 49 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Feb 2019 21:57:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Furquan Shaikh (Code Review) 12 Feb '19

12 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31375 ) Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/31375/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31375/2//COMMIT_MSG@10 PS2, Line 10: SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose Can you please add details indicating that this UPD defaults to 2 if not set and hence it needs to be initialized as per this config. https://review.coreboot.org/#/c/31375/2/src/soc/intel/cannonlake/fsp_params… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/#/c/31375/2/src/soc/intel/cannonlake/fsp_params… PS2, Line 166: * space after * https://review.coreboot.org/#/c/31375/2/src/soc/intel/cannonlake/fsp_params… PS2, Line 166: * space before * -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Feb 2019 21:46:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Felix Singer (Code Review) 12 Feb '19

12 Feb '19

Felix Singer has uploaded a new patch set (#6) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c 2 files changed, 354 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29897/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: fintek/f81803a: Add new superio - Fintek F81803A
by Kyösti Mälkki (Code Review) 12 Feb '19

12 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21032 ) Change subject: fintek/f81803a: Add new superio - Fintek F81803A ...................................................................... Patch Set 9: Marshall, please advice Richard to reuse these padmelon Change-IDs, where applicable. Seems to me community already did some reviews on the superio part at least. -- To view, visit https://review.coreboot.org/c/coreboot/+/21032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fb1a1d42d004123c3b12caf26cf0b03cd4046ec Gerrit-Change-Number: 21032 Gerrit-PatchSet: 9 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Feb 2019 17:37:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by build bot (Jenkins) (Code Review) 12 Feb '19

12 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 49: (7 comments) https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@98 PS49, Line 98: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@1… PS49, Line 104: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@2… PS49, Line 281: return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); line over 80 characters https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@3… PS49, Line 308: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) line over 80 characters https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@3… PS49, Line 319: if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && !vboot_platform_is_resuming()) { line over 80 characters https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@3… PS49, Line 324: if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) line over 80 characters https://review.coreboot.org/#/c/29547/49/src/security/vboot/vboot_logic.c@3… PS49, Line 333: if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 49 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Feb 2019 16:15:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by build bot (Jenkins) (Code Review) 12 Feb '19

12 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 48: (7 comments) https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c@98 PS48, Line 98: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c@1… PS48, Line 104: BUG(); /* Should never get called if init() returned an error. */ Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c@2… PS48, Line 281: return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); line over 80 characters https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c@3… PS48, Line 308: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) line over 80 characters https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c@3… PS48, Line 319: if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && !vboot_platform_is_resuming()) { line over 80 characters https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c@3… PS48, Line 324: if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) line over 80 characters https://review.coreboot.org/#/c/29547/48/src/security/vboot/vboot_logic.c@3… PS48, Line 333: if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 48 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Feb 2019 16:14:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Philipp Deppenwiese (Code Review) 12 Feb '19

12 Feb '19

Hello Patrick Rudolph, Aaron Durbin, Piotr Król, Julius Werner, Krystian Hebel, Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Werner Zeh, Huang Jin, York Yang, David Hendricks, Martin Roth, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29547 to look at the new patch set (#48). Change subject: security/vboot: Add measured boot mode ...................................................................... security/vboot: Add measured boot mode * Introduce a measured boot mode into vboot. * Add hook for stage measurements in prog_ops. * Implement and hook-up CRTM in vboot and check for suspend. * Documentation will be done in a follow up Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/lib/prog_ops.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc A src/security/vboot/vboot_crtm.c A src/security/vboot/vboot_crtm.h M src/security/vboot/vboot_logic.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M util/abuild/abuild 19 files changed, 273 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29547/48 -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 48 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: postcar: Make more use of postcar_frame_add_romcache()
by Nico Huber (Code Review) 12 Feb '19

12 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31320 Change subject: postcar: Make more use of postcar_frame_add_romcache() ...................................................................... postcar: Make more use of postcar_frame_add_romcache() Some similar calls to postcar_frame_add_mtrr() were added in the meantime or were under review while postcar_frame_add_romcache() was introduced. Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/haswell/romstage.c M src/northbridge/intel/i440bx/ram_calc.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 4 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31320/1 diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9b9f156..cfc4a13 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -55,8 +55,7 @@ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE_C, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 50e0a0d..962f3ba 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -81,8 +81,7 @@ die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE_C, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a2bf938..8de6700 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -249,8 +249,7 @@ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE_C, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index add0b47..0cbc8c2 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -47,8 +47,7 @@ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE_C, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); -- To view, visit https://review.coreboot.org/c/coreboot/+/31320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198 Gerrit-Change-Number: 31320 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: binaryPI: Drop nested northbridge in devicetree
by Kyösti Mälkki (Code Review) 12 Feb '19

12 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31271 Change subject: binaryPI: Drop nested northbridge in devicetree ...................................................................... binaryPI: Drop nested northbridge in devicetree SPD data needs to remain within same chip -block with device 0:18.2. Change-Id: Ic12481b637ee5f5119faec3239b477f613e4e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/devicetree.cb M src/mainboard/amd/db-ft3b-lc/devicetree.cb M src/mainboard/amd/lamar/devicetree.cb M src/mainboard/amd/olivehillplus/devicetree.cb M src/mainboard/bap/ode_e21XX/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb 9 files changed, 491 insertions(+), 501 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31271/1 diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb index a259e92..84aaf41 100644 --- a/src/mainboard/amd/bettong/devicetree.cb +++ b/src/mainboard/amd/bettong/devicetree.cb @@ -21,53 +21,54 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00660F01 # CPU side of HT root complex - chip northbridge/amd/pi/00660F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - device pci 3.0 on end # Edge Connector - device pci 3.1 on end # Edge Connector - end #chip northbridge/amd/pi/00660F01 + chip northbridge/amd/pi/00660F01 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + device pci 3.0 on end # Edge Connector + device pci 3.1 on end # Edge Connector + end #chip northbridge/amd/pi/00660F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 9.0 on end # HDA - device pci 9.2 on end # HDA - device pci 10.0 on end # USB - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - #device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/pi/hudson + chip southbridge/amd/pi/hudson + device pci 9.0 on end # HDA + device pci 9.2 on end # HDA + device pci 10.0 on end # USB + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + #device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/pi/hudson + chip northbridge/amd/pi/00660F01 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + register "spdAddrLookup" = " { { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/pi/00660F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00660F01/root_complex diff --git a/src/mainboard/amd/db-ft3b-lc/devicetree.cb b/src/mainboard/amd/db-ft3b-lc/devicetree.cb index 1faebf4..dfbe3e2 100644 --- a/src/mainboard/amd/db-ft3b-lc/devicetree.cb +++ b/src/mainboard/amd/db-ft3b-lc/devicetree.cb @@ -22,42 +22,40 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 off end # Edge Connector - device pci 2.5 off end # Edge Connector - device pci 8.0 off end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 off end # Edge Connector + device pci 2.5 off end # Edge Connector + device pci 8.0 off end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI #0 - device pci 13.0 on end # EHCI #1 - device pci 14.0 on end # SMBus - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # EHCI #2 - register "sd_mode" = "3" - end #chip southbridge/amd/pi/hudson + chip southbridge/amd/pi/hudson + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI #0 + device pci 13.0 on end # EHCI #1 + device pci 14.0 on end # SMBus + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + device pci 16.0 on end # EHCI #2 + register "sd_mode" = "3" + end #chip southbridge/amd/pi/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb index 593f95b..d7f3f05 100644 --- a/src/mainboard/amd/lamar/devicetree.cb +++ b/src/mainboard/amd/lamar/devicetree.cb @@ -22,81 +22,81 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00630F01 # CPU side of HT root complex - chip northbridge/amd/pi/00630F01 # PCI side of HT root complex - device pci 0.0 on end # 0x1422 Root Complex - device pci 0.2 off end # 0x1423 IOMMU - device pci 1.0 on end # 0x13XX Internal Graphics - device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio - device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge - device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) - device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 - device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge - device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) - device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) - device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 - device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 - device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 - device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge + chip northbridge/amd/pi/00630F01 + device pci 0.0 on end # 0x1422 Root Complex + device pci 0.2 off end # 0x1423 IOMMU + device pci 1.0 on end # 0x13XX Internal Graphics + device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio + device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge + device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) + device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 + device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge + device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) + device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) + device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 + device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 + device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 + device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge # device pci 4.1 on end # 0x1426 P2P bridge for UMI link # device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 # device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 # device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 # device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 - end #chip northbridge/amd/pi/00630F01 + end #chip northbridge/amd/pi/00630F01 - chip southbridge/amd/pi/hudson - device pci 10.0 on end # 0x7814 XHCI HC0 - device pci 10.1 on end # 0x7814 XHCI HC1 - device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) - device pci 12.0 on end # 0x7807 USB OHCI - device pci 12.2 on end # 0x7808 USB EHCI - device pci 13.0 on end # 0x7807 USB OHCI - device pci 13.2 on end # 0x7808 USB EHCI - device pci 14.0 on # 0x780B SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/pi/hudson + device pci 10.0 on end # 0x7814 XHCI HC0 + device pci 10.1 on end # 0x7814 XHCI HC1 + device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) + device pci 12.0 on end # 0x7807 USB OHCI + device pci 12.2 on end # 0x7808 USB EHCI + device pci 13.0 on end # 0x7807 USB OHCI + device pci 13.2 on end # 0x7808 USB EHCI + device pci 14.0 on # 0x780B SMBus + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # 0x780C IDE + device pci 14.2 on end # 0x780D HDA + device pci 14.3 on # 0x780E LPC + chip superio/fintek/f81216h + register "conf_key_mode" = "0x77" + device pnp 4e.0 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # 0x780C IDE - device pci 14.2 on end # 0x780D HDA - device pci 14.3 on # 0x780E LPC - chip superio/fintek/f81216h - register "conf_key_mode" = "0x77" - device pnp 4e.0 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.1 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.2 off end # COM3 - device pnp 4e.3 off end # COM4 - device pnp 4e.8 off end # WDT - end # f81865f - end #LPC - device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. - device pci 14.5 on end # 0x7809 USB OHCI - device pci 14.7 on end # 0x7806 SD Flash Controller - device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) - device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) - device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) - device pci 15.3 off end # 0x43A3 SB GPP Port 3 - register "gpp_configuration" = "4" - device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) - end #southbridge/amd/pi/hudson + device pnp 4e.2 off end # COM3 + device pnp 4e.3 off end # COM4 + device pnp 4e.8 off end # WDT + end # f81865f + end #LPC + device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. + device pci 14.5 on end # 0x7809 USB OHCI + device pci 14.7 on end # 0x7806 SD Flash Controller + device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) + device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) + device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) + device pci 15.3 off end # 0x43A3 SB GPP Port 3 + register "gpp_configuration" = "4" + device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) + end #southbridge/amd/pi/hudson + chip northbridge/amd/pi/00630F01 device pci 18.0 on end # 0x141A HT Configuration device pci 18.1 on end # 0x141B Address Maps device pci 18.2 on end # 0x141C DRAM Configuration @@ -108,7 +108,7 @@ { { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/pi/00630F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00630F01/root_complex diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index ee0cd98..430b17b 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -21,52 +21,53 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI #0 - device pci 13.0 on end # EHCI #1 - device pci 14.0 on # SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SMbus - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # EHCI #2 - end #chip southbridge/amd/pi/hudson + chip southbridge/amd/pi/hudson + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI #0 + device pci 13.0 on end # EHCI #1 + device pci 14.0 on # SMBus + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SMbus + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + device pci 16.0 on end # EHCI #2 + end #chip southbridge/amd/pi/hudson + chip northbridge/amd/pi/00730F01 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + register "spdAddrLookup" = " { { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/bap/ode_e21XX/devicetree.cb b/src/mainboard/bap/ode_e21XX/devicetree.cb index 04b0932..021ee90 100644 --- a/src/mainboard/bap/ode_e21XX/devicetree.cb +++ b/src/mainboard/bap/ode_e21XX/devicetree.cb @@ -21,96 +21,94 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # PCIe Q7 Realtek GBit LAN - device pci 2.3 on end # PCIe CB Realtek GBit LAN - device pci 2.4 on end # PCIe x2 BAP FPGA - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # PCIe Q7 Realtek GBit LAN + device pci 2.3 on end # PCIe CB Realtek GBit LAN + device pci 2.4 on end # PCIe x2 BAP FPGA + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI #0 - device pci 13.0 on end # EHCI #1 - device pci 14.0 on end # SMBus - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81866d - register "hwm_amd_tsi_addr" = "0x98" # Set to AMD - register "hwm_amd_tsi_control" = "0x02" # Set to AMD - register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM - register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode - register "hwm_fan3_control" = "0x00" # Fan control 23kHz - register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz - register "hwm_fan2_bound1" = "0x3C" # 60°C - register "hwm_fan2_bound2" = "0x32" # 50°C - register "hwm_fan2_bound3" = "0x28" # 40°C - register "hwm_fan2_bound4" = "0x1E" # 30°C - register "hwm_fan2_seg1_speed" = "0xFF" # 100% - register "hwm_fan2_seg2_speed" = "0xD9" # 85% - register "hwm_fan2_seg3_speed" = "0xB2" # 70% - register "hwm_fan2_seg4_speed" = "0x99" # 60% - register "hwm_fan2_seg5_speed" = "0x80" # 50% - register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 on # Hardware Monitor - io 0x60 = 0x295 - irq 0x70 = 0 - end - device pnp 4e.5 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.7 on end # WDT - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.12 off # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 4e.13 off # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 4e.14 off # COM5 - end - device pnp 4e.15 off # COM6 - end - end # f81866d - end #LPC - device pci 14.7 on end # SD - end #chip southbridge/amd/pi/hudson + chip southbridge/amd/pi/hudson + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI #0 + device pci 13.0 on end # EHCI #1 + device pci 14.0 on end # SMBus + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81866d + register "hwm_amd_tsi_addr" = "0x98" # Set to AMD + register "hwm_amd_tsi_control" = "0x02" # Set to AMD + register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM + register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode + register "hwm_fan3_control" = "0x00" # Fan control 23kHz + register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz + register "hwm_fan2_bound1" = "0x3C" # 60°C + register "hwm_fan2_bound2" = "0x32" # 50°C + register "hwm_fan2_bound3" = "0x28" # 40°C + register "hwm_fan2_bound4" = "0x1E" # 30°C + register "hwm_fan2_seg1_speed" = "0xFF" # 100% + register "hwm_fan2_seg2_speed" = "0xD9" # 85% + register "hwm_fan2_seg3_speed" = "0xB2" # 70% + register "hwm_fan2_seg4_speed" = "0x99" # 60% + register "hwm_fan2_seg5_speed" = "0x80" # 50% + register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.7 on end # WDT + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 off # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 4e.13 off # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 4e.14 off # COM5 + end + device pnp 4e.15 off # COM6 + end + end # f81866d + end #LPC + device pci 14.7 on end # SD + end #chip southbridge/amd/pi/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 2905e2c..6728228 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -21,74 +21,72 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.2 on end # LAN3 + device pci 2.3 on end # LAN2 + device pci 2.4 on end # LAN1 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 off end # USB EHCI0 usb[0:3] not connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 on - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 on - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 on end - device pnp 2e.107 on end - device pnp 2e.607 off end - device pnp 2e.e off end - end # SIO NCT5104D - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end # LPC TPM - end # LPC 0x439d + chip southbridge/amd/pi/hudson + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 off end # USB EHCI0 usb[0:3] not connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM + end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson + device pci 14.7 on end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 4da123e..0c0c21e 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -21,71 +21,69 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.2 on end # LAN3 + device pci 2.3 on end # LAN2 + device pci 2.4 on end # LAN1 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 on - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 on - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 on end - device pnp 2e.107 on end - device pnp 2e.607 off end - device pnp 2e.e off end - end # SIO NCT5104D - end # LPC 0x439d + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI0 usb[0:3] is connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson + device pci 14.7 on end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index b95afab..c93c04f 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -21,71 +21,69 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # LAN1 - device pci 2.2 on end # LAN2 - device pci 2.3 on end # LAN3 - device pci 2.4 on end # LAN4 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # LAN1 + device pci 2.2 on end # LAN2 + device pci 2.3 on end # LAN3 + device pci 2.4 on end # LAN4 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 on - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 on - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 on end - device pnp 2e.107 on end - device pnp 2e.607 off end - device pnp 2e.e off end - end # SIO NCT5104D - end # LPC 0x439d + chip southbridge/amd/pi/hudson + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI0 usb[0:3] is connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson + device pci 14.7 on end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index b5700f8..b6b22cf 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -21,73 +21,71 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.2 on end # LAN3 + device pci 2.3 on end # LAN2 + device pci 2.4 on end # LAN1 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 on - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 on - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - device pnp 2e.007 off end - device pnp 2e.107 off end - device pnp 2e.607 off end - device pnp 2e.e off end - end # SIO NCT5104D - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end # LPC TPM - end # LPC 0x439d + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI0 usb[0:3] is connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + device pnp 2e.007 off end + device pnp 2e.107 off end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM + end # LPC 0x439d - device pci 14.7 off end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson + device pci 14.7 off end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain end #northbridge/amd/pi/00730F01/root_complex -- To view, visit https://review.coreboot.org/c/coreboot/+/31271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic12481b637ee5f5119faec3239b477f613e4e511 Gerrit-Change-Number: 31271 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019